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1.1 root 1: /* sis900.h Definitions for SiS ethernet controllers including 7014/7016 and 900
2: * Copyright 1999 Silicon Integrated System Corporation
3: * References:
4: * SiS 7016 Fast Ethernet PCI Bus 10/100 Mbps LAN Controller with OnNow Support,
5: * preliminary Rev. 1.0 Jan. 14, 1998
6: * SiS 900 Fast Ethernet PCI Bus 10/100 Mbps LAN Single Chip with OnNow Support,
7: * preliminary Rev. 1.0 Nov. 10, 1998
8: * SiS 7014 Single Chip 100BASE-TX/10BASE-T Physical Layer Solution,
9: * preliminary Rev. 1.0 Jan. 18, 1998
10: * http://www.sis.com.tw/support/databook.htm
11: */
12:
13: /* MAC operationl registers of SiS 7016 and SiS 900 ehternet controller */
14: /* The I/O extent, SiS 900 needs 256 bytes of io address */
15: #define SIS900_TOTAL_SIZE 0x100
16:
17: /* Symbolic offsets to registers. */
18: enum sis900_registers {
19: cr=0x0, //Command Register
20: cfg=0x4, //Configuration Register
21: mear=0x8, //EEPROM Access Register
22: ptscr=0xc, //PCI Test Control Register
23: isr=0x10, //Interrupt Status Register
24: imr=0x14, //Interrupt Mask Register
25: ier=0x18, //Interrupt Enable Register
26: epar=0x18, //Enhanced PHY Access Register
27: txdp=0x20, //Transmit Descriptor Pointer Register
28: txcfg=0x24, //Transmit Configuration Register
29: rxdp=0x30, //Receive Descriptor Pointer Register
30: rxcfg=0x34, //Receive Configuration Register
31: flctrl=0x38, //Flow Control Register
32: rxlen=0x3c, //Receive Packet Length Register
33: rfcr=0x48, //Receive Filter Control Register
34: rfdr=0x4C, //Receive Filter Data Register
35: pmctrl=0xB0, //Power Management Control Register
36: pmer=0xB4 //Power Management Wake-up Event Register
37: };
38:
39: /* Symbolic names for bits in various registers */
40: enum sis900_command_register_bits {
41: RELOAD = 0x00000400, ACCESSMODE = 0x00000200,/* ET */
42: RESET = 0x00000100, SWI = 0x00000080, RxRESET = 0x00000020,
43: TxRESET = 0x00000010, RxDIS = 0x00000008, RxENA = 0x00000004,
44: TxDIS = 0x00000002, TxENA = 0x00000001
45: };
46:
47: enum sis900_configuration_register_bits {
48: DESCRFMT = 0x00000100 /* 7016 specific */, REQALG = 0x00000080,
49: SB = 0x00000040, POW = 0x00000020, EXD = 0x00000010,
50: PESEL = 0x00000008, LPM = 0x00000004, BEM = 0x00000001,
51: /* 635 & 900B Specific */
52: RND_CNT = 0x00000400, FAIR_BACKOFF = 0x00000200,
53: EDB_MASTER_EN = 0x00002000
54: };
55:
56: enum sis900_eeprom_access_reigster_bits {
57: MDC = 0x00000040, MDDIR = 0x00000020, MDIO = 0x00000010, /* 7016 specific */
58: EECS = 0x00000008, EECLK = 0x00000004, EEDO = 0x00000002,
59: EEDI = 0x00000001
60: };
61:
62: enum sis900_interrupt_register_bits {
63: WKEVT = 0x10000000, TxPAUSEEND = 0x08000000, TxPAUSE = 0x04000000,
64: TxRCMP = 0x02000000, RxRCMP = 0x01000000, DPERR = 0x00800000,
65: SSERR = 0x00400000, RMABT = 0x00200000, RTABT = 0x00100000,
66: RxSOVR = 0x00010000, HIBERR = 0x00008000, SWINT = 0x00001000,
67: MIBINT = 0x00000800, TxURN = 0x00000400, TxIDLE = 0x00000200,
68: TxERR = 0x00000100, TxDESC = 0x00000080, TxOK = 0x00000040,
69: RxORN = 0x00000020, RxIDLE = 0x00000010, RxEARLY = 0x00000008,
70: RxERR = 0x00000004, RxDESC = 0x00000002, RxOK = 0x00000001
71: };
72:
73: enum sis900_interrupt_enable_reigster_bits {
74: IE = 0x00000001
75: };
76:
77: /* maximum dma burst fro transmission and receive*/
78: #define MAX_DMA_RANGE 7 /* actually 0 means MAXIMUM !! */
79: #define TxMXDMA_shift 20
80: #define RxMXDMA_shift 20
81:
82: enum sis900_tx_rx_dma{
83: DMA_BURST_512 = 0, DMA_BURST_64 = 5
84: };
85:
86: /* transmit FIFO threshholds */
87: #define TX_FILL_THRESH 16 /* 1/4 FIFO size */
88: #define TxFILLT_shift 8
89: #define TxDRNT_shift 0
90: #define TxDRNT_100 48 /* 3/4 FIFO size */
91: #define TxDRNT_10 16 /* 1/2 FIFO size */
92:
93: enum sis900_transmit_config_register_bits {
94: TxCSI = 0x80000000, TxHBI = 0x40000000, TxMLB = 0x20000000,
95: TxATP = 0x10000000, TxIFG = 0x0C000000, TxFILLT = 0x00003F00,
96: TxDRNT = 0x0000003F
97: };
98:
99: /* recevie FIFO thresholds */
100: #define RxDRNT_shift 1
101: #define RxDRNT_100 16 /* 1/2 FIFO size */
102: #define RxDRNT_10 24 /* 3/4 FIFO size */
103:
104: enum sis900_reveive_config_register_bits {
105: RxAEP = 0x80000000, RxARP = 0x40000000, RxATX = 0x10000000,
106: RxAJAB = 0x08000000, RxDRNT = 0x0000007F
107: };
108:
109: #define RFAA_shift 28
110: #define RFADDR_shift 16
111:
112: enum sis900_receive_filter_control_register_bits {
113: RFEN = 0x80000000, RFAAB = 0x40000000, RFAAM = 0x20000000,
114: RFAAP = 0x10000000, RFPromiscuous = (RFAAB|RFAAM|RFAAP)
115: };
116:
117: enum sis900_reveive_filter_data_mask {
118: RFDAT = 0x0000FFFF
119: };
120:
121: /* EEPROM Addresses */
122: enum sis900_eeprom_address {
123: EEPROMSignature = 0x00, EEPROMVendorID = 0x02, EEPROMDeviceID = 0x03,
124: EEPROMMACAddr = 0x08, EEPROMChecksum = 0x0b
125: };
126:
127: /* The EEPROM commands include the alway-set leading bit. Refer to NM93Cxx datasheet */
128: enum sis900_eeprom_command {
129: EEread = 0x0180, EEwrite = 0x0140, EEerase = 0x01C0,
130: EEwriteEnable = 0x0130, EEwriteDisable = 0x0100,
131: EEeraseAll = 0x0120, EEwriteAll = 0x0110,
132: EEaddrMask = 0x013F, EEcmdShift = 16
133: };
134:
135: /* For SiS962, request the eeprom software access */
136: enum sis962_eeprom_command {
137: EEREQ = 0x00000400, EEDONE = 0x00000200, EEGNT = 0x00000100
138: };
139:
140: /* Manamgement Data I/O (mdio) frame */
141: #define MIIread 0x6000
142: #define MIIwrite 0x5002
143: #define MIIpmdShift 7
144: #define MIIregShift 2
145: #define MIIcmdLen 16
146: #define MIIcmdShift 16
147:
148: /* Buffer Descriptor Status*/
149: enum sis900_buffer_status {
150: OWN = 0x80000000, MORE = 0x40000000, INTR = 0x20000000,
151: SUPCRC = 0x10000000, INCCRC = 0x10000000,
152: OK = 0x08000000, DSIZE = 0x00000FFF
153: };
154: /* Status for TX Buffers */
155: enum sis900_tx_buffer_status {
156: ABORT = 0x04000000, UNDERRUN = 0x02000000, NOCARRIER = 0x01000000,
157: DEFERD = 0x00800000, EXCDEFER = 0x00400000, OWCOLL = 0x00200000,
158: EXCCOLL = 0x00100000, COLCNT = 0x000F0000
159: };
160:
161: enum sis900_rx_bufer_status {
162: OVERRUN = 0x02000000, DEST = 0x00800000, BCAST = 0x01800000,
163: MCAST = 0x01000000, UNIMATCH = 0x00800000, TOOLONG = 0x00400000,
164: RUNT = 0x00200000, RXISERR = 0x00100000, CRCERR = 0x00080000,
165: FAERR = 0x00040000, LOOPBK = 0x00020000, RXCOL = 0x00010000
166: };
167:
168: /* MII register offsets */
169: enum mii_registers {
170: MII_CONTROL = 0x0000, MII_STATUS = 0x0001, MII_PHY_ID0 = 0x0002,
171: MII_PHY_ID1 = 0x0003, MII_ANADV = 0x0004, MII_ANLPAR = 0x0005,
172: MII_ANEXT = 0x0006
173: };
174:
175: /* mii registers specific to SiS 900 */
176: enum sis_mii_registers {
177: MII_CONFIG1 = 0x0010, MII_CONFIG2 = 0x0011, MII_STSOUT = 0x0012,
178: MII_MASK = 0x0013, MII_RESV = 0x0014
179: };
180:
181: /* mii registers specific to ICS 1893 */
182: enum ics_mii_registers {
183: MII_EXTCTRL = 0x0010, MII_QPDSTS = 0x0011, MII_10BTOP = 0x0012,
184: MII_EXTCTRL2 = 0x0013
185: };
186:
187: /* mii registers specific to AMD 79C901 */
188: enum amd_mii_registers {
189: MII_STATUS_SUMMARY = 0x0018
190: };
191:
192: /* MII Control register bit definitions. */
193: enum mii_control_register_bits {
194: MII_CNTL_FDX = 0x0100, MII_CNTL_RST_AUTO = 0x0200,
195: MII_CNTL_ISOLATE = 0x0400, MII_CNTL_PWRDWN = 0x0800,
196: MII_CNTL_AUTO = 0x1000, MII_CNTL_SPEED = 0x2000,
197: MII_CNTL_LPBK = 0x4000, MII_CNTL_RESET = 0x8000
198: };
199:
200: /* MII Status register bit */
201: enum mii_status_register_bits {
202: MII_STAT_EXT = 0x0001, MII_STAT_JAB = 0x0002,
203: MII_STAT_LINK = 0x0004, MII_STAT_CAN_AUTO = 0x0008,
204: MII_STAT_FAULT = 0x0010, MII_STAT_AUTO_DONE = 0x0020,
205: MII_STAT_CAN_T = 0x0800, MII_STAT_CAN_T_FDX = 0x1000,
206: MII_STAT_CAN_TX = 0x2000, MII_STAT_CAN_TX_FDX = 0x4000,
207: MII_STAT_CAN_T4 = 0x8000
208: };
209:
210: #define MII_ID1_OUI_LO 0xFC00 /* low bits of OUI mask */
211: #define MII_ID1_MODEL 0x03F0 /* model number */
212: #define MII_ID1_REV 0x000F /* model number */
213:
214: /* MII NWAY Register Bits ...
215: valid for the ANAR (Auto-Negotiation Advertisement) and
216: ANLPAR (Auto-Negotiation Link Partner) registers */
217: enum mii_nway_register_bits {
218: MII_NWAY_NODE_SEL = 0x001f, MII_NWAY_CSMA_CD = 0x0001,
219: MII_NWAY_T = 0x0020, MII_NWAY_T_FDX = 0x0040,
220: MII_NWAY_TX = 0x0080, MII_NWAY_TX_FDX = 0x0100,
221: MII_NWAY_T4 = 0x0200, MII_NWAY_PAUSE = 0x0400,
222: MII_NWAY_RF = 0x2000, MII_NWAY_ACK = 0x4000,
223: MII_NWAY_NP = 0x8000
224: };
225:
226: enum mii_stsout_register_bits {
227: MII_STSOUT_LINK_FAIL = 0x4000,
228: MII_STSOUT_SPD = 0x0080, MII_STSOUT_DPLX = 0x0040
229: };
230:
231: enum mii_stsics_register_bits {
232: MII_STSICS_SPD = 0x8000, MII_STSICS_DPLX = 0x4000,
233: MII_STSICS_LINKSTS = 0x0001
234: };
235:
236: enum mii_stssum_register_bits {
237: MII_STSSUM_LINK = 0x0008, MII_STSSUM_DPLX = 0x0004,
238: MII_STSSUM_AUTO = 0x0002, MII_STSSUM_SPD = 0x0001
239: };
240:
241: enum sis900_revision_id {
242: SIS630A_900_REV = 0x80, SIS630E_900_REV = 0x81,
243: SIS630S_900_REV = 0x82, SIS630EA1_900_REV = 0x83,
244: SIS630ET_900_REV = 0x84, SIS635A_900_REV = 0x90,
245: SIS962_900_REV = 0X91, SIS900B_900_REV = 0x03
246: };
247:
248: enum sis630_revision_id {
249: SIS630A0 = 0x00, SIS630A1 = 0x01,
250: SIS630B0 = 0x10, SIS630B1 = 0x11
251: };
252:
253: #define FDX_CAPABLE_DUPLEX_UNKNOWN 0
254: #define FDX_CAPABLE_HALF_SELECTED 1
255: #define FDX_CAPABLE_FULL_SELECTED 2
256:
257: #define HW_SPEED_UNCONFIG 0
258: #define HW_SPEED_HOME 1
259: #define HW_SPEED_10_MBPS 10
260: #define HW_SPEED_100_MBPS 100
261: #define HW_SPEED_DEFAULT (HW_SPEED_100_MBPS)
262:
263: #define CRC_SIZE 4
264: #define MAC_HEADER_SIZE 14
265:
266: #define TX_BUF_SIZE 1536
267: #define RX_BUF_SIZE 1536
268:
269: #define NUM_TX_DESC 16 /* Number of Tx descriptor registers. */
270: #define NUM_RX_DESC 16 /* Number of Rx descriptor registers. */
271:
272: #define TRUE 1
273: #define FALSE 0
274:
275: /* PCI stuff, should be move to pic.h */
276: #define PCI_DEVICE_ID_SI_900 0x900
277: #define PCI_DEVICE_ID_SI_7016 0x7016
278: #define SIS630_VENDOR_ID 0x1039
279: #define SIS630_DEVICE_ID 0x0630
280:
281: /* ioctl for accessing MII transveiver */
282: #define SIOCGMIIPHY (SIOCDEVPRIVATE) /* Get the PHY in use. */
283: #define SIOCGMIIREG (SIOCDEVPRIVATE+1) /* Read a PHY register. */
284: #define SIOCSMIIREG (SIOCDEVPRIVATE+2) /* Write a PHY register */
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