![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to sk_g16.h CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [GnuMach] / Gnu-Mach / linux / src / drivers / net|
Return to sk_g16.h CVS log | Up to [GnuMach] / Gnu-Mach / linux / src / drivers / net |
1.1 root 1: /*-
2: *
3: * This software may be used and distributed according to the terms
4: * of the GNU Public License, incorporated herein by reference.
5: *
6: * Module : sk_g16.h
1.1.1.2 ! root 7: * Version : $Revision: 1.1.4.1 $
1.1 root 8: *
9: * Author : M.Hipp ([email protected])
10: * changes by : Patrick J.D. Weichmann
11: *
12: * Date Created : 94/05/25
13: *
14: * Description : In here are all necessary definitions of
15: * the am7990 (LANCE) chip used for writing a
16: * network device driver which uses this chip
17: *
18: -*/
19:
20: #ifndef SK_G16_H
21:
22: #define SK_G16_H
23:
24:
25: /*
26: * Control and Status Register 0 (CSR0) bit definitions
27: *
28: * (R=Readable) (W=Writeable) (S=Set on write) (C-Clear on write)
29: *
30: */
31:
32: #define CSR0_ERR 0x8000 /* Error summary (R) */
33: #define CSR0_BABL 0x4000 /* Babble transmitter timeout error (RC) */
34: #define CSR0_CERR 0x2000 /* Collision Error (RC) */
35: #define CSR0_MISS 0x1000 /* Missed packet (RC) */
36: #define CSR0_MERR 0x0800 /* Memory Error (RC) */
37: #define CSR0_RINT 0x0400 /* Receiver Interrupt (RC) */
38: #define CSR0_TINT 0x0200 /* Transmit Interrupt (RC) */
39: #define CSR0_IDON 0x0100 /* Initialization Done (RC) */
40: #define CSR0_INTR 0x0080 /* Interrupt Flag (R) */
41: #define CSR0_INEA 0x0040 /* Interrupt Enable (RW) */
42: #define CSR0_RXON 0x0020 /* Receiver on (R) */
43: #define CSR0_TXON 0x0010 /* Transmitter on (R) */
44: #define CSR0_TDMD 0x0008 /* Transmit Demand (RS) */
45: #define CSR0_STOP 0x0004 /* Stop (RS) */
46: #define CSR0_STRT 0x0002 /* Start (RS) */
47: #define CSR0_INIT 0x0001 /* Initialize (RS) */
48:
49: #define CSR0_CLRALL 0x7f00 /* mask for all clearable bits */
50:
51: /*
52: * Control and Status Register 3 (CSR3) bit definitions
53: *
54: */
55:
56: #define CSR3_BSWAP 0x0004 /* Byte Swap (RW) */
57: #define CSR3_ACON 0x0002 /* ALE Control (RW) */
58: #define CSR3_BCON 0x0001 /* Byte Control (RW) */
59:
60: /*
61: * Initialization Block Mode operation Bit Definitions.
62: */
63:
64: #define MODE_PROM 0x8000 /* Promiscuous Mode */
65: #define MODE_INTL 0x0040 /* Internal Loopback */
66: #define MODE_DRTY 0x0020 /* Disable Retry */
67: #define MODE_COLL 0x0010 /* Force Collision */
68: #define MODE_DTCR 0x0008 /* Disable Transmit CRC) */
69: #define MODE_LOOP 0x0004 /* Loopback */
70: #define MODE_DTX 0x0002 /* Disable the Transmitter */
71: #define MODE_DRX 0x0001 /* Disable the Receiver */
72:
73: #define MODE_NORMAL 0x0000 /* Normal operation mode */
74:
75: /*
76: * Receive message descriptor status bit definitions.
77: */
78:
79: #define RX_OWN 0x80 /* Owner bit 0 = host, 1 = lance */
80: #define RX_ERR 0x40 /* Error Summary */
81: #define RX_FRAM 0x20 /* Framing Error */
82: #define RX_OFLO 0x10 /* Overflow Error */
83: #define RX_CRC 0x08 /* CRC Error */
84: #define RX_BUFF 0x04 /* Buffer Error */
85: #define RX_STP 0x02 /* Start of Packet */
86: #define RX_ENP 0x01 /* End of Packet */
87:
88:
89: /*
90: * Transmit message descriptor status bit definitions.
91: */
92:
93: #define TX_OWN 0x80 /* Owner bit 0 = host, 1 = lance */
94: #define TX_ERR 0x40 /* Error Summary */
95: #define TX_MORE 0x10 /* More the 1 retry needed to Xmit */
96: #define TX_ONE 0x08 /* One retry needed to Xmit */
97: #define TX_DEF 0x04 /* Deferred */
98: #define TX_STP 0x02 /* Start of Packet */
99: #define TX_ENP 0x01 /* End of Packet */
100:
101: /*
102: * Transmit status (2) (valid if TX_ERR == 1)
103: */
104:
105: #define TX_BUFF 0x8000 /* Buffering error (no ENP) */
106: #define TX_UFLO 0x4000 /* Underflow (late memory) */
107: #define TX_LCOL 0x1000 /* Late collision */
108: #define TX_LCAR 0x0400 /* Loss of Carrier */
109: #define TX_RTRY 0x0200 /* Failed after 16 retransmissions */
110: #define TX_TDR 0x003f /* Time-domain-reflectometer-value */
111:
112:
113: /*
114: * Structures used for Communication with the LANCE
115: */
116:
117: /* LANCE Initialize Block */
118:
119: struct init_block
120: {
121: unsigned short mode; /* Mode Register */
122: unsigned char paddr[6]; /* Physical Address (MAC) */
123: unsigned char laddr[8]; /* Logical Filter Address (not used) */
124: unsigned int rdrp; /* Receive Descriptor Ring pointer */
125: unsigned int tdrp; /* Transmit Descriptor Ring pointer */
126: };
127:
128:
129: /* Receive Message Descriptor Entry */
130:
131: struct rmd
132: {
133: union
134: {
135: unsigned long buffer; /* Address of buffer */
136: struct
137: {
138: unsigned char unused[3];
139: unsigned volatile char status; /* Status Bits */
140: } s;
141: } u;
142: volatile short blen; /* Buffer Length (two's complement) */
143: unsigned short mlen; /* Message Byte Count */
144: };
145:
146:
147: /* Transmit Message Descriptor Entry */
148:
149: struct tmd
150: {
151: union
152: {
153: unsigned long buffer; /* Address of buffer */
154: struct
155: {
156: unsigned char unused[3];
157: unsigned volatile char status; /* Status Bits */
158: } s;
159: } u;
160: unsigned short blen; /* Buffer Length (two's complement) */
161: unsigned volatile short status2; /* Error Status Bits */
162: };
163:
164: #endif /* End of SK_G16_H */
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.