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1.1 root 1: /*
2: * NCR 53c{7,8}0x0 driver, header file
3: *
4: * Sponsored by
5: * iX Multiuser Multitasking Magazine
6: * Hannover, Germany
7: * [email protected]
8: *
9: * Copyright 1993, 1994, 1995 Drew Eckhardt
10: * Visionary Computing
11: * (Unix and Linux consulting and custom programming)
12: * [email protected]
13: * +1 (303) 786-7975
14: *
15: * TolerANT and SCSI SCRIPTS are registered trademarks of NCR Corporation.
16: *
17: * PRE-ALPHA
18: *
19: * For more information, please consult
20: *
21: * NCR 53C700/53C700-66
22: * SCSI I/O Processor
23: * Data Manual
24: *
25: * NCR 53C810
26: * PCI-SCSI I/O Processor
27: * Data Manual
28: *
29: * NCR Microelectronics
30: * 1635 Aeroplaza Drive
31: * Colorado Springs, CO 80916
32: * +1 (719) 578-3400
33: *
34: * Toll free literature number
35: * +1 (800) 334-5454
36: *
37: */
38:
39: #ifndef NCR53c7x0_H
40: #define NCR53c7x0_H
41: #if !defined(LINUX_1_2) && !defined(LINUX_1_3)
42: #include <linux/version.h>
43: #if LINUX_VERSION_CODE > 65536 + 3 * 256
44: #define LINUX_1_3
45: #else
46: #define LINUX_1_2
47: #endif
48: #endif
49:
50: /*
51: * Prevent name space pollution in hosts.c, and only provide the
52: * define we need to get the NCR53c7x0 driver into the host template
53: * array.
54: */
55:
56: #if defined(HOSTS_C) || defined(MODULE)
57: #include <scsi/scsicam.h>
58:
59: extern int NCR53c7xx_abort(Scsi_Cmnd *);
60: extern int NCR53c7xx_detect(Scsi_Host_Template *tpnt);
61: extern int NCR53c7xx_queue_command(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
62: extern int NCR53c7xx_reset(Scsi_Cmnd *, unsigned int);
63: #ifdef MODULE
64: extern int NCR53c7xx_release(struct Scsi_Host *);
65: #else
66: #define NCR53c7xx_release NULL
67: #endif
68:
69: #ifdef LINUX_1_2
70: #define NCR53c7xx {NULL, NULL, "NCR53c{7,8}xx (rel 17)", NCR53c7xx_detect,\
71: NULL, /* info */ NULL, /* command, deprecated */ NULL, \
72: NCR53c7xx_queue_command, NCR53c7xx_abort, NCR53c7xx_reset, \
73: NULL /* slave attach */, scsicam_bios_param, /* can queue */ 24, \
74: /* id */ 7, 127 /* old SG_ALL */, /* cmd per lun */ 3, \
75: /* present */ 0, /* unchecked isa dma */ 0, DISABLE_CLUSTERING}
76: #else
77: #define NCR53c7xx {NULL, NULL, NULL, NULL, \
78: "NCR53c{7,8}xx (rel 17)", NCR53c7xx_detect,\
79: NULL, /* info */ NULL, /* command, deprecated */ NULL, \
80: NCR53c7xx_queue_command, NCR53c7xx_abort, NCR53c7xx_reset, \
81: NULL /* slave attach */, scsicam_bios_param, /* can queue */ 24, \
82: /* id */ 7, 127 /* old SG_ALL */, /* cmd per lun */ 3, \
83: /* present */ 0, /* unchecked isa dma */ 0, DISABLE_CLUSTERING}
84: #endif
85:
86: #endif /* defined(HOSTS_C) || defined(MODULE) */
87:
88: #ifndef HOSTS_C
89: #ifdef LINUX_1_2
90: /*
91: * Change virtual addresses to physical addresses and vv.
92: * These are trivial on the 1:1 Linux/i386 mapping (but if we ever
93: * make the kernel segment mapped at 0, we need to do translation
94: * on the i386 as well)
95: */
96: extern inline unsigned long virt_to_phys(volatile void * address)
97: {
98: return (unsigned long) address;
99: }
100:
101: extern inline void * phys_to_virt(unsigned long address)
102: {
103: return (void *) address;
104: }
105:
106: /*
107: * IO bus memory addresses are also 1:1 with the physical address
108: */
109: #define virt_to_bus virt_to_phys
110: #define bus_to_virt phys_to_virt
111:
112: /*
113: * readX/writeX() are used to access memory mapped devices. On some
114: * architectures the memory mapped IO stuff needs to be accessed
115: * differently. On the x86 architecture, we just read/write the
116: * memory location directly.
117: */
118: #define readb(addr) (*(volatile unsigned char *) (addr))
119: #define readw(addr) (*(volatile unsigned short *) (addr))
120: #define readl(addr) (*(volatile unsigned int *) (addr))
121:
122: #define writeb(b,addr) ((*(volatile unsigned char *) (addr)) = (b))
123: #define writew(b,addr) ((*(volatile unsigned short *) (addr)) = (b))
124: #define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b))
125:
126: #define mb()
127:
128: #endif /* def LINUX_1_2 */
129:
130: /* Register addresses, ordered numerically */
131:
132: /* SCSI control 0 rw, default = 0xc0 */
133: #define SCNTL0_REG 0x00
134: #define SCNTL0_ARB1 0x80 /* 0 0 = simple arbitration */
135: #define SCNTL0_ARB2 0x40 /* 1 1 = full arbitration */
136: #define SCNTL0_STRT 0x20 /* Start Sequence */
137: #define SCNTL0_WATN 0x10 /* Select with ATN */
138: #define SCNTL0_EPC 0x08 /* Enable parity checking */
139: /* Bit 2 is reserved on 800 series chips */
140: #define SCNTL0_EPG_700 0x04 /* Enable parity generation */
141: #define SCNTL0_AAP 0x02 /* ATN/ on parity error */
142: #define SCNTL0_TRG 0x01 /* Target mode */
143:
144: /* SCSI control 1 rw, default = 0x00 */
145:
146: #define SCNTL1_REG 0x01
147: #define SCNTL1_EXC 0x80 /* Extra Clock Cycle of Data setup */
148: #define SCNTL1_ADB 0x40 /* contents of SODL on bus */
149: #define SCNTL1_ESR_700 0x20 /* Enable SIOP response to selection
150: and reselection */
151: #define SCNTL1_DHP_800 0x20 /* Disable halt on parity error or ATN
152: target mode only */
153: #define SCNTL1_CON 0x10 /* Connected */
154: #define SCNTL1_RST 0x08 /* SCSI RST/ */
155: #define SCNTL1_AESP 0x04 /* Force bad parity */
156: #define SCNTL1_SND_700 0x02 /* Start SCSI send */
157: #define SCNTL1_IARB_800 0x02 /* Immediate Arbitration, start
158: arbitration immediately after
159: busfree is detected */
160: #define SCNTL1_RCV_700 0x01 /* Start SCSI receive */
161: #define SCNTL1_SST_800 0x01 /* Start SCSI transfer */
162:
163: /* SCSI control 2 rw, */
164:
165: #define SCNTL2_REG_800 0x02
166: #define SCNTL2_800_SDU 0x80 /* SCSI disconnect unexpected */
167:
168: /* SCSI control 3 rw */
169:
170: #define SCNTL3_REG_800 0x03
171: #define SCNTL3_800_SCF_SHIFT 4
172: #define SCNTL3_800_SCF_MASK 0x70
173: #define SCNTL3_800_SCF2 0x40 /* Synchronous divisor */
174: #define SCNTL3_800_SCF1 0x20 /* 0x00 = SCLK/3 */
175: #define SCNTL3_800_SCF0 0x10 /* 0x10 = SCLK/1 */
176: /* 0x20 = SCLK/1.5
177: 0x30 = SCLK/2
178: 0x40 = SCLK/3 */
179:
180: #define SCNTL3_800_CCF_SHIFT 0
181: #define SCNTL3_800_CCF_MASK 0x07
182: #define SCNTL3_800_CCF2 0x04 /* 0x00 50.01 to 66 */
183: #define SCNTL3_800_CCF1 0x02 /* 0x01 16.67 to 25 */
184: #define SCNTL3_800_CCF0 0x01 /* 0x02 25.01 - 37.5
185: 0x03 37.51 - 50
186: 0x04 50.01 - 66 */
187:
188: /*
189: * SCSI destination ID rw - the appropriate bit is set for the selected
190: * target ID. This is written by the SCSI SCRIPTS processor.
191: * default = 0x00
192: */
193: #define SDID_REG_700 0x02
194: #define SDID_REG_800 0x06
195:
196: #define GP_REG_800 0x07 /* General purpose IO */
197: #define GP_800_IO1 0x02
198: #define GP_800_IO2 0x01
199:
200:
201: /* SCSI interrupt enable rw, default = 0x00 */
202: #define SIEN_REG_700 0x03
203: #define SIEN0_REG_800 0x40
204: #define SIEN_MA 0x80 /* Phase mismatch (ini) or ATN (tgt) */
205: #define SIEN_FC 0x40 /* Function complete */
206: #define SIEN_700_STO 0x20 /* Selection or reselection timeout */
207: #define SIEN_800_SEL 0x20 /* Selected */
208: #define SIEN_700_SEL 0x10 /* Selected or reselected */
209: #define SIEN_800_RESEL 0x10 /* Reselected */
210: #define SIEN_SGE 0x08 /* SCSI gross error */
211: #define SIEN_UDC 0x04 /* Unexpected disconnect */
212: #define SIEN_RST 0x02 /* SCSI RST/ received */
213: #define SIEN_PAR 0x01 /* Parity error */
214:
215: /*
216: * SCSI chip ID rw
217: * NCR53c700 :
218: * When arbitrating, the highest bit is used, when reselection or selection
219: * occurs, the chip responds to all IDs for which a bit is set.
220: * default = 0x00
221: * NCR53c810 :
222: * Uses bit mapping
223: */
224: #define SCID_REG 0x04
225: /* Bit 7 is reserved on 800 series chips */
226: #define SCID_800_RRE 0x40 /* Enable response to reselection */
227: #define SCID_800_SRE 0x20 /* Enable response to selection */
228: /* Bits four and three are reserved on 800 series chips */
229: #define SCID_800_ENC_MASK 0x07 /* Encoded SCSI ID */
230:
231: /* SCSI transfer rw, default = 0x00 */
232: #define SXFER_REG 0x05
233: #define SXFER_DHP 0x80 /* Disable halt on parity */
234:
235: #define SXFER_TP2 0x40 /* Transfer period msb */
236: #define SXFER_TP1 0x20
237: #define SXFER_TP0 0x10 /* lsb */
238: #define SXFER_TP_MASK 0x70
239: /* FIXME : SXFER_TP_SHIFT == 5 is right for '8xx chips */
240: #define SXFER_TP_SHIFT 5
241: #define SXFER_TP_4 0x00 /* Divisors */
242: #define SXFER_TP_5 0x10<<1
243: #define SXFER_TP_6 0x20<<1
244: #define SXFER_TP_7 0x30<<1
245: #define SXFER_TP_8 0x40<<1
246: #define SXFER_TP_9 0x50<<1
247: #define SXFER_TP_10 0x60<<1
248: #define SXFER_TP_11 0x70<<1
249:
250: #define SXFER_MO3 0x08 /* Max offset msb */
251: #define SXFER_MO2 0x04
252: #define SXFER_MO1 0x02
253: #define SXFER_MO0 0x01 /* lsb */
254: #define SXFER_MO_MASK 0x0f
255: #define SXFER_MO_SHIFT 0
256:
257: /*
258: * SCSI output data latch rw
259: * The contents of this register are driven onto the SCSI bus when
260: * the Assert Data Bus bit of the SCNTL1 register is set and
261: * the CD, IO, and MSG bits of the SOCL register match the SCSI phase
262: */
263: #define SODL_REG_700 0x06
264: #define SODL_REG_800 0x54
265:
266:
267: /*
268: * SCSI output control latch rw, default = 0
269: * Note that when the chip is being manually programmed as an initiator,
270: * the MSG, CD, and IO bits must be set correctly for the phase the target
271: * is driving the bus in. Otherwise no data transfer will occur due to
272: * phase mismatch.
273: */
274:
275: #define SBCL_REG 0x0b
276: #define SBCL_REQ 0x80 /* REQ */
277: #define SBCL_ACK 0x40 /* ACK */
278: #define SBCL_BSY 0x20 /* BSY */
279: #define SBCL_SEL 0x10 /* SEL */
280: #define SBCL_ATN 0x08 /* ATN */
281: #define SBCL_MSG 0x04 /* MSG */
282: #define SBCL_CD 0x02 /* C/D */
283: #define SBCL_IO 0x01 /* I/O */
284: #define SBCL_PHASE_CMDOUT SBCL_CD
285: #define SBCL_PHASE_DATAIN SBCL_IO
286: #define SBCL_PHASE_DATAOUT 0
287: #define SBCL_PHASE_MSGIN (SBCL_CD|SBCL_IO|SBCL_MSG)
288: #define SBCL_PHASE_MSGOUT (SBCL_CD|SBCL_MSG)
289: #define SBCL_PHASE_STATIN (SBCL_CD|SBCL_IO)
290: #define SBCL_PHASE_MASK (SBCL_CD|SBCL_IO|SBCL_MSG)
291:
292: /*
293: * SCSI first byte received latch ro
294: * This register contains the first byte received during a block MOVE
295: * SCSI SCRIPTS instruction, including
296: *
297: * Initiator mode Target mode
298: * Message in Command
299: * Status Message out
300: * Data in Data out
301: *
302: * It also contains the selecting or reselecting device's ID and our
303: * ID.
304: *
305: * Note that this is the register the various IF conditionals can
306: * operate on.
307: */
308: #define SFBR_REG 0x08
309:
310: /*
311: * SCSI input data latch ro
312: * In initiator mode, data is latched into this register on the rising
313: * edge of REQ/. In target mode, data is latched on the rising edge of
314: * ACK/
315: */
316: #define SIDL_REG_700 0x09
317: #define SIDL_REG_800 0x50
318:
319: /*
320: * SCSI bus data lines ro
321: * This register reflects the instantaneous status of the SCSI data
322: * lines. Note that SCNTL0 must be set to disable parity checking,
323: * otherwise reading this register will latch new parity.
324: */
325: #define SBDL_REG_700 0x0a
326: #define SBDL_REG_800 0x58
327:
328: #define SSID_REG_800 0x0a
329: #define SSID_800_VAL 0x80 /* Exactly two bits asserted at sel */
330: #define SSID_800_ENCID_MASK 0x07 /* Device which performed operation */
331:
332:
333: /*
334: * SCSI bus control lines rw,
335: * instantaneous readout of control lines
336: */
337: #define SOCL_REG 0x0b
338: #define SOCL_REQ 0x80 /* REQ ro */
339: #define SOCL_ACK 0x40 /* ACK ro */
340: #define SOCL_BSY 0x20 /* BSY ro */
341: #define SOCL_SEL 0x10 /* SEL ro */
342: #define SOCL_ATN 0x08 /* ATN ro */
343: #define SOCL_MSG 0x04 /* MSG ro */
344: #define SOCL_CD 0x02 /* C/D ro */
345: #define SOCL_IO 0x01 /* I/O ro */
346: /*
347: * Synchronous SCSI Clock Control bits
348: * 0 - set by DCNTL
349: * 1 - SCLK / 1.0
350: * 2 - SCLK / 1.5
351: * 3 - SCLK / 2.0
352: */
353: #define SBCL_SSCF1 0x02 /* wo, -66 only */
354: #define SBCL_SSCF0 0x01 /* wo, -66 only */
355: #define SBCL_SSCF_MASK 0x03
356:
357: /*
358: * XXX note : when reading the DSTAT and STAT registers to clear interrupts,
359: * insure that 10 clocks elapse between the two
360: */
361: /* DMA status ro */
362: #define DSTAT_REG 0x0c
363: #define DSTAT_DFE 0x80 /* DMA FIFO empty */
364: #define DSTAT_800_MDPE 0x40 /* Master Data Parity Error */
365: #define DSTAT_800_BF 0x20 /* Bus Fault */
366: #define DSTAT_ABRT 0x10 /* Aborted - set on error */
367: #define DSTAT_SSI 0x08 /* SCRIPTS single step interrupt */
368: #define DSTAT_SIR 0x04 /* SCRIPTS interrupt received -
369: set when INT instruction is
370: executed */
371: #define DSTAT_WTD 0x02 /* Watchdog timeout detected */
372: #define DSTAT_OPC 0x01 /* Illegal instruction */
373: #define DSTAT_800_IID 0x01 /* Same thing, different name */
374:
375:
376: /* NCR53c800 moves this stuff into SIST0 */
377: #define SSTAT0_REG 0x0d /* SCSI status 0 ro */
378: #define SIST0_REG_800 0x42
379: #define SSTAT0_MA 0x80 /* ini : phase mismatch,
380: * tgt : ATN/ asserted
381: */
382: #define SSTAT0_CMP 0x40 /* function complete */
383: #define SSTAT0_700_STO 0x20 /* Selection or reselection timeout */
384: #define SIST0_800_SEL 0x20 /* Selected */
385: #define SSTAT0_700_SEL 0x10 /* Selected or reselected */
386: #define SIST0_800_RSL 0x10 /* Reselected */
387: #define SSTAT0_SGE 0x08 /* SCSI gross error */
388: #define SSTAT0_UDC 0x04 /* Unexpected disconnect */
389: #define SSTAT0_RST 0x02 /* SCSI RST/ received */
390: #define SSTAT0_PAR 0x01 /* Parity error */
391:
392: /* And uses SSTAT0 for what was SSTAT1 */
393:
394: #define SSTAT1_REG 0x0e /* SCSI status 1 ro */
395: #define SSTAT1_ILF 0x80 /* SIDL full */
396: #define SSTAT1_ORF 0x40 /* SODR full */
397: #define SSTAT1_OLF 0x20 /* SODL full */
398: #define SSTAT1_AIP 0x10 /* Arbitration in progress */
399: #define SSTAT1_LOA 0x08 /* Lost arbitration */
400: #define SSTAT1_WOA 0x04 /* Won arbitration */
401: #define SSTAT1_RST 0x02 /* Instant readout of RST/ */
402: #define SSTAT1_SDP 0x01 /* Instant readout of SDP/ */
403:
404: #define SSTAT2_REG 0x0f /* SCSI status 2 ro */
405: #define SSTAT2_FF3 0x80 /* number of bytes in synchronous */
406: #define SSTAT2_FF2 0x40 /* data FIFO */
407: #define SSTAT2_FF1 0x20
408: #define SSTAT2_FF0 0x10
409: #define SSTAT2_FF_MASK 0xf0
410: #define SSTAT2_FF_SHIFT 4
411:
412: /*
413: * Latched signals, latched on the leading edge of REQ/ for initiators,
414: * ACK/ for targets.
415: */
416: #define SSTAT2_SDP 0x08 /* SDP */
417: #define SSTAT2_MSG 0x04 /* MSG */
418: #define SSTAT2_CD 0x02 /* C/D */
419: #define SSTAT2_IO 0x01 /* I/O */
420: #define SSTAT2_PHASE_CMDOUT SSTAT2_CD
421: #define SSTAT2_PHASE_DATAIN SSTAT2_IO
422: #define SSTAT2_PHASE_DATAOUT 0
423: #define SSTAT2_PHASE_MSGIN (SSTAT2_CD|SSTAT2_IO|SSTAT2_MSG)
424: #define SSTAT2_PHASE_MSGOUT (SSTAT2_CD|SSTAT2_MSG)
425: #define SSTAT2_PHASE_STATIN (SSTAT2_CD|SSTAT2_IO)
426: #define SSTAT2_PHASE_MASK (SSTAT2_CD|SSTAT2_IO|SSTAT2_MSG)
427:
428:
429: /* NCR53c700-66 only */
430: #define SCRATCHA_REG_00 0x10 /* through 0x13 Scratch A rw */
431: /* NCR53c710 and higher */
432: #define DSA_REG 0x10 /* DATA structure address */
433:
434: #define CTEST0_REG_700 0x14 /* Chip test 0 ro */
435: #define CTEST0_REG_800 0x18 /* Chip test 0 rw, general purpose */
436: /* 0x80 - 0x04 are reserved */
437: #define CTEST0_700_RTRG 0x02 /* Real target mode */
438: #define CTEST0_700_DDIR 0x01 /* Data direction, 1 =
439: * SCSI bus to host, 0 =
440: * host to SCSI.
441: */
442:
443: #define CTEST1_REG_700 0x15 /* Chip test 1 ro */
444: #define CTEST1_REG_800 0x19 /* Chip test 1 ro */
445: #define CTEST1_FMT3 0x80 /* Identify which byte lanes are empty */
446: #define CTEST1_FMT2 0x40 /* in the DMA FIFO */
447: #define CTEST1_FMT1 0x20
448: #define CTEST1_FMT0 0x10
449:
450: #define CTEST1_FFL3 0x08 /* Identify which bytes lanes are full */
451: #define CTEST1_FFL2 0x04 /* in the DMA FIFO */
452: #define CTEST1_FFL1 0x02
453: #define CTEST1_FFL0 0x01
454:
455: #define CTEST2_REG_700 0x16 /* Chip test 2 ro */
456: #define CTEST2_REG_800 0x1a /* Chip test 2 ro */
457:
458: #define CTEST2_800_DDIR 0x80 /* 1 = SCSI->host */
459: #define CTEST2_800_SIGP 0x40 /* A copy of SIGP in ISTAT.
460: Reading this register clears */
461: #define CTEST2_800_CIO 0x20 /* Configured as IO */.
462: #define CTEST2_800_CM 0x10 /* Configured as memory */
463:
464: /* 0x80 - 0x40 are reserved on 700 series chips */
465: #define CTEST2_700_SOFF 0x20 /* SCSI Offset Compare,
466: * As an initiator, this bit is
467: * one when the synchronous offset
468: * is zero, as a target this bit
469: * is one when the synchronous
470: * offset is at the maximum
471: * defined in SXFER
472: */
473: #define CTEST2_700_SFP 0x10 /* SCSI FIFO parity bit,
474: * reading CTEST3 unloads a byte
475: * from the FIFO and sets this
476: */
477: #define CTEST2_700_DFP 0x08 /* DMA FIFO parity bit,
478: * reading CTEST6 unloads a byte
479: * from the FIFO and sets this
480: */
481: #define CTEST2_TEOP 0x04 /* SCSI true end of process,
482: * indicates a totally finished
483: * transfer
484: */
485: #define CTEST2_DREQ 0x02 /* Data request signal */
486: /* 0x01 is reserved on 700 series chips */
487: #define CTEST2_800_DACK 0x01
488:
489: /*
490: * Chip test 3 ro
491: * Unloads the bottom byte of the eight deep SCSI synchronous FIFO,
492: * check SSTAT2 FIFO full bits to determine size. Note that a GROSS
493: * error results if a read is attempted on this register. Also note
494: * that 16 and 32 bit reads of this register will cause corruption.
495: */
496: #define CTEST3_REG_700 0x17
497: /* Chip test 3 rw */
498: #define CTEST3_REG_800 0x1b
499: #define CTEST3_800_V3 0x80 /* Chip revision */
500: #define CTEST3_800_V2 0x40
501: #define CTEST3_800_V1 0x20
502: #define CTEST3_800_V0 0x10
503: #define CTEST3_800_FLF 0x08 /* Flush DMA FIFO */
504: #define CTEST3_800_CLF 0x04 /* Clear DMA FIFO */
505: #define CTEST3_800_FM 0x02 /* Fetch mode pin */
506: /* bit 0 is reserved on 800 series chips */
507:
508: #define CTEST4_REG_700 0x18 /* Chip test 4 rw */
509: #define CTEST4_REG_800 0x21 /* Chip test 4 rw */
510: /* 0x80 is reserved on 700 series chips */
511: #define CTEST4_800_BDIS 0x80 /* Burst mode disable */
512: #define CTEST4_ZMOD 0x40 /* High impedance mode */
513: #define CTEST4_SZM 0x20 /* SCSI bus high impedance */
514: #define CTEST4_700_SLBE 0x10 /* SCSI loopback enabled */
515: #define CTEST4_800_SRTM 0x10 /* Shadow Register Test Mode */
516: #define CTEST4_700_SFWR 0x08 /* SCSI FIFO write enable,
517: * redirects writes from SODL
518: * to the SCSI FIFO.
519: */
520: #define CTEST4_800_MPEE 0x08 /* Enable parity checking
521: during master cycles on PCI
522: bus */
523:
524: /*
525: * These bits send the contents of the CTEST6 register to the appropriate
526: * byte lane of the 32 bit DMA FIFO. Normal operation is zero, otherwise
527: * the high bit means the low two bits select the byte lane.
528: */
529: #define CTEST4_FBL2 0x04
530: #define CTEST4_FBL1 0x02
531: #define CTEST4_FBL0 0x01
532: #define CTEST4_FBL_MASK 0x07
533: #define CTEST4_FBL_0 0x04 /* Select DMA FIFO byte lane 0 */
534: #define CTEST4_FBL_1 0x05 /* Select DMA FIFO byte lane 1 */
535: #define CTEST4_FBL_2 0x06 /* Select DMA FIFO byte lane 2 */
536: #define CTEST4_FBL_3 0x07 /* Select DMA FIFO byte lane 3 */
537: #define CTEST4_800_SAVE (CTEST4_800_BDIS)
538:
539:
540: #define CTEST5_REG_700 0x19 /* Chip test 5 rw */
541: #define CTEST5_REG_800 0x22 /* Chip test 5 rw */
542: /*
543: * Clock Address Incrementor. When set, it increments the
544: * DNAD register to the next bus size boundary. It automatically
545: * resets itself when the operation is complete.
546: */
547: #define CTEST5_ADCK 0x80
548: /*
549: * Clock Byte Counter. When set, it decrements the DBC register to
550: * the next bus size boundary.
551: */
552: #define CTEST5_BBCK 0x40
553: /*
554: * Reset SCSI Offset. Setting this bit to 1 clears the current offset
555: * pointer in the SCSI synchronous offset counter (SSTAT). This bit
556: * is set to 1 if a SCSI Gross Error Condition occurs. The offset should
557: * be cleared when a synchronous transfer fails. When written, it is
558: * automatically cleared after the SCSI synchronous offset counter is
559: * reset.
560: */
561: /* Bit 5 is reserved on 800 series chips */
562: #define CTEST5_700_ROFF 0x20
563: /*
564: * Master Control for Set or Reset pulses. When 1, causes the low
565: * four bits of register to set when set, 0 causes the low bits to
566: * clear when set.
567: */
568: #define CTEST5_MASR 0x10
569: #define CTEST5_DDIR 0x08 /* DMA direction */
570: /*
571: * Bits 2-0 are reserved on 800 series chips
572: */
573: #define CTEST5_700_EOP 0x04 /* End of process */
574: #define CTEST5_700_DREQ 0x02 /* Data request */
575: #define CTEST5_700_DACK 0x01 /* Data acknowledge */
576:
577: /*
578: * Chip test 6 rw - writing to this register writes to the byte
579: * lane in the DMA FIFO as determined by the FBL bits in the CTEST4
580: * register.
581: */
582: #define CTEST6_REG_700 0x1a
583: #define CTEST6_REG_800 0x23
584:
585: #define CTEST7_REG 0x1b /* Chip test 7 rw */
586: /* 0x80 - 0x40 are reserved on NCR53c700 and NCR53c700-66 chips */
587: #define CTEST7_10_CDIS 0x80 /* Cache burst disable */
588: #define CTEST7_10_SC1 0x40 /* Snoop control bits */
589: #define CTEST7_10_SC0 0x20
590: #define CTEST7_10_SC_MASK 0x60
591: /* 0x20 is reserved on the NCR53c700 */
592: #define CTEST7_0060_FM 0x20 /* Fetch mode */
593: #define CTEST7_STD 0x10 /* Selection timeout disable */
594: #define CTEST7_DFP 0x08 /* DMA FIFO parity bit for CTEST6 */
595: #define CTEST7_EVP 0x04 /* 1 = host bus even parity, 0 = odd */
596: #define CTEST7_10_TT1 0x02 /* Transfer type */
597: #define CTEST7_00_DC 0x02 /* Set to drive DC low during instruction
598: fetch */
599: #define CTEST7_DIFF 0x01 /* Differential mode */
600:
601: #define CTEST7_SAVE ( CTEST7_EVP | CTEST7_DIFF )
602:
603:
604: #define TEMP_REG 0x1c /* through 0x1f Temporary stack rw */
605:
606: #define DFIFO_REG 0x20 /* DMA FIFO rw */
607: /*
608: * 0x80 is reserved on the NCR53c710, the CLF and FLF bits have been
609: * moved into the CTEST8 register.
610: */
611: #define DFIFO_00_FLF 0x80 /* Flush DMA FIFO to memory */
612: #define DFIFO_00_CLF 0x40 /* Clear DMA and SCSI FIFOs */
613: #define DFIFO_BO6 0x40
614: #define DFIFO_BO5 0x20
615: #define DFIFO_BO4 0x10
616: #define DFIFO_BO3 0x08
617: #define DFIFO_BO2 0x04
618: #define DFIFO_BO1 0x02
619: #define DFIFO_BO0 0x01
620: #define DFIFO_10_BO_MASK 0x7f /* 7 bit counter */
621: #define DFIFO_00_BO_MASK 0x3f /* 6 bit counter */
622:
623: /*
624: * Interrupt status rw
625: * Note that this is the only register which can be read while SCSI
626: * SCRIPTS are being executed.
627: */
628: #define ISTAT_REG_700 0x21
629: #define ISTAT_REG_800 0x14
630: #define ISTAT_ABRT 0x80 /* Software abort, write
631: *1 to abort, wait for interrupt. */
632: /* 0x40 and 0x20 are reserved on NCR53c700 and NCR53c700-66 chips */
633: #define ISTAT_10_SRST 0x40 /* software reset */
634: #define ISTAT_10_SIGP 0x20 /* signal script */
635: /* 0x10 is reserved on NCR53c700 series chips */
636: #define ISTAT_800_SEM 0x10 /* semaphore */
637: #define ISTAT_CON 0x08 /* 1 when connected */
638: #define ISTAT_800_INTF 0x04 /* Interrupt on the fly */
639: #define ISTAT_700_PRE 0x04 /* Pointer register empty.
640: * Set to 1 when DSPS and DSP
641: * registers are empty in pipeline
642: * mode, always set otherwise.
643: */
644: #define ISTAT_SIP 0x02 /* SCSI interrupt pending from
645: * SCSI portion of SIOP see
646: * SSTAT0
647: */
648: #define ISTAT_DIP 0x01 /* DMA interrupt pending
649: * see DSTAT
650: */
651:
652: /* NCR53c700-66 and NCR53c710 only */
653: #define CTEST8_REG 0x22 /* Chip test 8 rw */
654: #define CTEST8_0066_EAS 0x80 /* Enable alternate SCSI clock,
655: * ie read from SCLK/ rather than CLK/
656: */
657: #define CTEST8_0066_EFM 0x40 /* Enable fetch and master outputs */
658: #define CTEST8_0066_GRP 0x20 /* Generate Receive Parity for
659: * pass through. This insures that
660: * bad parity won't reach the host
661: * bus.
662: */
663: #define CTEST8_0066_TE 0x10 /* TolerANT enable. Enable
664: * active negation, should only
665: * be used for slow SCSI
666: * non-differential.
667: */
668: #define CTEST8_0066_HSC 0x08 /* Halt SCSI clock */
669: #define CTEST8_0066_SRA 0x04 /* Shorten REQ/ACK filtering,
670: * must be set for fast SCSI-II
671: * speeds.
672: */
673: #define CTEST8_0066_DAS 0x02 /* Disable automatic target/initiator
674: * switching.
675: */
676: #define CTEST8_0066_LDE 0x01 /* Last disconnect enable.
677: * The status of pending
678: * disconnect is maintained by
679: * the core, eliminating
680: * the possibility of missing a
681: * selection or reselection
682: * while waiting to fetch a
683: * WAIT DISCONNECT opcode.
684: */
685:
686: #define CTEST8_10_V3 0x80 /* Chip revision */
687: #define CTEST8_10_V2 0x40
688: #define CTEST8_10_V1 0x20
689: #define CTEST8_10_V0 0x10
690: #define CTEST8_10_V_MASK 0xf0
691: #define CTEST8_10_FLF 0x08 /* Flush FIFOs */
692: #define CTEST8_10_CLF 0x04 /* Clear FIFOs */
693: #define CTEST8_10_FM 0x02 /* Fetch pin mode */
694: #define CTEST8_10_SM 0x01 /* Snoop pin mode */
695:
696:
697: /*
698: * The CTEST9 register may be used to differentiate between a
699: * NCR53c700 and a NCR53c710.
700: *
701: * Write 0xff to this register.
702: * Read it.
703: * If the contents are 0xff, it is a NCR53c700
704: * If the contents are 0x00, it is a NCR53c700-66 first revision
705: * If the contents are some other value, it is some other NCR53c700-66
706: */
707: #define CTEST9_REG_00 0x23 /* Chip test 9 ro */
708: #define LCRC_REG_10 0x23
709:
710: /*
711: * 0x24 through 0x27 are the DMA byte counter register. Instructions
712: * write their high 8 bits into the DCMD register, the low 24 bits into
713: * the DBC register.
714: *
715: * Function is dependent on the command type being executed.
716: */
717:
718:
719: #define DBC_REG 0x24
720: /*
721: * For Block Move Instructions, DBC is a 24 bit quantity representing
722: * the number of bytes to transfer.
723: * For Transfer Control Instructions, DBC is bit fielded as follows :
724: */
725: /* Bits 20 - 23 should be clear */
726: #define DBC_TCI_TRUE (1 << 19) /* Jump when true */
727: #define DBC_TCI_COMPARE_DATA (1 << 18) /* Compare data */
728: #define DBC_TCI_COMPARE_PHASE (1 << 17) /* Compare phase with DCMD field */
729: #define DBC_TCI_WAIT_FOR_VALID (1 << 16) /* Wait for REQ */
730: /* Bits 8 - 15 are reserved on some implementations ? */
731: #define DBC_TCI_MASK_MASK 0xff00 /* Mask for data compare */
732: #define DBC_TCI_MASK_SHIFT 8
733: #define DBC_TCI_DATA_MASK 0xff /* Data to be compared */
734: #define DBC_TCI_DATA_SHIFT 0
735:
736: #define DBC_RWRI_IMMEDIATE_MASK 0xff00 /* Immediate data */
737: #define DBC_RWRI_IMMEDIATE_SHIFT 8 /* Amount to shift */
738: #define DBC_RWRI_ADDRESS_MASK 0x3f0000 /* Register address */
739: #define DBC_RWRI_ADDRESS_SHIFT 16
740:
741:
742: /*
743: * DMA command r/w
744: */
745: #define DCMD_REG 0x27
746: #define DCMD_TYPE_MASK 0xc0 /* Masks off type */
747: #define DCMD_TYPE_BMI 0x00 /* Indicates a Block Move instruction */
748: #define DCMD_BMI_IO 0x01 /* I/O, CD, and MSG bits selecting */
749: #define DCMD_BMI_CD 0x02 /* the phase for the block MOVE */
750: #define DCMD_BMI_MSG 0x04 /* instruction */
751:
752: #define DCMD_BMI_OP_MASK 0x18 /* mask for opcode */
753: #define DCMD_BMI_OP_MOVE_T 0x00 /* MOVE */
754: #define DCMD_BMI_OP_MOVE_I 0x08 /* MOVE Initiator */
755:
756: #define DCMD_BMI_INDIRECT 0x20 /* Indirect addressing */
757:
758: #define DCMD_TYPE_TCI 0x80 /* Indicates a Transfer Control
759: instruction */
760: #define DCMD_TCI_IO 0x01 /* I/O, CD, and MSG bits selecting */
761: #define DCMD_TCI_CD 0x02 /* the phase for the block MOVE */
762: #define DCMD_TCI_MSG 0x04 /* instruction */
763: #define DCMD_TCI_OP_MASK 0x38 /* mask for opcode */
764: #define DCMD_TCI_OP_JUMP 0x00 /* JUMP */
765: #define DCMD_TCI_OP_CALL 0x08 /* CALL */
766: #define DCMD_TCI_OP_RETURN 0x10 /* RETURN */
767: #define DCMD_TCI_OP_INT 0x18 /* INT */
768:
769: #define DCMD_TYPE_RWRI 0x40 /* Indicates I/O or register Read/Write
770: instruction */
771: #define DCMD_RWRI_OPC_MASK 0x38 /* Opcode mask */
772: #define DCMD_RWRI_OPC_WRITE 0x28 /* Write SFBR to register */
773: #define DCMD_RWRI_OPC_READ 0x30 /* Read register to SFBR */
774: #define DCMD_RWRI_OPC_MODIFY 0x38 /* Modify in place */
775:
776: #define DCMD_RWRI_OP_MASK 0x07
777: #define DCMD_RWRI_OP_MOVE 0x00
778: #define DCMD_RWRI_OP_SHL 0x01
779: #define DCMD_RWRI_OP_OR 0x02
780: #define DCMD_RWRI_OP_XOR 0x03
781: #define DCMD_RWRI_OP_AND 0x04
782: #define DCMD_RWRI_OP_SHR 0x05
783: #define DCMD_RWRI_OP_ADD 0x06
784: #define DCMD_RWRI_OP_ADDC 0x07
785:
786: #define DCMD_TYPE_MMI 0xc0 /* Indicates a Memory Move instruction
787: (three words) */
788:
789:
790: #define DNAD_REG 0x28 /* through 0x2b DMA next address for
791: data */
792: #define DSP_REG 0x2c /* through 0x2f DMA SCRIPTS pointer rw */
793: #define DSPS_REG 0x30 /* through 0x33 DMA SCRIPTS pointer
794: save rw */
795: #define DMODE_REG_00 0x34 /* DMA mode rw */
796: #define DMODE_00_BL1 0x80 /* Burst length bits */
797: #define DMODE_00_BL0 0x40
798: #define DMODE_BL_MASK 0xc0
799: /* Burst lengths (800) */
800: #define DMODE_BL_2 0x00 /* 2 transfer */
801: #define DMODE_BL_4 0x40 /* 4 transfers */
802: #define DMODE_BL_8 0x80 /* 8 transfers */
803: #define DMODE_BL_16 0xc0 /* 16 transfers */
804:
805: #define DMODE_700_BW16 0x20 /* Host buswidth = 16 */
806: #define DMODE_700_286 0x10 /* 286 mode */
807: #define DMODE_700_IOM 0x08 /* Transfer to IO port */
808: #define DMODE_700_FAM 0x04 /* Fixed address mode */
809: #define DMODE_700_PIPE 0x02 /* Pipeline mode disables
810: * automatic fetch / exec
811: */
812: #define DMODE_MAN 0x01 /* Manual start mode,
813: * requires a 1 to be written
814: * to the start DMA bit in the DCNTL
815: * register to run scripts
816: */
817:
818: #define DMODE_700_SAVE ( DMODE_00_BL_MASK | DMODE_00_BW16 | DMODE_00_286 )
819:
820: /* NCR53c800 series only */
821: #define SCRATCHA_REG_800 0x34 /* through 0x37 Scratch A rw */
822: /* NCR53c710 only */
823: #define SCRATCB_REG_10 0x34 /* through 0x37 scratch B rw */
824:
825: #define DMODE_REG_10 0x38 /* DMA mode rw, NCR53c710 and newer */
826: #define DMODE_800_SIOM 0x20 /* Source IO = 1 */
827: #define DMODE_800_DIOM 0x10 /* Destination IO = 1 */
828: #define DMODE_800_ERL 0x08 /* Enable Read Line */
829:
830: /* 35-38 are reserved on 700 and 700-66 series chips */
831: #define DIEN_REG 0x39 /* DMA interrupt enable rw */
832: /* 0x80, 0x40, and 0x20 are reserved on 700-series chips */
833: #define DIEN_800_MDPE 0x40 /* Master data parity error */
834: #define DIEN_800_BF 0x20 /* BUS fault */
835: #define DIEN_ABRT 0x10 /* Enable aborted interrupt */
836: #define DIEN_SSI 0x08 /* Enable single step interrupt */
837: #define DIEN_SIR 0x04 /* Enable SCRIPTS INT command
838: * interrupt
839: */
840: /* 0x02 is reserved on 800 series chips */
841: #define DIEN_700_WTD 0x02 /* Enable watchdog timeout interrupt */
842: #define DIEN_700_OPC 0x01 /* Enable illegal instruction
843: * interrupt
844: */
845: #define DIEN_800_IID 0x01 /* Same meaning, different name */
846:
847: /*
848: * DMA watchdog timer rw
849: * set in 16 CLK input periods.
850: */
851: #define DWT_REG 0x3a
852:
853: /* DMA control rw */
854: #define DCNTL_REG 0x3b
855: #define DCNTL_700_CF1 0x80 /* Clock divisor bits */
856: #define DCNTL_700_CF0 0x40
857: #define DCNTL_700_CF_MASK 0xc0
858: /* Clock divisors Divisor SCLK range (MHZ) */
859: #define DCNTL_700_CF_2 0x00 /* 2.0 37.51-50.00 */
860: #define DCNTL_700_CF_1_5 0x40 /* 1.5 25.01-37.50 */
861: #define DCNTL_700_CF_1 0x80 /* 1.0 16.67-25.00 */
862: #define DCNTL_700_CF_3 0xc0 /* 3.0 50.01-66.67 (53c700-66) */
863:
864: #define DCNTL_700_S16 0x20 /* Load scripts 16 bits at a time */
865: #define DCNTL_SSM 0x10 /* Single step mode */
866: #define DCNTL_700_LLM 0x08 /* Low level mode, can only be set
867: * after selection */
868: #define DCNTL_800_IRQM 0x08 /* Totem pole IRQ pin */
869: #define DCNTL_STD 0x04 /* Start DMA / SCRIPTS */
870: /* 0x02 is reserved */
871: #define DCNTL_00_RST 0x01 /* Software reset, resets everything
872: * but 286 mode bit in DMODE. On the
873: * NCR53c710, this bit moved to CTEST8
874: */
875: #define DCNTL_10_COM 0x01 /* 700 software compatibility mode */
876:
877: #define DCNTL_700_SAVE ( DCNTL_CF_MASK | DCNTL_S16)
878:
879:
880: /* NCR53c700-66 only */
881: #define SCRATCHB_REG_00 0x3c /* through 0x3f scratch b rw */
882: #define SCRATCHB_REG_800 0x5c /* through 0x5f scratch b rw */
883: /* NCR53c710 only */
884: #define ADDER_REG_10 0x3c /* Adder, NCR53c710 only */
885:
886: #define SIEN1_REG_800 0x41
887: #define SIEN1_800_STO 0x04 /* selection/reselection timeout */
888: #define SIEN1_800_GEN 0x02 /* general purpose timer */
889: #define SIEN1_800_HTH 0x01 /* handshake to handshake */
890:
891: #define SIST1_REG_800 0x43
892: #define SIST1_800_STO 0x04 /* selection/reselection timeout */
893: #define SIST1_800_GEN 0x02 /* general purpose timer */
894: #define SIST1_800_HTH 0x01 /* handshake to handshake */
895:
896: #define SLPAR_REG_800 0x44 /* Parity */
897:
898: #define MACNTL_REG_800 0x46 /* Memory access control */
899: #define MACNTL_800_TYP3 0x80
900: #define MACNTL_800_TYP2 0x40
901: #define MACNTL_800_TYP1 0x20
902: #define MACNTL_800_TYP0 0x10
903: #define MACNTL_800_DWR 0x08
904: #define MACNTL_800_DRD 0x04
905: #define MACNTL_800_PSCPT 0x02
906: #define MACNTL_800_SCPTS 0x01
907:
908: #define GPCNTL_REG_800 0x47 /* General Purpose Pin Control */
909:
910: /* Timeouts are expressed such that 0=off, 1=100us, doubling after that */
911: #define STIME0_REG_800 0x48 /* SCSI Timer Register 0 */
912: #define STIME0_800_HTH_MASK 0xf0 /* Handshake to Handshake timeout */
913: #define STIME0_800_HTH_SHIFT 4
914: #define STIME0_800_SEL_MASK 0x0f /* Selection timeout */
915: #define STIME0_800_SEL_SHIFT 0
916:
917: #define STIME1_REG_800 0x49
918: #define STIME1_800_GEN_MASK 0x0f /* General purpose timer */
919:
920: #define RESPID_REG_800 0x4a /* Response ID, bit fielded. 8
921: bits on narrow chips, 16 on WIDE */
922:
923: #define STEST0_REG_800 0x4c
924: #define STEST0_800_SLT 0x08 /* Selection response logic test */
925: #define STEST0_800_ART 0x04 /* Arbitration priority encoder test */
926: #define STEST0_800_SOZ 0x02 /* Synchronous offset zero */
927: #define STEST0_800_SOM 0x01 /* Synchronous offset maximum */
928:
929: #define STEST1_REG_800 0x4d
930: #define STEST1_800_SCLK 0x80 /* Disable SCSI clock */
931:
932: #define STEST2_REG_800 0x4e
933: #define STEST2_800_SCE 0x80 /* Enable SOCL/SODL */
934: #define STEST2_800_ROF 0x40 /* Reset SCSI sync offset */
935: #define STEST2_800_SLB 0x10 /* Enable SCSI loopback mode */
936: #define STEST2_800_SZM 0x08 /* SCSI high impedance mode */
937: #define STEST2_800_EXT 0x02 /* Extend REQ/ACK filter 30 to 60ns */
938: #define STEST2_800_LOW 0x01 /* SCSI low level mode */
939:
940: #define STEST3_REG_800 0x4f
941: #define STEST3_800_TE 0x80 /* Enable active negation */
942: #define STEST3_800_STR 0x40 /* SCSI FIFO test read */
943: #define STEST3_800_HSC 0x20 /* Halt SCSI clock */
944: #define STEST3_800_DSI 0x10 /* Disable single initiator response */
945: #define STEST3_800_TTM 0x04 /* Time test mode */
946: #define STEST3_800_CSF 0x02 /* Clear SCSI FIFO */
947: #define STEST3_800_STW 0x01 /* SCSI FIFO test write */
948:
949: #define OPTION_PARITY 0x1 /* Enable parity checking */
950: #define OPTION_TAGGED_QUEUE 0x2 /* Enable SCSI-II tagged queuing */
951: #define OPTION_700 0x8 /* Always run NCR53c700 scripts */
952: #define OPTION_INTFLY 0x10 /* Use INTFLY interrupts */
953: #define OPTION_DEBUG_INTR 0x20 /* Debug interrupts */
954: #define OPTION_DEBUG_INIT_ONLY 0x40 /* Run initialization code and
955: simple test code, return
956: DID_NO_CONNECT if any SCSI
957: commands are attempted. */
958: #define OPTION_DEBUG_READ_ONLY 0x80 /* Return DID_ERROR if any
959: SCSI write is attempted */
960: #define OPTION_DEBUG_TRACE 0x100 /* Animated trace mode, print
961: each address and instruction
962: executed to debug buffer. */
963: #define OPTION_DEBUG_SINGLE 0x200 /* stop after executing one
964: instruction */
965: #define OPTION_SYNCHRONOUS 0x400 /* Enable sync SCSI. */
966: #define OPTION_MEMORY_MAPPED 0x800 /* NCR registers have valid
967: memory mapping */
968: #define OPTION_IO_MAPPED 0x1000 /* NCR registers have valid
969: I/O mapping */
970: #define OPTION_DEBUG_PROBE_ONLY 0x2000 /* Probe only, don't even init */
971: #define OPTION_DEBUG_TESTS_ONLY 0x4000 /* Probe, init, run selected tests */
972: #define OPTION_DEBUG_TEST0 0x08000 /* Run test 0 */
973: #define OPTION_DEBUG_TEST1 0x10000 /* Run test 1 */
974: #define OPTION_DEBUG_TEST2 0x20000 /* Run test 2 */
975: #define OPTION_DEBUG_DUMP 0x40000 /* Dump commands */
976: #define OPTION_DEBUG_TARGET_LIMIT 0x80000 /* Only talk to target+luns specified */
977: #define OPTION_DEBUG_NCOMMANDS_LIMIT 0x100000 /* Limit the number of commands */
978: #define OPTION_DEBUG_SCRIPT 0x200000 /* Print when checkpoints are passed */
979: #define OPTION_DEBUG_FIXUP 0x400000 /* print fixup values */
980: #define OPTION_DEBUG_DSA 0x800000
981: #define OPTION_DEBUG_CORRUPTION 0x1000000 /* Detect script corruption */
982: #define OPTION_DEBUG_SDTR 0x2000000 /* Debug SDTR problem */
983: #define OPTION_DEBUG_MISMATCH 0x4000000 /* Debug phase mismatches */
984: #define OPTION_DISCONNECT 0x8000000 /* Allow disconnect */
985: #define OPTION_DEBUG_DISCONNECT 0x10000000
986: #define OPTION_ALWAYS_SYNCHRONOUS 0x20000000 /* Negotiate sync. transfers
987: on power up */
988: #define OPTION_DEBUG_QUEUES 0x80000000
989: #define OPTION_DEBUG_ALLOCATION 0x100000000LL
990: #define OPTION_DEBUG_SYNCHRONOUS 0x200000000LL /* Sanity check SXFER and
991: SCNTL3 registers */
992: #define OPTION_NO_ASYNC 0x400000000LL /* Don't automagically send
993: SDTR for async transfers when
994: we haven't been told to do
995: a synchronous transfer. */
996: #define OPTION_NO_PRINT_RACE 0x800000000LL /* Don't print message when
997: the reselect/WAIT DISCONNECT
998: race condition hits */
999: #if !defined(PERM_OPTIONS)
1000: #define PERM_OPTIONS 0
1001: #endif
1002:
1003: struct NCR53c7x0_synchronous {
1004: u32 select_indirect; /* Value used for indirect selection */
1005: u32 script[8]; /* Size ?? Script used when target is
1006: reselected */
1007: unsigned char synchronous_want[5]; /* Per target desired SDTR */
1008: /*
1009: * Set_synchronous programs these, select_indirect and current settings after
1010: * int_debug_should show a match.
1011: */
1012: unsigned char sxfer_sanity, scntl3_sanity;
1013: };
1014:
1015: #define CMD_FLAG_SDTR 1 /* Initiating synchronous
1016: transfer negotiation */
1017: #define CMD_FLAG_WDTR 2 /* Initiating wide transfer
1018: negotiation */
1019: #define CMD_FLAG_DID_SDTR 4 /* did SDTR */
1020: #define CMD_FLAG_DID_WDTR 8 /* did WDTR */
1021:
1022: struct NCR53c7x0_table_indirect {
1023: u32 count;
1024: void *address;
1025: };
1026:
1027: enum ncr_event {
1028: EVENT_NONE = 0,
1029: /*
1030: * Order is IMPORTANT, since these must correspond to the event interrupts
1031: * in 53c7,8xx.scr
1032: */
1033:
1034: EVENT_ISSUE_QUEUE = 0x5000000, /* Command was added to issue queue */
1035: EVENT_START_QUEUE, /* Command moved to start queue */
1036: EVENT_SELECT, /* Command completed selection */
1037: EVENT_DISCONNECT, /* Command disconnected */
1038: EVENT_RESELECT, /* Command reselected */
1039: EVENT_COMPLETE, /* Command completed */
1040: EVENT_IDLE,
1041: EVENT_SELECT_FAILED,
1042: EVENT_BEFORE_SELECT,
1043: EVENT_RESELECT_FAILED
1044: };
1045:
1046: struct NCR53c7x0_event {
1047: enum ncr_event event; /* What type of event */
1048: unsigned char target;
1049: unsigned char lun;
1050: struct timeval time;
1051: u32 *dsa; /* What's in the DSA register now (virt) */
1052: /*
1053: * A few things from that SCSI pid so we know what happened after
1054: * the Scsi_Cmnd structure in question may have disappeared.
1055: */
1056: unsigned long pid; /* The SCSI PID which caused this
1057: event */
1058: unsigned char cmnd[12];
1059: };
1060:
1061: /*
1062: * Things in the NCR53c7x0_cmd structure are split into two parts :
1063: *
1064: * 1. A fixed portion, for things which are not accessed directly by static NCR
1065: * code (ie, are referenced only by the Linux side of the driver,
1066: * or only by dynamically generated code).
1067: *
1068: * 2. The DSA portion, for things which are accessed directly by static NCR
1069: * code.
1070: *
1071: * This is a little ugly, but it
1072: * 1. Avoids conflicts between the NCR code's picture of the structure, and
1073: * Linux code's idea of what it looks like.
1074: *
1075: * 2. Minimizes the pain in the Linux side of the code needed
1076: * to calculate real dsa locations for things, etc.
1077: *
1078: */
1079:
1080: struct NCR53c7x0_cmd {
1081: void *real; /* Real, unaligned address for
1082: free function */
1083: void (* free)(void *, int); /* Command to deallocate; NULL
1084: for structures allocated with
1085: scsi_register, etc. */
1086: Scsi_Cmnd *cmd; /* Associated Scsi_Cmnd
1087: structure, Scsi_Cmnd points
1088: at NCR53c7x0_cmd using
1089: host_scribble structure */
1090:
1091: int size; /* scsi_malloc'd size of this
1092: structure */
1093:
1094: int flags; /* CMD_* flags */
1095:
1096: /*
1097: * SDTR and WIDE messages are an either/or affair
1098: * in this message, since we will go into message out and send
1099: * _the whole mess_ without dropping out of message out to
1100: * let the target go into message in after sending the first
1101: * message.
1102: */
1103:
1104: unsigned char select[11]; /* Select message, includes
1105: IDENTIFY
1106: (optional) QUEUE TAG
1107: (optional) SDTR or WDTR
1108: */
1109:
1110:
1111: volatile struct NCR53c7x0_cmd *next; /* Linux maintained lists (free,
1112: running, eventually finished */
1113:
1114:
1115: u32 *data_transfer_start; /* Start of data transfer routines */
1116: u32 *data_transfer_end; /* Address after end of data transfer o
1117: routines */
1118: /*
1119: * The following three fields were moved from the DSA proper to here
1120: * since only dynamically generated NCR code refers to them, meaning
1121: * we don't need dsa_* absolutes, and it is simpler to let the
1122: * host code refer to them directly.
1123: */
1124:
1125: /*
1126: * HARD CODED : residual and saved_residual need to agree with the sizes
1127: * used in NCR53c7,8xx.scr.
1128: *
1129: * FIXME: we want to consider the case where we have odd-length
1130: * scatter/gather buffers and a WIDE transfer, in which case
1131: * we'll need to use the CHAIN MOVE instruction. Ick.
1132: */
1133: u32 residual[6]; /* Residual data transfer which
1134: allows pointer code to work
1135: right.
1136:
1137: [0-1] : Conditional call to
1138: appropriate other transfer
1139: routine.
1140: [2-3] : Residual block transfer
1141: instruction.
1142: [4-5] : Jump to instruction
1143: after splice.
1144: */
1145: u32 saved_residual[6]; /* Copy of old residual, so we
1146: can get another partial
1147: transfer and still recover
1148: */
1149:
1150: u32 saved_data_pointer; /* Saved data pointer */
1151:
1152: u32 dsa_next_addr; /* _Address_ of dsa_next field
1153: in this dsa for RISCy
1154: style constant. */
1155:
1156: u32 dsa_addr; /* Address of dsa; RISCy style
1157: constant */
1158:
1159: u32 dsa[0]; /* Variable length (depending
1160: on host type, number of scatter /
1161: gather buffers, etc). */
1162: };
1163:
1164: struct NCR53c7x0_break {
1165: u32 *address, old_instruction[2];
1166: struct NCR53c7x0_break *next;
1167: unsigned char old_size; /* Size of old instruction */
1168: };
1169:
1170: /* Indicates that the NCR is not executing code */
1171: #define STATE_HALTED 0
1172: /*
1173: * Indicates that the NCR is executing the wait for select / reselect
1174: * script. Only used when running NCR53c700 compatible scripts, only
1175: * state during which an ABORT is _not_ considered an error condition.
1176: */
1177: #define STATE_WAITING 1
1178: /* Indicates that the NCR is executing other code. */
1179: #define STATE_RUNNING 2
1180: /*
1181: * Indicates that the NCR was being aborted.
1182: */
1183: #define STATE_ABORTING 3
1184: /* Indicates that the NCR was successfully aborted. */
1185: #define STATE_ABORTED 4
1186: /* Indicates that the NCR has been disabled due to a fatal error */
1187: #define STATE_DISABLED 5
1188:
1189: /*
1190: * Where knowledge of SCSI SCRIPT(tm) specified values are needed
1191: * in an interrupt handler, an interrupt handler exists for each
1192: * different SCSI script so we don't have name space problems.
1193: *
1194: * Return values of these handlers are as follows :
1195: */
1196: #define SPECIFIC_INT_NOTHING 0 /* don't even restart */
1197: #define SPECIFIC_INT_RESTART 1 /* restart at the next instruction */
1198: #define SPECIFIC_INT_ABORT 2 /* recoverable error, abort cmd */
1199: #define SPECIFIC_INT_PANIC 3 /* unrecoverable error, panic */
1200: #define SPECIFIC_INT_DONE 4 /* normal command completion */
1201: #define SPECIFIC_INT_BREAK 5 /* break point encountered */
1202:
1203: struct NCR53c7x0_hostdata {
1204: int size; /* Size of entire Scsi_Host
1205: structure */
1206: int board; /* set to board type, useful if
1207: we have host specific things,
1208: ie, a general purpose I/O
1209: bit is being used to enable
1210: termination, etc. */
1211:
1212: int chip; /* set to chip type; 700-66 is
1213: 700-66, rest are last three
1214: digits of part number */
1215: /*
1216: * PCI bus, device, function, only for NCR53c8x0 chips.
1217: * pci_valid indicates that the PCI configuration information
1218: * is valid, and we can twiddle MAX_LAT, etc. as recommended
1219: * for maximum performance in the NCR documentation.
1220: */
1221: unsigned char pci_bus, pci_device_fn;
1222: unsigned pci_valid:1;
1223:
1224: u32 *dsp; /* dsp to restart with after
1225: all stacked interrupts are
1226: handled. */
1227:
1228: unsigned dsp_changed:1; /* Has dsp changed within this
1229: set of stacked interrupts ? */
1230:
1231: unsigned char dstat; /* Most recent value of dstat */
1232: unsigned dstat_valid:1;
1233:
1234: unsigned expecting_iid:1; /* Expect IID interrupt */
1235: unsigned expecting_sto:1; /* Expect STO interrupt */
1236:
1237: /*
1238: * The code stays cleaner if we use variables with function
1239: * pointers and offsets that are unique for the different
1240: * scripts rather than having a slew of switch(hostdata->chip)
1241: * statements.
1242: *
1243: * It also means that the #defines from the SCSI SCRIPTS(tm)
1244: * don't have to be visible outside of the script-specific
1245: * instructions, preventing name space pollution.
1246: */
1247:
1248: void (* init_fixup)(struct Scsi_Host *host);
1249: void (* init_save_regs)(struct Scsi_Host *host);
1250: void (* dsa_fixup)(struct NCR53c7x0_cmd *cmd);
1251: void (* soft_reset)(struct Scsi_Host *host);
1252: int (* run_tests)(struct Scsi_Host *host);
1253:
1254: /*
1255: * Called when DSTAT_SIR is set, indicating an interrupt generated
1256: * by the INT instruction, where values are unique for each SCSI
1257: * script. Should return one of the SPEC_* values.
1258: */
1259:
1260: int (* dstat_sir_intr)(struct Scsi_Host *host, struct NCR53c7x0_cmd *cmd);
1261:
1262: int dsa_len; /* Size of DSA structure */
1263:
1264: /*
1265: * Location of DSA fields for the SCSI SCRIPT corresponding to this
1266: * chip.
1267: */
1268:
1269: s32 dsa_start;
1270: s32 dsa_end;
1271: s32 dsa_next;
1272: s32 dsa_prev;
1273: s32 dsa_cmnd;
1274: s32 dsa_select;
1275: s32 dsa_msgout;
1276: s32 dsa_cmdout;
1277: s32 dsa_dataout;
1278: s32 dsa_datain;
1279: s32 dsa_msgin;
1280: s32 dsa_msgout_other;
1281: s32 dsa_write_sync;
1282: s32 dsa_write_resume;
1283: s32 dsa_check_reselect;
1284: s32 dsa_status;
1285: s32 dsa_saved_pointer;
1286: s32 dsa_jump_dest;
1287:
1288: /*
1289: * Important entry points that generic fixup code needs
1290: * to know about, fixed up.
1291: */
1292:
1293: s32 E_accept_message;
1294: s32 E_command_complete;
1295: s32 E_data_transfer;
1296: s32 E_dsa_code_template;
1297: s32 E_dsa_code_template_end;
1298: s32 E_end_data_transfer;
1299: s32 E_msg_in;
1300: s32 E_initiator_abort;
1301: s32 E_other_transfer;
1302: s32 E_other_in;
1303: s32 E_other_out;
1304: s32 E_target_abort;
1305: s32 E_debug_break;
1306: s32 E_reject_message;
1307: s32 E_respond_message;
1308: s32 E_select;
1309: s32 E_select_msgout;
1310: s32 E_test_0;
1311: s32 E_test_1;
1312: s32 E_test_2;
1313: s32 E_test_3;
1314: s32 E_dsa_zero;
1315: s32 E_cmdout_cmdout;
1316: s32 E_wait_reselect;
1317: s32 E_dsa_code_begin;
1318:
1319: long long options; /* Bitfielded set of options enabled */
1320: volatile u32 test_completed; /* Test completed */
1321: int test_running; /* Test currently running */
1322: s32 test_source;
1323: volatile s32 test_dest;
1324:
1325: volatile int state; /* state of driver, only used for
1326: OPTION_700 */
1327:
1328: unsigned char dmode; /*
1329: * set to the address of the DMODE
1330: * register for this chip.
1331: */
1332: unsigned char istat; /*
1333: * set to the address of the ISTAT
1334: * register for this chip.
1335: */
1336:
1337: int scsi_clock; /*
1338: * SCSI clock in HZ. 0 may be used
1339: * for unknown, although this will
1340: * disable synchronous negotiation.
1341: */
1342:
1343: volatile int intrs; /* Number of interrupts */
1344: volatile int resets; /* Number of SCSI resets */
1345: unsigned char saved_dmode;
1346: unsigned char saved_ctest4;
1347: unsigned char saved_ctest7;
1348: unsigned char saved_dcntl;
1349: unsigned char saved_scntl3;
1350:
1351: unsigned char this_id_mask;
1352:
1353: /* Debugger information */
1354: struct NCR53c7x0_break *breakpoints, /* Linked list of all break points */
1355: *breakpoint_current; /* Current breakpoint being stepped
1356: through, NULL if we are running
1357: normally. */
1358: #ifdef NCR_DEBUG
1359: int debug_size; /* Size of debug buffer */
1360: volatile int debug_count; /* Current data count */
1361: volatile char *debug_buf; /* Output ring buffer */
1362: volatile char *debug_write; /* Current write pointer */
1363: volatile char *debug_read; /* Current read pointer */
1364: #endif /* def NCR_DEBUG */
1365:
1366: /* XXX - primitive debugging junk, remove when working ? */
1367: int debug_print_limit; /* Number of commands to print
1368: out exhaustive debugging
1369: information for if
1370: OPTION_DEBUG_DUMP is set */
1371:
1372: unsigned char debug_lun_limit[16]; /* If OPTION_DEBUG_TARGET_LIMIT
1373: set, puke if commands are sent
1374: to other target/lun combinations */
1375:
1376: int debug_count_limit; /* Number of commands to execute
1377: before puking to limit debugging
1378: output */
1379:
1380:
1381: volatile unsigned idle:1; /* set to 1 if idle */
1382:
1383: /*
1384: * Table of synchronous+wide transfer parameters set on a per-target
1385: * basis.
1386: */
1387:
1388: volatile struct NCR53c7x0_synchronous sync[16];
1389:
1390: volatile Scsi_Cmnd *issue_queue;
1391: /* waiting to be issued by
1392: Linux driver */
1393: volatile struct NCR53c7x0_cmd *running_list;
1394: /* commands running, maintained
1395: by Linux driver */
1396:
1397: volatile struct NCR53c7x0_cmd *current; /* currently connected
1398: nexus, ONLY valid for
1399: NCR53c700/NCR53c700-66
1400: */
1401:
1402: volatile struct NCR53c7x0_cmd *spare; /* pointer to spare,
1403: allocated at probe time,
1404: which we can use for
1405: initialization */
1406: volatile struct NCR53c7x0_cmd *free;
1407: int max_cmd_size; /* Maximum size of NCR53c7x0_cmd
1408: based on number of
1409: scatter/gather segments, etc.
1410: */
1411: volatile int num_cmds; /* Number of commands
1412: allocated */
1413: volatile int extra_allocate;
1414: volatile unsigned char cmd_allocated[16]; /* Have we allocated commands
1415: for this target yet? If not,
1416: do so ASAP */
1417: volatile unsigned char busy[16][8]; /* number of commands
1418: executing on each target
1419: */
1420: /*
1421: * Eventually, I'll switch to a coroutine for calling
1422: * cmd->done(cmd), etc. so that we can overlap interrupt
1423: * processing with this code for maximum performance.
1424: */
1425:
1426: volatile struct NCR53c7x0_cmd *finished_queue;
1427:
1428:
1429: /* Shared variables between SCRIPT and host driver */
1430: volatile u32 *schedule; /* Array of JUMPs to dsa_begin
1431: routines of various DSAs.
1432: When not in use, replace
1433: with jump to next slot */
1434:
1435:
1436: volatile unsigned char msg_buf[16]; /* buffer for messages
1437: other than the command
1438: complete message */
1439:
1440: /* Per-target default synchronous and WIDE messages */
1441: volatile unsigned char synchronous_want[16][5];
1442: volatile unsigned char wide_want[16][4];
1443:
1444: /* Bit fielded set of targets we want to speak synchronously with */
1445: volatile u16 initiate_sdtr;
1446: /* Bit fielded set of targets we want to speak wide with */
1447: volatile u16 initiate_wdtr;
1448: /* Bit fielded list of targets we've talked to. */
1449: volatile u16 talked_to;
1450:
1451: /* Array of bit-fielded lun lists that we need to request_sense */
1452: volatile unsigned char request_sense[16];
1453:
1454: u32 addr_reconnect_dsa_head; /* RISCy style constant,
1455: address of following */
1456: volatile u32 reconnect_dsa_head;
1457: /* Data identifying nexus we are trying to match during reselection */
1458: volatile unsigned char reselected_identify; /* IDENTIFY message */
1459: volatile unsigned char reselected_tag; /* second byte of queue tag
1460: message or 0 */
1461: /* These were static variables before we moved them */
1462:
1463: s32 NCR53c7xx_zero;
1464: s32 NCR53c7xx_sink;
1465: u32 NOP_insn;
1466: char NCR53c7xx_msg_reject;
1467: char NCR53c7xx_msg_abort;
1468: char NCR53c7xx_msg_nop;
1469:
1470: volatile int event_size, event_index;
1471: volatile struct NCR53c7x0_event *events;
1472:
1473: /* If we need to generate code to kill off the currently connected
1474: command, this is where we do it. Should have a BMI instruction
1475: to source or sink the current data, followed by a JUMP
1476: to abort_connected */
1477:
1478: u32 *abort_script;
1479:
1480: int script_count; /* Size of script in words */
1481: u32 script[0]; /* Relocated SCSI script */
1482:
1483: };
1484:
1485: #define IRQ_NONE 255
1486: #define DMA_NONE 255
1487: #define IRQ_AUTO 254
1488: #define DMA_AUTO 254
1489:
1490: #define BOARD_GENERIC 0
1491:
1492: #define NCR53c7x0_insn_size(insn) \
1493: (((insn) & DCMD_TYPE_MASK) == DCMD_TYPE_MMI ? 3 : 2)
1494:
1495:
1496: #define NCR53c7x0_local_declare() \
1497: volatile unsigned char *NCR53c7x0_address_memory; \
1498: unsigned int NCR53c7x0_address_io; \
1499: int NCR53c7x0_memory_mapped
1500:
1501: #define NCR53c7x0_local_setup(host) \
1502: NCR53c7x0_address_memory = (void *) (host)->base; \
1503: NCR53c7x0_address_io = (unsigned int) (host)->io_port; \
1504: NCR53c7x0_memory_mapped = ((struct NCR53c7x0_hostdata *) \
1505: host->hostdata)-> options & OPTION_MEMORY_MAPPED
1506:
1507: #define NCR53c7x0_read8(address) \
1508: (NCR53c7x0_memory_mapped ? \
1509: (unsigned int)readb(NCR53c7x0_address_memory + (address)) : \
1510: inb(NCR53c7x0_address_io + (address)))
1511:
1512: #define NCR53c7x0_read16(address) \
1513: (NCR53c7x0_memory_mapped ? \
1514: (unsigned int)readw(NCR53c7x0_address_memory + (address)) : \
1515: inw(NCR53c7x0_address_io + (address)))
1516:
1517: #define NCR53c7x0_read32(address) \
1518: (NCR53c7x0_memory_mapped ? \
1519: (unsigned int) readl(NCR53c7x0_address_memory + (address)) : \
1520: inl(NCR53c7x0_address_io + (address)))
1521:
1522: #define NCR53c7x0_write8(address,value) \
1523: (NCR53c7x0_memory_mapped ? \
1524: ({writeb((value), NCR53c7x0_address_memory + (address)); mb();}) : \
1525: outb((value), NCR53c7x0_address_io + (address)))
1526:
1527: #define NCR53c7x0_write16(address,value) \
1528: (NCR53c7x0_memory_mapped ? \
1529: ({writew((value), NCR53c7x0_address_memory + (address)); mb();}) : \
1530: outw((value), NCR53c7x0_address_io + (address)))
1531:
1532: #define NCR53c7x0_write32(address,value) \
1533: (NCR53c7x0_memory_mapped ? \
1534: ({writel((value), NCR53c7x0_address_memory + (address)); mb();}) : \
1535: outl((value), NCR53c7x0_address_io + (address)))
1536:
1537: /* Patch arbitrary 32 bit words in the script */
1538: #define patch_abs_32(script, offset, symbol, value) \
1539: for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \
1540: (u32)); ++i) { \
1541: (script)[A_##symbol##_used[i] - (offset)] += (value); \
1542: if (hostdata->options & OPTION_DEBUG_FIXUP) \
1543: printk("scsi%d : %s reference %d at 0x%x in %s is now 0x%x\n",\
1544: host->host_no, #symbol, i, A_##symbol##_used[i] - \
1545: (int)(offset), #script, (script)[A_##symbol##_used[i] - \
1546: (offset)]); \
1547: }
1548:
1549: /* Patch read/write instruction immediate field */
1550: #define patch_abs_rwri_data(script, offset, symbol, value) \
1551: for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \
1552: (u32)); ++i) \
1553: (script)[A_##symbol##_used[i] - (offset)] = \
1554: ((script)[A_##symbol##_used[i] - (offset)] & \
1555: ~DBC_RWRI_IMMEDIATE_MASK) | \
1556: (((value) << DBC_RWRI_IMMEDIATE_SHIFT) & \
1557: DBC_RWRI_IMMEDIATE_MASK)
1558:
1559: /* Patch transfer control instruction data field */
1560: #define patch_abs_tci_data(script, offset, symbol, value) \
1561: for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \
1562: (u32)); ++i) \
1563: (script)[A_##symbol##_used[i] - (offset)] = \
1564: ((script)[A_##symbol##_used[i] - (offset)] & \
1565: ~DBC_TCI_DATA_MASK) | \
1566: (((value) << DBC_TCI_DATA_SHIFT) & \
1567: DBC_TCI_DATA_MASK)
1568:
1569: /* Patch field in dsa structure (assignment should be +=?) */
1570: #define patch_dsa_32(dsa, symbol, word, value) \
1571: { \
1.1.1.2 ! root 1572: (dsa)[(hostdata->symbol - hostdata->dsa_start) / sizeof(u32) \
1.1 root 1573: + (word)] = (value); \
1574: if (hostdata->options & OPTION_DEBUG_DSA) \
1575: printk("scsi : dsa %s symbol %s(%d) word %d now 0x%x\n", \
1.1.1.2 ! root 1576: #dsa, #symbol, hostdata->symbol, \
1.1 root 1577: (word), (u32) (value)); \
1578: }
1579:
1580: /* Paranoid people could use panic() here. */
1581: #define FATAL(host) shutdown((host));
1582:
1583: #endif /* NCR53c7x0_C */
1584: #endif /* NCR53c7x0_H */
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