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1.1 root 1: /* AM53/79C974 (PCscsi) driver release 0.5
2: *
3: * The architecture and much of the code of this device
4: * driver was originally developed by Drew Eckhardt for
5: * the NCR5380. The following copyrights apply:
6: * For the architecture and all parts similar to the NCR5380:
7: * Copyright 1993, Drew Eckhardt
8: * Visionary Computing
9: * (Unix and Linux consulting and custom programming)
10: * [email protected]
11: * +1 (303) 666-5836
12: *
13: * The AM53C974_nobios_detect code was originally developed by
14: * Robin Cutshaw ([email protected]) and is used here in a
15: * modified form.
16: *
17: * For the other parts:
18: * Copyright 1994, D. Frieauff
19: * EMail: [email protected]
20: * Phone: x49-7545-8-2256 , x49-7541-42305
21: */
22:
23: /*
24: * $Log: AM53C974.h,v $
25: * Revision 1.1 1999/04/26 05:53:51 tb
26: * 1998-11-30 OKUJI Yoshinori <[email protected]>
27: *
28: * Clean up linux emulation code to make it architecture-independent
29: * as much as possible.
30: *
31: * * linux: Renamed from linuxdev.
32: * * Makefile.in (objfiles): Add linux.o instead of linuxdev.o.
33: * (MAKE): New variable. Used for the linux.o target.
34: * * configure.in: Add AC_CHECK_TOOL(MAKE, make).
35: * * i386/i386/spl.h: Include <i386/ipl.h>, for compatibility with
36: * OSF Mach 3.0. Suggested by Elgin Lee <[email protected]>.
37: * * linux/src: Renamed from linux/linux.
38: * * linux/dev: Renamed from linux/mach.
39: * * linux/Drivers.in (AC_INIT): Use dev/include/linux/autoconf.h,
40: * instead of mach/include/linux/autoconf.h.
41: * * Makefile.in (all): Target ../linux.o instead of ../linuxdev.o.
42: * * linux/dev/drivers/block/genhd.c: Include <machine/spl.h> instead
43: * of <i386/ipl.h>.
44: * * linux/dev/drivers/net/auto_irq.c: Remove unneeded header files,
45: * <i386/ipl.h> and <i386/pic.h>.
46: * * linux/dev/init/main.c: Many i386-dependent codes moved to ...
47: * * linux/dev/arch/i386/irq.c: ... here.
48: * * linux/dev/arch/i386/setup.c: New file.
49: * * linux/dev/arch/i386/linux_emul.h: Likewise.
50: * * linux/dev/arch/i386/glue/timer.c: Merged into sched.c.
51: * * linux/dev/arch/i386/glue/sched.c: Include <machine/spl.h> instead
52: * of <i386/ipl.h>, and moved to ...
53: * * linux/dev/kernel/sched.c: ... here.
54: * * linux/dev/arch/i386/glue/block.c: Include <machine/spl.h> and
55: * <linux_emul.h>, instead of i386-dependent header files, and
56: * moved to ...
57: * * linux/dev/glue/blocl.c: ... here.
58: * * linux/dev/arch/i386/glue/net.c: Include <machine/spl.h> and
59: * <linux_emul.h>, instead of i386-dependent header files, and
60: * moved to ...
61: * * linux/dev/glue/net.c: ... here.
62: * * linux/dev/arch/i386/glue/misc.c: Remove `x86' and moved to ...
63: * * linux/dev/glue/misc.c: ... here.
64: * * linux/dev/arch/i386/glue/kmem.c: Moved to ...
65: * * linux/dev/glue/kmem.c: ... here.
66: *
67: */
68:
69: #ifndef AM53C974_H
70: #define AM53C974_H
71:
72: #include <scsi/scsicam.h>
73:
74: /***************************************************************************************
75: * Default setting of the controller's SCSI id. Edit and uncomment this only if your *
76: * BIOS does not correctly initialize the controller's SCSI id. *
77: * If you don't get a warning during boot, it is correctly initialized. *
78: ****************************************************************************************/
79: /* #define AM53C974_SCSI_ID 7 */
80:
81: /***************************************************************************************
82: * Default settings for sync. negotiation enable, transfer rate and sync. offset. *
83: * These settings can be replaced by LILO overrides (append) with the following syntax: *
84: * AM53C974=host-scsi-id, target-scsi-id, max-rate, max-offset *
85: * Sync. negotiation is disabled by default and will be enabled for those targets which *
86: * are specified in the LILO override *
87: ****************************************************************************************/
88: #define DEFAULT_SYNC_NEGOTIATION_ENABLED 0 /* 0 or 1 */
89: #define DEFAULT_RATE 5 /* MHz, min: 3; max: 10 */
90: #define DEFAULT_SYNC_OFFSET 0 /* bytes, min: 0; max: 15; use 0 for async. mode */
91:
92:
93: /* --------------------- don't edit below here --------------------- */
94:
95: #define AM53C974_DRIVER_REVISION_MAJOR 0
96: #define AM53C974_DRIVER_REVISION_MINOR 5
97: #define SEPARATOR_LINE \
98: "--------------------------------------------------------------------------\n"
99:
100: /* debug control */
101: /* #define AM53C974_DEBUG */
102: /* #define AM53C974_DEBUG_MSG */
103: /* #define AM53C974_DEBUG_KEYWAIT */
104: /* #define AM53C974_DEBUG_INIT */
105: /* #define AM53C974_DEBUG_QUEUE */
106: /* #define AM53C974_DEBUG_INFO */
107: /* #define AM53C974_DEBUG_LINKED */
108: /* #define VERBOSE_AM53C974_DEBUG */
109: /* #define AM53C974_DEBUG_INTR */
110: /* #define AM53C974_DEB_RESEL */
111: #define AM53C974_DEBUG_ABORT
112: /* #define AM53C974_OPTION_DEBUG_PROBE_ONLY */
113:
114: /* special options/constants */
115: #define DEF_CLK 40 /* chip clock freq. in MHz */
116: #define MIN_PERIOD 4 /* for negotiation: min. number of clocks per cycle */
117: #define MAX_PERIOD 13 /* for negotiation: max. number of clocks per cycle */
118: #define MAX_OFFSET 15 /* for negotiation: max. offset (0=async) */
119:
120: #define DEF_SCSI_TIMEOUT 245 /* STIMREG value, 40 Mhz */
121: #define DEF_STP 8 /* STPREG value assuming 5.0 MB/sec, FASTCLK, FASTSCSI */
122: #define DEF_SOF_RAD 0 /* REQ/ACK deassertion delay */
123: #define DEF_SOF_RAA 0 /* REQ/ACK assertion delay */
124: #define DEF_ETM 0 /* CNTLREG1, ext. timing mode */
125: #define DEF_PERE 1 /* CNTLREG1, parity error reporting */
126: #define DEF_CLKF 0 /* CLKFREG, 0=40 Mhz */
127: #define DEF_ENF 1 /* CNTLREG2, enable features */
128: #define DEF_ADIDCHK 0 /* CNTLREG3, additional ID check */
129: #define DEF_FASTSCSI 1 /* CNTLREG3, fast SCSI */
130: #define DEF_FASTCLK 1 /* CNTLREG3, fast clocking, 5 MB/sec at 40MHz chip clk */
131: #define DEF_GLITCH 1 /* CNTLREG4, glitch eater, 0=12ns, 1=35ns, 2=25ns, 3=off */
132: #define DEF_PWD 0 /* CNTLREG4, reduced power feature */
133: #define DEF_RAE 0 /* CNTLREG4, RAE active negation on REQ, ACK only */
134: #define DEF_RADE 1 /* 1CNTLREG4, active negation on REQ, ACK and data */
135:
136: /*** PCI block ***/
137: /* standard registers are defined in <linux/pci.h> */
138: #ifndef PCI_VENDOR_ID_AMD
139: #define PCI_VENDOR_ID_AMD 0x1022
140: #define PCI_DEVICE_ID_AMD_SCSI 0x2020
141: #endif
142: #define PCI_BASE_MASK 0xFFFFFFE0
143: #define PCI_COMMAND_PERREN 0x40
144: #define PCI_SCRATCH_REG_0 0x40 /* 16 bits */
145: #define PCI_SCRATCH_REG_1 0x42 /* 16 bits */
146: #define PCI_SCRATCH_REG_2 0x44 /* 16 bits */
147: #define PCI_SCRATCH_REG_3 0x46 /* 16 bits */
148: #define PCI_SCRATCH_REG_4 0x48 /* 16 bits */
149: #define PCI_SCRATCH_REG_5 0x4A /* 16 bits */
150: #define PCI_SCRATCH_REG_6 0x4C /* 16 bits */
151: #define PCI_SCRATCH_REG_7 0x4E /* 16 bits */
152:
153: /*** SCSI block ***/
154: #define CTCLREG 0x00 /* r current transf. count, low byte */
155: #define CTCMREG 0x04 /* r current transf. count, middle byte */
156: #define CTCHREG 0x38 /* r current transf. count, high byte */
157: #define STCLREG 0x00 /* w start transf. count, low byte */
158: #define STCMREG 0x04 /* w start transf. count, middle byte */
159: #define STCHREG 0x38 /* w start transf. count, high byte */
160: #define FFREG 0x08 /* rw SCSI FIFO reg. */
161: #define STIMREG 0x14 /* w SCSI timeout reg. */
162:
163: #define SDIDREG 0x10 /* w SCSI destination ID reg. */
164: #define SDIREG_MASK 0x07 /* mask */
165:
166: #define STPREG 0x18 /* w synchronous transf. period reg. */
167: #define STPREG_STP 0x1F /* synchr. transfer period */
168:
169: #define CLKFREG 0x24 /* w clock factor reg. */
170: #define CLKFREG_MASK 0x07 /* mask */
171:
172: #define CMDREG 0x0C /* rw SCSI command reg. */
173: #define CMDREG_DMA 0x80 /* set DMA mode (set together with opcodes below) */
174: #define CMDREG_IT 0x10 /* information transfer */
175: #define CMDREG_ICCS 0x11 /* initiator command complete steps */
176: #define CMDREG_MA 0x12 /* message accepted */
177: #define CMDREG_TPB 0x98 /* transfer pad bytes, DMA mode only */
178: #define CMDREG_SATN 0x1A /* set ATN */
179: #define CMDREG_RATN 0x1B /* reset ATN */
180: #define CMDREG_SOAS 0x41 /* select without ATN steps */
181: #define CMDREG_SAS 0x42 /* select with ATN steps (1 msg byte) */
182: #define CMDREG_SASS 0x43 /* select with ATN and stop steps */
183: #define CMDREG_ESR 0x44 /* enable selection/reselection */
184: #define CMDREG_DSR 0x45 /* disable selection/reselection */
185: #define CMDREG_SA3S 0x46 /* select with ATN 3 steps (3 msg bytes) */
186: #define CMDREG_NOP 0x00 /* no operation */
187: #define CMDREG_CFIFO 0x01 /* clear FIFO */
188: #define CMDREG_RDEV 0x02 /* reset device */
189: #define CMDREG_RBUS 0x03 /* reset SCSI bus */
190:
191: #define STATREG 0x10 /* r SCSI status reg. */
192: #define STATREG_INT 0x80 /* SCSI interrupt condition detected */
193: #define STATREG_IOE 0x40 /* SCSI illegal operation error detected */
194: #define STATREG_PE 0x20 /* SCSI parity error detected */
195: #define STATREG_CTZ 0x10 /* CTC reg decremented to zero */
196: #define STATREG_MSG 0x04 /* SCSI MSG phase (latched?) */
197: #define STATREG_CD 0x02 /* SCSI C/D phase (latched?) */
198: #define STATREG_IO 0x01 /* SCSI I/O phase (latched?) */
199: #define STATREG_PHASE 0x07 /* SCSI phase mask */
200:
201: #define INSTREG 0x14 /* r interrupt status reg. */
202: #define INSTREG_SRST 0x80 /* SCSI reset detected */
203: #define INSTREG_ICMD 0x40 /* SCSI invalid command detected */
204: #define INSTREG_DIS 0x20 /* target disconnected or sel/resel timeout*/
205: #define INSTREG_SR 0x10 /* device on bus has service request */
206: #define INSTREG_SO 0x08 /* successful operation */
207: #define INSTREG_RESEL 0x04 /* device reselected as initiator */
208:
209: #define ISREG 0x18 /* r internal state reg. */
210: #define ISREG_SOF 0x08 /* synchronous offset flag (act. low) */
211: #define ISREG_IS 0x07 /* status of intermediate op. */
212: #define ISREG_OK_NO_STOP 0x04 /* selection successful */
213: #define ISREG_OK_STOP 0x01 /* selection successful */
214:
215: #define CFIREG 0x1C /* r current FIFO/internal state reg. */
216: #define CFIREG_IS 0xE0 /* status of intermediate op. */
217: #define CFIREG_CF 0x1F /* number of bytes in SCSI FIFO */
218:
219: #define SOFREG 0x1C /* w synchr. offset reg. */
220: #define SOFREG_RAD 0xC0 /* REQ/ACK deassertion delay (sync.) */
221: #define SOFREG_RAA 0x30 /* REQ/ACK assertion delay (sync.) */
222: #define SOFREG_SO 0x0F /* synch. offset (sync.) */
223:
224: #define CNTLREG1 0x20 /* rw control register one */
225: #define CNTLREG1_ETM 0x80 /* set extended timing mode */
226: #define CNTLREG1_DISR 0x40 /* disable interrupt on SCSI reset */
227: #define CNTLREG1_PERE 0x10 /* enable parity error reporting */
228: #define CNTLREG1_SID 0x07 /* host adapter SCSI ID */
229:
230: #define CNTLREG2 0x2C /* rw control register two */
231: #define CNTLREG2_ENF 0x40 /* enable features */
232:
233: #define CNTLREG3 0x30 /* rw control register three */
234: #define CNTLREG3_ADIDCHK 0x80 /* additional ID check */
235: #define CNTLREG3_FASTSCSI 0x10 /* fast SCSI */
236: #define CNTLREG3_FASTCLK 0x08 /* fast SCSI clocking */
237:
238: #define CNTLREG4 0x34 /* rw control register four */
239: #define CNTLREG4_GLITCH 0xC0 /* glitch eater */
240: #define CNTLREG4_PWD 0x20 /* reduced power feature */
241: #define CNTLREG4_RAE 0x08 /* write only, active negot. ctrl. */
242: #define CNTLREG4_RADE 0x04 /* active negot. ctrl. */
243: #define CNTLREG4_RES 0x10 /* reserved bit, must be 1 */
244:
245: /*** DMA block ***/
246: #define DMACMD 0x40 /* rw command */
247: #define DMACMD_DIR 0x80 /* transfer direction (1=read from device) */
248: #define DMACMD_INTE_D 0x40 /* DMA transfer interrupt enable */
249: #define DMACMD_INTE_P 0x20 /* page transfer interrupt enable */
250: #define DMACMD_MDL 0x10 /* map to memory descriptor list */
251: #define DMACMD_DIAG 0x04 /* diagnostics, set to 0 */
252: #define DMACMD_IDLE 0x00 /* idle cmd */
253: #define DMACMD_BLAST 0x01 /* flush FIFO to memory */
254: #define DMACMD_ABORT 0x02 /* terminate DMA */
255: #define DMACMD_START 0x03 /* start DMA */
256:
257: #define DMASTATUS 0x54 /* r status register */
258: #define DMASTATUS_BCMPLT 0x20 /* BLAST complete */
259: #define DMASTATUS_SCSIINT 0x10 /* SCSI interrupt pending */
260: #define DMASTATUS_DONE 0x08 /* DMA transfer terminated */
261: #define DMASTATUS_ABORT 0x04 /* DMA transfer aborted */
262: #define DMASTATUS_ERROR 0x02 /* DMA transfer error */
263: #define DMASTATUS_PWDN 0x02 /* power down indicator */
264:
265: #define DMASTC 0x44 /* rw starting transfer count */
266: #define DMASPA 0x48 /* rw starting physical address */
267: #define DMAWBC 0x4C /* r working byte counter */
268: #define DMAWAC 0x50 /* r working address counter */
269: #define DMASMDLA 0x58 /* rw starting MDL address */
270: #define DMAWMAC 0x5C /* r working MDL counter */
271:
272: /*** SCSI phases ***/
273: #define PHASE_MSGIN 0x07
274: #define PHASE_MSGOUT 0x06
275: #define PHASE_RES_1 0x05
276: #define PHASE_RES_0 0x04
277: #define PHASE_STATIN 0x03
278: #define PHASE_CMDOUT 0x02
279: #define PHASE_DATAIN 0x01
280: #define PHASE_DATAOUT 0x00
281:
282: struct AM53C974_hostdata {
283: volatile unsigned in_reset:1; /* flag, says bus reset pending */
284: volatile unsigned aborted:1; /* flag, says aborted */
285: volatile unsigned selecting:1; /* selection started, but not yet finished */
286: volatile unsigned disconnecting: 1; /* disconnection started, but not yet finished */
287: volatile unsigned dma_busy:1; /* dma busy when service request for info transfer received */
288: volatile unsigned char msgout[10]; /* message to output in MSGOUT_PHASE */
289: volatile unsigned char last_message[10]; /* last message OUT */
290: volatile Scsi_Cmnd *issue_queue; /* waiting to be issued */
291: volatile Scsi_Cmnd *disconnected_queue; /* waiting for reconnect */
292: volatile Scsi_Cmnd *sel_cmd; /* command for selection */
293: volatile Scsi_Cmnd *connected; /* currently connected command */
294: volatile unsigned char busy[8]; /* index = target, bit = lun */
295: unsigned char sync_per[8]; /* synchronous transfer period (in effect) */
296: unsigned char sync_off[8]; /* synchronous offset (in effect) */
297: unsigned char sync_neg[8]; /* sync. negotiation performed (in effect) */
298: unsigned char sync_en[8]; /* sync. negotiation performed (in effect) */
299: unsigned char max_rate[8]; /* max. transfer rate (setup) */
300: unsigned char max_offset[8]; /* max. sync. offset (setup), only valid if corresponding sync_en is nonzero */
301: };
302:
303: #define AM53C974 { \
304: NULL, /* pointer to next in list */ \
305: NULL, /* long * usage_count */ \
306: NULL, /* struct proc_dir_entry *proc_dir */ \
307: NULL, /* int (*proc_info)(char *, char **, off_t, int, int, int); */ \
308: "AM53C974", /* name */ \
309: AM53C974_detect, /* int (* detect)(struct SHT *) */ \
310: NULL, /* int (*release)(struct Scsi_Host *) */ \
311: AM53C974_info, /* const char *(* info)(struct Scsi_Host *) */ \
312: AM53C974_command, /* int (* command)(Scsi_Cmnd *) */ \
313: AM53C974_queue_command, /* int (* queuecommand)(Scsi_Cmnd *, \
314: void (*done)(Scsi_Cmnd *)) */ \
315: AM53C974_abort, /* int (* abort)(Scsi_Cmnd *) */ \
316: AM53C974_reset, /* int (* reset)(Scsi_Cmnd *) */ \
317: NULL, /* int (* slave_attach)(int, int) */ \
318: scsicam_bios_param, /* int (* bios_param)(Disk *, int, int[]) */ \
319: 12, /* can_queue */ \
320: -1, /* this_id */ \
321: SG_ALL, /* sg_tablesize */ \
322: 1, /* cmd_per_lun */ \
323: 0, /* present, i.e. how many adapters of this kind */ \
324: 0, /* unchecked_isa_dma */ \
325: DISABLE_CLUSTERING /* use_clustering */ \
326: }
327:
328: void AM53C974_setup(char *str, int *ints);
329: int AM53C974_detect(Scsi_Host_Template *tpnt);
330: int AM53C974_biosparm(Disk *disk, int dev, int *info_array);
331: const char *AM53C974_info(struct Scsi_Host *);
332: int AM53C974_command(Scsi_Cmnd *SCpnt);
333: int AM53C974_queue_command(Scsi_Cmnd *cmd, void (*done)(Scsi_Cmnd *));
334: int AM53C974_abort(Scsi_Cmnd *cmd);
335: int AM53C974_reset (Scsi_Cmnd *cmd, unsigned int flags);
336:
337: #define AM53C974_local_declare() unsigned long io_port
338: #define AM53C974_setio(instance) io_port = instance->io_port
339: #define AM53C974_read_8(addr) inb(io_port + (addr))
340: #define AM53C974_write_8(addr,x) outb((x), io_port + (addr))
341: #define AM53C974_read_16(addr) inw(io_port + (addr))
342: #define AM53C974_write_16(addr,x) outw((x), io_port + (addr))
343: #define AM53C974_read_32(addr) inl(io_port + (addr))
344: #define AM53C974_write_32(addr,x) outl((x), io_port + (addr))
345:
346: #define AM53C974_poll_int() { do { statreg = AM53C974_read_8(STATREG); } \
347: while (!(statreg & STATREG_INT)) ; \
348: AM53C974_read_8(INSTREG) ; } /* clear int */
349: #define AM53C974_cfifo() (AM53C974_read_8(CFIREG) & CFIREG_CF)
350:
351: /* These are "special" values for the tag parameter passed to AM53C974_select. */
352: #define TAG_NEXT -1 /* Use next free tag */
353: #define TAG_NONE -2 /* Establish I_T_L nexus instead of I_T_L_Q
354: * even on SCSI-II devices */
355:
356: /************ LILO overrides *************/
357: typedef struct _override_t {
358: int host_scsi_id; /* SCSI id of the bus controller */
359: int target_scsi_id; /* SCSI id of target */
360: int max_rate; /* max. transfer rate */
361: int max_offset; /* max. sync. offset, 0 = asynchronous */
362: } override_t;
363:
364: /************ PCI stuff *************/
365: #define AM53C974_PCIREG_OPEN() outb(0xF1, 0xCF8); outb(0, 0xCFA)
366: #define AM53C974_PCIREG_CLOSE() outb(0, 0xCF8)
367: #define AM53C974_PCIREG_READ_BYTE(instance,a) ( inb((a) + (instance)->io_port) )
368: #define AM53C974_PCIREG_READ_WORD(instance,a) ( inw((a) + (instance)->io_port) )
369: #define AM53C974_PCIREG_READ_DWORD(instance,a) ( inl((a) + (instance)->io_port) )
370: #define AM53C974_PCIREG_WRITE_BYTE(instance,x,a) ( outb((x), (a) + (instance)->io_port) )
371: #define AM53C974_PCIREG_WRITE_WORD(instance,x,a) ( outw((x), (a) + (instance)->io_port) )
372: #define AM53C974_PCIREG_WRITE_DWORD(instance,x,a) ( outl((x), (a) + (instance)->io_port) )
373:
374: typedef struct _pci_config_t {
375: /* start of official PCI config space header */
376: union {
377: unsigned int device_vendor;
378: struct {
379: unsigned short vendor;
380: unsigned short device;
381: } dv;
382: } dv_id;
383: #define _device_vendor dv_id.device_vendor
384: #define _vendor dv_id.dv.vendor
385: #define _device dv_id.dv.device
386: union {
387: unsigned int status_command;
388: struct {
389: unsigned short command;
390: unsigned short status;
391: } sc;
392: } stat_cmd;
393: #define _status_command stat_cmd.status_command
394: #define _command stat_cmd.sc.command
395: #define _status stat_cmd.sc.status
396: union {
397: unsigned int class_revision;
398: struct {
399: unsigned char rev_id;
400: unsigned char prog_if;
401: unsigned char sub_class;
402: unsigned char base_class;
403: } cr;
404: } class_rev;
405: #define _class_revision class_rev.class_revision
406: #define _rev_id class_rev.cr.rev_id
407: #define _prog_if class_rev.cr.prog_if
408: #define _sub_class class_rev.cr.sub_class
409: #define _base_class class_rev.cr.base_class
410: union {
411: unsigned int bist_header_latency_cache;
412: struct {
413: unsigned char cache_line_size;
414: unsigned char latency_timer;
415: unsigned char header_type;
416: unsigned char bist;
417: } bhlc;
418: } bhlc;
419: #define _bist_header_latency_cache bhlc.bist_header_latency_cache
420: #define _cache_line_size bhlc.bhlc.cache_line_size
421: #define _latency_timer bhlc.bhlc.latency_timer
422: #define _header_type bhlc.bhlc.header_type
423: #define _bist bhlc.bhlc.bist
424: unsigned int _base0;
425: unsigned int _base1;
426: unsigned int _base2;
427: unsigned int _base3;
428: unsigned int _base4;
429: unsigned int _base5;
430: unsigned int rsvd1;
431: unsigned int rsvd2;
432: unsigned int _baserom;
433: unsigned int rsvd3;
434: unsigned int rsvd4;
435: union {
436: unsigned int max_min_ipin_iline;
437: struct {
438: unsigned char int_line;
439: unsigned char int_pin;
440: unsigned char min_gnt;
441: unsigned char max_lat;
442: } mmii;
443: } mmii;
444: #define _max_min_ipin_iline mmii.max_min_ipin_iline
445: #define _int_line mmii.mmii.int_line
446: #define _int_pin mmii.mmii.int_pin
447: #define _min_gnt mmii.mmii.min_gnt
448: #define _max_lat mmii.mmii.max_lat
449: /* end of official PCI config space header */
450: unsigned short _ioaddr; /* config type 1 - private I/O addr */
451: unsigned int _pcibus; /* config type 2 - private bus id */
452: unsigned int _cardnum; /* config type 2 - private card number */
453: } pci_config_t;
454:
455: #endif /* AM53C974_H */
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