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1.1 root 1: /* AM53/79C974 (PCscsi) driver release 0.5
2: *
3: * The architecture and much of the code of this device
4: * driver was originally developed by Drew Eckhardt for
5: * the NCR5380. The following copyrights apply:
6: * For the architecture and all parts similar to the NCR5380:
7: * Copyright 1993, Drew Eckhardt
8: * Visionary Computing
9: * (Unix and Linux consulting and custom programming)
10: * [email protected]
11: * +1 (303) 666-5836
12: *
13: * The AM53C974_nobios_detect code was originally developed by
14: * Robin Cutshaw ([email protected]) and is used here in a
15: * modified form.
16: *
17: * For the other parts:
18: * Copyright 1994, D. Frieauff
19: * EMail: [email protected]
20: * Phone: x49-7545-8-2256 , x49-7541-42305
21: */
22:
23: #ifndef AM53C974_H
24: #define AM53C974_H
25:
26: #include <scsi/scsicam.h>
27:
28: /***************************************************************************************
29: * Default setting of the controller's SCSI id. Edit and uncomment this only if your *
30: * BIOS does not correctly initialize the controller's SCSI id. *
31: * If you don't get a warning during boot, it is correctly initialized. *
32: ****************************************************************************************/
33: /* #define AM53C974_SCSI_ID 7 */
34:
35: /***************************************************************************************
36: * Default settings for sync. negotiation enable, transfer rate and sync. offset. *
37: * These settings can be replaced by LILO overrides (append) with the following syntax: *
38: * AM53C974=host-scsi-id, target-scsi-id, max-rate, max-offset *
39: * Sync. negotiation is disabled by default and will be enabled for those targets which *
40: * are specified in the LILO override *
41: ****************************************************************************************/
42: #define DEFAULT_SYNC_NEGOTIATION_ENABLED 0 /* 0 or 1 */
43: #define DEFAULT_RATE 5 /* MHz, min: 3; max: 10 */
44: #define DEFAULT_SYNC_OFFSET 0 /* bytes, min: 0; max: 15; use 0 for async. mode */
45:
46:
47: /* --------------------- don't edit below here --------------------- */
48:
49: #define AM53C974_DRIVER_REVISION_MAJOR 0
50: #define AM53C974_DRIVER_REVISION_MINOR 5
51: #define SEPARATOR_LINE \
52: "--------------------------------------------------------------------------\n"
53:
54: /* debug control */
55: /* #define AM53C974_DEBUG */
56: /* #define AM53C974_DEBUG_MSG */
57: /* #define AM53C974_DEBUG_KEYWAIT */
58: /* #define AM53C974_DEBUG_INIT */
59: /* #define AM53C974_DEBUG_QUEUE */
60: /* #define AM53C974_DEBUG_INFO */
61: /* #define AM53C974_DEBUG_LINKED */
62: /* #define VERBOSE_AM53C974_DEBUG */
63: /* #define AM53C974_DEBUG_INTR */
64: /* #define AM53C974_DEB_RESEL */
65: #define AM53C974_DEBUG_ABORT
66: /* #define AM53C974_OPTION_DEBUG_PROBE_ONLY */
67:
68: /* special options/constants */
69: #define DEF_CLK 40 /* chip clock freq. in MHz */
70: #define MIN_PERIOD 4 /* for negotiation: min. number of clocks per cycle */
71: #define MAX_PERIOD 13 /* for negotiation: max. number of clocks per cycle */
72: #define MAX_OFFSET 15 /* for negotiation: max. offset (0=async) */
73:
74: #define DEF_SCSI_TIMEOUT 245 /* STIMREG value, 40 Mhz */
75: #define DEF_STP 8 /* STPREG value assuming 5.0 MB/sec, FASTCLK, FASTSCSI */
76: #define DEF_SOF_RAD 0 /* REQ/ACK deassertion delay */
77: #define DEF_SOF_RAA 0 /* REQ/ACK assertion delay */
78: #define DEF_ETM 0 /* CNTLREG1, ext. timing mode */
79: #define DEF_PERE 1 /* CNTLREG1, parity error reporting */
80: #define DEF_CLKF 0 /* CLKFREG, 0=40 Mhz */
81: #define DEF_ENF 1 /* CNTLREG2, enable features */
82: #define DEF_ADIDCHK 0 /* CNTLREG3, additional ID check */
83: #define DEF_FASTSCSI 1 /* CNTLREG3, fast SCSI */
84: #define DEF_FASTCLK 1 /* CNTLREG3, fast clocking, 5 MB/sec at 40MHz chip clk */
85: #define DEF_GLITCH 1 /* CNTLREG4, glitch eater, 0=12ns, 1=35ns, 2=25ns, 3=off */
86: #define DEF_PWD 0 /* CNTLREG4, reduced power feature */
87: #define DEF_RAE 0 /* CNTLREG4, RAE active negation on REQ, ACK only */
88: #define DEF_RADE 1 /* 1CNTLREG4, active negation on REQ, ACK and data */
89:
90: /*** PCI block ***/
91: /* standard registers are defined in <linux/pci.h> */
92: #ifndef PCI_VENDOR_ID_AMD
93: #define PCI_VENDOR_ID_AMD 0x1022
94: #define PCI_DEVICE_ID_AMD_SCSI 0x2020
95: #endif
96: #define PCI_BASE_MASK 0xFFFFFFE0
97: #define PCI_COMMAND_PERREN 0x40
98: #define PCI_SCRATCH_REG_0 0x40 /* 16 bits */
99: #define PCI_SCRATCH_REG_1 0x42 /* 16 bits */
100: #define PCI_SCRATCH_REG_2 0x44 /* 16 bits */
101: #define PCI_SCRATCH_REG_3 0x46 /* 16 bits */
102: #define PCI_SCRATCH_REG_4 0x48 /* 16 bits */
103: #define PCI_SCRATCH_REG_5 0x4A /* 16 bits */
104: #define PCI_SCRATCH_REG_6 0x4C /* 16 bits */
105: #define PCI_SCRATCH_REG_7 0x4E /* 16 bits */
106:
107: /*** SCSI block ***/
108: #define CTCLREG 0x00 /* r current transf. count, low byte */
109: #define CTCMREG 0x04 /* r current transf. count, middle byte */
110: #define CTCHREG 0x38 /* r current transf. count, high byte */
111: #define STCLREG 0x00 /* w start transf. count, low byte */
112: #define STCMREG 0x04 /* w start transf. count, middle byte */
113: #define STCHREG 0x38 /* w start transf. count, high byte */
114: #define FFREG 0x08 /* rw SCSI FIFO reg. */
115: #define STIMREG 0x14 /* w SCSI timeout reg. */
116:
117: #define SDIDREG 0x10 /* w SCSI destination ID reg. */
118: #define SDIREG_MASK 0x07 /* mask */
119:
120: #define STPREG 0x18 /* w synchronous transf. period reg. */
121: #define STPREG_STP 0x1F /* synchr. transfer period */
122:
123: #define CLKFREG 0x24 /* w clock factor reg. */
124: #define CLKFREG_MASK 0x07 /* mask */
125:
126: #define CMDREG 0x0C /* rw SCSI command reg. */
127: #define CMDREG_DMA 0x80 /* set DMA mode (set together with opcodes below) */
128: #define CMDREG_IT 0x10 /* information transfer */
129: #define CMDREG_ICCS 0x11 /* initiator command complete steps */
130: #define CMDREG_MA 0x12 /* message accepted */
131: #define CMDREG_TPB 0x98 /* transfer pad bytes, DMA mode only */
132: #define CMDREG_SATN 0x1A /* set ATN */
133: #define CMDREG_RATN 0x1B /* reset ATN */
134: #define CMDREG_SOAS 0x41 /* select without ATN steps */
135: #define CMDREG_SAS 0x42 /* select with ATN steps (1 msg byte) */
136: #define CMDREG_SASS 0x43 /* select with ATN and stop steps */
137: #define CMDREG_ESR 0x44 /* enable selection/reselection */
138: #define CMDREG_DSR 0x45 /* disable selection/reselection */
139: #define CMDREG_SA3S 0x46 /* select with ATN 3 steps (3 msg bytes) */
140: #define CMDREG_NOP 0x00 /* no operation */
141: #define CMDREG_CFIFO 0x01 /* clear FIFO */
142: #define CMDREG_RDEV 0x02 /* reset device */
143: #define CMDREG_RBUS 0x03 /* reset SCSI bus */
144:
145: #define STATREG 0x10 /* r SCSI status reg. */
146: #define STATREG_INT 0x80 /* SCSI interrupt condition detected */
147: #define STATREG_IOE 0x40 /* SCSI illegal operation error detected */
148: #define STATREG_PE 0x20 /* SCSI parity error detected */
149: #define STATREG_CTZ 0x10 /* CTC reg decremented to zero */
150: #define STATREG_MSG 0x04 /* SCSI MSG phase (latched?) */
151: #define STATREG_CD 0x02 /* SCSI C/D phase (latched?) */
152: #define STATREG_IO 0x01 /* SCSI I/O phase (latched?) */
153: #define STATREG_PHASE 0x07 /* SCSI phase mask */
154:
155: #define INSTREG 0x14 /* r interrupt status reg. */
156: #define INSTREG_SRST 0x80 /* SCSI reset detected */
157: #define INSTREG_ICMD 0x40 /* SCSI invalid command detected */
158: #define INSTREG_DIS 0x20 /* target disconnected or sel/resel timeout*/
159: #define INSTREG_SR 0x10 /* device on bus has service request */
160: #define INSTREG_SO 0x08 /* successful operation */
161: #define INSTREG_RESEL 0x04 /* device reselected as initiator */
162:
163: #define ISREG 0x18 /* r internal state reg. */
164: #define ISREG_SOF 0x08 /* synchronous offset flag (act. low) */
165: #define ISREG_IS 0x07 /* status of intermediate op. */
166: #define ISREG_OK_NO_STOP 0x04 /* selection successful */
167: #define ISREG_OK_STOP 0x01 /* selection successful */
168:
169: #define CFIREG 0x1C /* r current FIFO/internal state reg. */
170: #define CFIREG_IS 0xE0 /* status of intermediate op. */
171: #define CFIREG_CF 0x1F /* number of bytes in SCSI FIFO */
172:
173: #define SOFREG 0x1C /* w synchr. offset reg. */
174: #define SOFREG_RAD 0xC0 /* REQ/ACK deassertion delay (sync.) */
175: #define SOFREG_RAA 0x30 /* REQ/ACK assertion delay (sync.) */
176: #define SOFREG_SO 0x0F /* synch. offset (sync.) */
177:
178: #define CNTLREG1 0x20 /* rw control register one */
179: #define CNTLREG1_ETM 0x80 /* set extended timing mode */
180: #define CNTLREG1_DISR 0x40 /* disable interrupt on SCSI reset */
181: #define CNTLREG1_PERE 0x10 /* enable parity error reporting */
182: #define CNTLREG1_SID 0x07 /* host adapter SCSI ID */
183:
184: #define CNTLREG2 0x2C /* rw control register two */
185: #define CNTLREG2_ENF 0x40 /* enable features */
186:
187: #define CNTLREG3 0x30 /* rw control register three */
188: #define CNTLREG3_ADIDCHK 0x80 /* additional ID check */
189: #define CNTLREG3_FASTSCSI 0x10 /* fast SCSI */
190: #define CNTLREG3_FASTCLK 0x08 /* fast SCSI clocking */
191:
192: #define CNTLREG4 0x34 /* rw control register four */
193: #define CNTLREG4_GLITCH 0xC0 /* glitch eater */
194: #define CNTLREG4_PWD 0x20 /* reduced power feature */
195: #define CNTLREG4_RAE 0x08 /* write only, active negot. ctrl. */
196: #define CNTLREG4_RADE 0x04 /* active negot. ctrl. */
197: #define CNTLREG4_RES 0x10 /* reserved bit, must be 1 */
198:
199: /*** DMA block ***/
200: #define DMACMD 0x40 /* rw command */
201: #define DMACMD_DIR 0x80 /* transfer direction (1=read from device) */
202: #define DMACMD_INTE_D 0x40 /* DMA transfer interrupt enable */
203: #define DMACMD_INTE_P 0x20 /* page transfer interrupt enable */
204: #define DMACMD_MDL 0x10 /* map to memory descriptor list */
205: #define DMACMD_DIAG 0x04 /* diagnostics, set to 0 */
206: #define DMACMD_IDLE 0x00 /* idle cmd */
207: #define DMACMD_BLAST 0x01 /* flush FIFO to memory */
208: #define DMACMD_ABORT 0x02 /* terminate DMA */
209: #define DMACMD_START 0x03 /* start DMA */
210:
211: #define DMASTATUS 0x54 /* r status register */
212: #define DMASTATUS_BCMPLT 0x20 /* BLAST complete */
213: #define DMASTATUS_SCSIINT 0x10 /* SCSI interrupt pending */
214: #define DMASTATUS_DONE 0x08 /* DMA transfer terminated */
215: #define DMASTATUS_ABORT 0x04 /* DMA transfer aborted */
216: #define DMASTATUS_ERROR 0x02 /* DMA transfer error */
217: #define DMASTATUS_PWDN 0x02 /* power down indicator */
218:
219: #define DMASTC 0x44 /* rw starting transfer count */
220: #define DMASPA 0x48 /* rw starting physical address */
221: #define DMAWBC 0x4C /* r working byte counter */
222: #define DMAWAC 0x50 /* r working address counter */
223: #define DMASMDLA 0x58 /* rw starting MDL address */
224: #define DMAWMAC 0x5C /* r working MDL counter */
225:
226: /*** SCSI phases ***/
227: #define PHASE_MSGIN 0x07
228: #define PHASE_MSGOUT 0x06
229: #define PHASE_RES_1 0x05
230: #define PHASE_RES_0 0x04
231: #define PHASE_STATIN 0x03
232: #define PHASE_CMDOUT 0x02
233: #define PHASE_DATAIN 0x01
234: #define PHASE_DATAOUT 0x00
235:
236: struct AM53C974_hostdata {
237: volatile unsigned in_reset:1; /* flag, says bus reset pending */
238: volatile unsigned aborted:1; /* flag, says aborted */
239: volatile unsigned selecting:1; /* selection started, but not yet finished */
240: volatile unsigned disconnecting: 1; /* disconnection started, but not yet finished */
241: volatile unsigned dma_busy:1; /* dma busy when service request for info transfer received */
242: volatile unsigned char msgout[10]; /* message to output in MSGOUT_PHASE */
243: volatile unsigned char last_message[10]; /* last message OUT */
244: volatile Scsi_Cmnd *issue_queue; /* waiting to be issued */
245: volatile Scsi_Cmnd *disconnected_queue; /* waiting for reconnect */
246: volatile Scsi_Cmnd *sel_cmd; /* command for selection */
247: volatile Scsi_Cmnd *connected; /* currently connected command */
248: volatile unsigned char busy[8]; /* index = target, bit = lun */
249: unsigned char sync_per[8]; /* synchronous transfer period (in effect) */
250: unsigned char sync_off[8]; /* synchronous offset (in effect) */
251: unsigned char sync_neg[8]; /* sync. negotiation performed (in effect) */
252: unsigned char sync_en[8]; /* sync. negotiation performed (in effect) */
253: unsigned char max_rate[8]; /* max. transfer rate (setup) */
254: unsigned char max_offset[8]; /* max. sync. offset (setup), only valid if corresponding sync_en is nonzero */
255: };
256:
257: #define AM53C974 { \
258: NULL, /* pointer to next in list */ \
259: NULL, /* long * usage_count */ \
260: NULL, /* struct proc_dir_entry *proc_dir */ \
261: NULL, /* int (*proc_info)(char *, char **, off_t, int, int, int); */ \
262: "AM53C974", /* name */ \
263: AM53C974_detect, /* int (* detect)(struct SHT *) */ \
264: NULL, /* int (*release)(struct Scsi_Host *) */ \
265: AM53C974_info, /* const char *(* info)(struct Scsi_Host *) */ \
266: AM53C974_command, /* int (* command)(Scsi_Cmnd *) */ \
267: AM53C974_queue_command, /* int (* queuecommand)(Scsi_Cmnd *, \
268: void (*done)(Scsi_Cmnd *)) */ \
269: AM53C974_abort, /* int (* abort)(Scsi_Cmnd *) */ \
270: AM53C974_reset, /* int (* reset)(Scsi_Cmnd *) */ \
271: NULL, /* int (* slave_attach)(int, int) */ \
272: scsicam_bios_param, /* int (* bios_param)(Disk *, int, int[]) */ \
273: 12, /* can_queue */ \
274: -1, /* this_id */ \
275: SG_ALL, /* sg_tablesize */ \
276: 1, /* cmd_per_lun */ \
277: 0, /* present, i.e. how many adapters of this kind */ \
278: 0, /* unchecked_isa_dma */ \
279: DISABLE_CLUSTERING /* use_clustering */ \
280: }
281:
282: void AM53C974_setup(char *str, int *ints);
283: int AM53C974_detect(Scsi_Host_Template *tpnt);
284: int AM53C974_biosparm(Disk *disk, int dev, int *info_array);
285: const char *AM53C974_info(struct Scsi_Host *);
286: int AM53C974_command(Scsi_Cmnd *SCpnt);
287: int AM53C974_queue_command(Scsi_Cmnd *cmd, void (*done)(Scsi_Cmnd *));
288: int AM53C974_abort(Scsi_Cmnd *cmd);
289: int AM53C974_reset (Scsi_Cmnd *cmd, unsigned int flags);
290:
291: #define AM53C974_local_declare() unsigned long io_port
292: #define AM53C974_setio(instance) io_port = instance->io_port
293: #define AM53C974_read_8(addr) inb(io_port + (addr))
294: #define AM53C974_write_8(addr,x) outb((x), io_port + (addr))
295: #define AM53C974_read_16(addr) inw(io_port + (addr))
296: #define AM53C974_write_16(addr,x) outw((x), io_port + (addr))
297: #define AM53C974_read_32(addr) inl(io_port + (addr))
298: #define AM53C974_write_32(addr,x) outl((x), io_port + (addr))
299:
300: #define AM53C974_poll_int() { do { statreg = AM53C974_read_8(STATREG); } \
301: while (!(statreg & STATREG_INT)) ; \
302: AM53C974_read_8(INSTREG) ; } /* clear int */
303: #define AM53C974_cfifo() (AM53C974_read_8(CFIREG) & CFIREG_CF)
304:
305: /* These are "special" values for the tag parameter passed to AM53C974_select. */
306: #define TAG_NEXT -1 /* Use next free tag */
307: #define TAG_NONE -2 /* Establish I_T_L nexus instead of I_T_L_Q
308: * even on SCSI-II devices */
309:
310: /************ LILO overrides *************/
311: typedef struct _override_t {
312: int host_scsi_id; /* SCSI id of the bus controller */
313: int target_scsi_id; /* SCSI id of target */
314: int max_rate; /* max. transfer rate */
315: int max_offset; /* max. sync. offset, 0 = asynchronous */
316: } override_t;
317:
318: /************ PCI stuff *************/
319: #define AM53C974_PCIREG_OPEN() outb(0xF1, 0xCF8); outb(0, 0xCFA)
320: #define AM53C974_PCIREG_CLOSE() outb(0, 0xCF8)
321: #define AM53C974_PCIREG_READ_BYTE(instance,a) ( inb((a) + (instance)->io_port) )
322: #define AM53C974_PCIREG_READ_WORD(instance,a) ( inw((a) + (instance)->io_port) )
323: #define AM53C974_PCIREG_READ_DWORD(instance,a) ( inl((a) + (instance)->io_port) )
324: #define AM53C974_PCIREG_WRITE_BYTE(instance,x,a) ( outb((x), (a) + (instance)->io_port) )
325: #define AM53C974_PCIREG_WRITE_WORD(instance,x,a) ( outw((x), (a) + (instance)->io_port) )
326: #define AM53C974_PCIREG_WRITE_DWORD(instance,x,a) ( outl((x), (a) + (instance)->io_port) )
327:
328: typedef struct _pci_config_t {
329: /* start of official PCI config space header */
330: union {
331: unsigned int device_vendor;
332: struct {
333: unsigned short vendor;
334: unsigned short device;
335: } dv;
336: } dv_id;
337: #define _device_vendor dv_id.device_vendor
338: #define _vendor dv_id.dv.vendor
339: #define _device dv_id.dv.device
340: union {
341: unsigned int status_command;
342: struct {
343: unsigned short command;
344: unsigned short status;
345: } sc;
346: } stat_cmd;
347: #define _status_command stat_cmd.status_command
348: #define _command stat_cmd.sc.command
349: #define _status stat_cmd.sc.status
350: union {
351: unsigned int class_revision;
352: struct {
353: unsigned char rev_id;
354: unsigned char prog_if;
355: unsigned char sub_class;
356: unsigned char base_class;
357: } cr;
358: } class_rev;
359: #define _class_revision class_rev.class_revision
360: #define _rev_id class_rev.cr.rev_id
361: #define _prog_if class_rev.cr.prog_if
362: #define _sub_class class_rev.cr.sub_class
363: #define _base_class class_rev.cr.base_class
364: union {
365: unsigned int bist_header_latency_cache;
366: struct {
367: unsigned char cache_line_size;
368: unsigned char latency_timer;
369: unsigned char header_type;
370: unsigned char bist;
371: } bhlc;
372: } bhlc;
373: #define _bist_header_latency_cache bhlc.bist_header_latency_cache
374: #define _cache_line_size bhlc.bhlc.cache_line_size
375: #define _latency_timer bhlc.bhlc.latency_timer
376: #define _header_type bhlc.bhlc.header_type
377: #define _bist bhlc.bhlc.bist
378: unsigned int _base0;
379: unsigned int _base1;
380: unsigned int _base2;
381: unsigned int _base3;
382: unsigned int _base4;
383: unsigned int _base5;
384: unsigned int rsvd1;
385: unsigned int rsvd2;
386: unsigned int _baserom;
387: unsigned int rsvd3;
388: unsigned int rsvd4;
389: union {
390: unsigned int max_min_ipin_iline;
391: struct {
392: unsigned char int_line;
393: unsigned char int_pin;
394: unsigned char min_gnt;
395: unsigned char max_lat;
396: } mmii;
397: } mmii;
398: #define _max_min_ipin_iline mmii.max_min_ipin_iline
399: #define _int_line mmii.mmii.int_line
400: #define _int_pin mmii.mmii.int_pin
401: #define _min_gnt mmii.mmii.min_gnt
402: #define _max_lat mmii.mmii.max_lat
403: /* end of official PCI config space header */
404: unsigned short _ioaddr; /* config type 1 - private I/O addr */
405: unsigned int _pcibus; /* config type 2 - private bus id */
406: unsigned int _cardnum; /* config type 2 - private card number */
407: } pci_config_t;
408:
409: #endif /* AM53C974_H */
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