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1.1 root 1: /*
2: * NCR 5380 defines
3: *
4: * Copyright 1993, Drew Eckhardt
5: * Visionary Computing
6: * (Unix consulting and custom programming)
7: * [email protected]
8: * +1 (303) 666-5836
9: *
10: * DISTRIBUTION RELEASE 7
11: *
12: * For more information, please consult
13: *
14: * NCR 5380 Family
15: * SCSI Protocol Controller
16: * Databook
17: * NCR Microelectronics
18: * 1635 Aeroplaza Drive
19: * Colorado Springs, CO 80916
20: * 1+ (719) 578-3400
21: * 1+ (800) 334-5454
22: */
23:
24: /*
25: * $Log: NCR5380.h,v $
26: * Revision 1.1 1999/04/26 05:54:00 tb
27: * 1998-11-30 OKUJI Yoshinori <[email protected]>
28: *
29: * Clean up linux emulation code to make it architecture-independent
30: * as much as possible.
31: *
32: * * linux: Renamed from linuxdev.
33: * * Makefile.in (objfiles): Add linux.o instead of linuxdev.o.
34: * (MAKE): New variable. Used for the linux.o target.
35: * * configure.in: Add AC_CHECK_TOOL(MAKE, make).
36: * * i386/i386/spl.h: Include <i386/ipl.h>, for compatibility with
37: * OSF Mach 3.0. Suggested by Elgin Lee <[email protected]>.
38: * * linux/src: Renamed from linux/linux.
39: * * linux/dev: Renamed from linux/mach.
40: * * linux/Drivers.in (AC_INIT): Use dev/include/linux/autoconf.h,
41: * instead of mach/include/linux/autoconf.h.
42: * * Makefile.in (all): Target ../linux.o instead of ../linuxdev.o.
43: * * linux/dev/drivers/block/genhd.c: Include <machine/spl.h> instead
44: * of <i386/ipl.h>.
45: * * linux/dev/drivers/net/auto_irq.c: Remove unneeded header files,
46: * <i386/ipl.h> and <i386/pic.h>.
47: * * linux/dev/init/main.c: Many i386-dependent codes moved to ...
48: * * linux/dev/arch/i386/irq.c: ... here.
49: * * linux/dev/arch/i386/setup.c: New file.
50: * * linux/dev/arch/i386/linux_emul.h: Likewise.
51: * * linux/dev/arch/i386/glue/timer.c: Merged into sched.c.
52: * * linux/dev/arch/i386/glue/sched.c: Include <machine/spl.h> instead
53: * of <i386/ipl.h>, and moved to ...
54: * * linux/dev/kernel/sched.c: ... here.
55: * * linux/dev/arch/i386/glue/block.c: Include <machine/spl.h> and
56: * <linux_emul.h>, instead of i386-dependent header files, and
57: * moved to ...
58: * * linux/dev/glue/blocl.c: ... here.
59: * * linux/dev/arch/i386/glue/net.c: Include <machine/spl.h> and
60: * <linux_emul.h>, instead of i386-dependent header files, and
61: * moved to ...
62: * * linux/dev/glue/net.c: ... here.
63: * * linux/dev/arch/i386/glue/misc.c: Remove `x86' and moved to ...
64: * * linux/dev/glue/misc.c: ... here.
65: * * linux/dev/arch/i386/glue/kmem.c: Moved to ...
66: * * linux/dev/glue/kmem.c: ... here.
67: *
68: */
69:
70: #ifndef NCR5380_H
71: #define NCR5380_H
72:
73: #define NCR5380_PUBLIC_RELEASE 7
74: #define NCR53C400_PUBLIC_RELEASE 2
75:
76: #define NDEBUG_ARBITRATION 0x1
77: #define NDEBUG_AUTOSENSE 0x2
78: #define NDEBUG_DMA 0x4
79: #define NDEBUG_HANDSHAKE 0x8
80: #define NDEBUG_INFORMATION 0x10
81: #define NDEBUG_INIT 0x20
82: #define NDEBUG_INTR 0x40
83: #define NDEBUG_LINKED 0x80
84: #define NDEBUG_MAIN 0x100
85: #define NDEBUG_NO_DATAOUT 0x200
86: #define NDEBUG_NO_WRITE 0x400
87: #define NDEBUG_PIO 0x800
88: #define NDEBUG_PSEUDO_DMA 0x1000
89: #define NDEBUG_QUEUES 0x2000
90: #define NDEBUG_RESELECTION 0x4000
91: #define NDEBUG_SELECTION 0x8000
92: #define NDEBUG_USLEEP 0x10000
93: #define NDEBUG_LAST_BYTE_SENT 0x20000
94: #define NDEBUG_RESTART_SELECT 0x40000
95: #define NDEBUG_EXTENDED 0x80000
96: #define NDEBUG_C400_PREAD 0x100000
97: #define NDEBUG_C400_PWRITE 0x200000
98: #define NDEBUG_LISTS 0x400000
99:
100: /*
101: * The contents of the OUTPUT DATA register are asserted on the bus when
102: * either arbitration is occurring or the phase-indicating signals (
103: * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
104: * bit in the INITIATOR COMMAND register is set.
105: */
106:
107: #define OUTPUT_DATA_REG 0 /* wo DATA lines on SCSI bus */
108: #define CURRENT_SCSI_DATA_REG 0 /* ro same */
109:
110: #define INITIATOR_COMMAND_REG 1 /* rw */
111: #define ICR_ASSERT_RST 0x80 /* rw Set to assert RST */
112: #define ICR_ARBITRATION_PROGRESS 0x40 /* ro Indicates arbitration complete */
113: #define ICR_TRI_STATE 0x40 /* wo Set to tri-state drivers */
114: #define ICR_ARBITRATION_LOST 0x20 /* ro Indicates arbitration lost */
115: #define ICR_DIFF_ENABLE 0x20 /* wo Set to enable diff. drivers */
116: #define ICR_ASSERT_ACK 0x10 /* rw ini Set to assert ACK */
117: #define ICR_ASSERT_BSY 0x08 /* rw Set to assert BSY */
118: #define ICR_ASSERT_SEL 0x04 /* rw Set to assert SEL */
119: #define ICR_ASSERT_ATN 0x02 /* rw Set to assert ATN */
120: #define ICR_ASSERT_DATA 0x01 /* rw SCSI_DATA_REG is asserted */
121:
122: #ifdef DIFFERENTIAL
123: #define ICR_BASE ICR_DIFF_ENABLE
124: #else
125: #define ICR_BASE 0
126: #endif
127:
128: #define MODE_REG 2
129: /*
130: * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the
131: * transfer, causing the chip to hog the bus. You probably don't want
132: * this.
133: */
134: #define MR_BLOCK_DMA_MODE 0x80 /* rw block mode DMA */
135: #define MR_TARGET 0x40 /* rw target mode */
136: #define MR_ENABLE_PAR_CHECK 0x20 /* rw enable parity checking */
137: #define MR_ENABLE_PAR_INTR 0x10 /* rw enable bad parity interrupt */
138: #define MR_ENABLE_EOP_INTR 0x08 /* rw enable eop interrupt */
139: #define MR_MONITOR_BSY 0x04 /* rw enable int on unexpected bsy fail */
140: #define MR_DMA_MODE 0x02 /* rw DMA / pseudo DMA mode */
141: #define MR_ARBITRATE 0x01 /* rw start arbitration */
142:
143: #ifdef PARITY
144: #define MR_BASE MR_ENABLE_PAR_CHECK
145: #else
146: #define MR_BASE 0
147: #endif
148:
149: #define TARGET_COMMAND_REG 3
150: #define TCR_LAST_BYTE_SENT 0x80 /* ro DMA done */
151: #define TCR_ASSERT_REQ 0x08 /* tgt rw assert REQ */
152: #define TCR_ASSERT_MSG 0x04 /* tgt rw assert MSG */
153: #define TCR_ASSERT_CD 0x02 /* tgt rw assert CD */
154: #define TCR_ASSERT_IO 0x01 /* tgt rw assert IO */
155:
156: #define STATUS_REG 4 /* ro */
157: /*
158: * Note : a set bit indicates an active signal, driven by us or another
159: * device.
160: */
161: #define SR_RST 0x80
162: #define SR_BSY 0x40
163: #define SR_REQ 0x20
164: #define SR_MSG 0x10
165: #define SR_CD 0x08
166: #define SR_IO 0x04
167: #define SR_SEL 0x02
168: #define SR_DBP 0x01
169:
170: /*
171: * Setting a bit in this register will cause an interrupt to be generated when
172: * BSY is false and SEL true and this bit is asserted on the bus.
173: */
174: #define SELECT_ENABLE_REG 4 /* wo */
175:
176: #define BUS_AND_STATUS_REG 5 /* ro */
177: #define BASR_END_DMA_TRANSFER 0x80 /* ro set on end of transfer */
178: #define BASR_DRQ 0x40 /* ro mirror of DRQ pin */
179: #define BASR_PARITY_ERROR 0x20 /* ro parity error detected */
180: #define BASR_IRQ 0x10 /* ro mirror of IRQ pin */
181: #define BASR_PHASE_MATCH 0x08 /* ro Set when MSG CD IO match TCR */
182: #define BASR_BUSY_ERROR 0x04 /* ro Unexpected change to inactive state */
183: #define BASR_ATN 0x02 /* ro BUS status */
184: #define BASR_ACK 0x01 /* ro BUS status */
185:
186: /* Write any value to this register to start a DMA send */
187: #define START_DMA_SEND_REG 5 /* wo */
188:
189: /*
190: * Used in DMA transfer mode, data is latched from the SCSI bus on
191: * the falling edge of REQ (ini) or ACK (tgt)
192: */
193: #define INPUT_DATA_REG 6 /* ro */
194:
195: /* Write any value to this register to start a DMA receive */
196: #define START_DMA_TARGET_RECEIVE_REG 6 /* wo */
197:
198: /* Read this register to clear interrupt conditions */
199: #define RESET_PARITY_INTERRUPT_REG 7 /* ro */
200:
201: /* Write any value to this register to start an ini mode DMA receive */
202: #define START_DMA_INITIATOR_RECEIVE_REG 7 /* wo */
203:
204: #define C400_CONTROL_STATUS_REG NCR53C400_register_offset-8 /* rw */
205:
206: #define CSR_RESET 0x80 /* wo Resets 53c400 */
207: #define CSR_53C80_REG 0x80 /* ro 5380 registers busy */
208: #define CSR_TRANS_DIR 0x40 /* rw Data transfer direction */
209: #define CSR_SCSI_BUFF_INTR 0x20 /* rw Enable int on transfer ready */
210: #define CSR_53C80_INTR 0x10 /* rw Enable 53c80 interrupts */
211: #define CSR_SHARED_INTR 0x08 /* rw Interrupt sharing */
212: #define CSR_HOST_BUF_NOT_RDY 0x04 /* ro Is Host buffer ready */
213: #define CSR_SCSI_BUF_RDY 0x02 /* ro SCSI buffer read */
214: #define CSR_GATED_53C80_IRQ 0x01 /* ro Last block xferred */
215:
216: #if 0
217: #define CSR_BASE CSR_SCSI_BUFF_INTR | CSR_53C80_INTR
218: #else
219: #define CSR_BASE CSR_53C80_INTR
220: #endif
221:
222: /* Number of 128-byte blocks to be transferred */
223: #define C400_BLOCK_COUNTER_REG NCR53C400_register_offset-7 /* rw */
224:
225: /* Resume transfer after disconnect */
226: #define C400_RESUME_TRANSFER_REG NCR53C400_register_offset-6 /* wo */
227:
228: /* Access to host buffer stack */
229: #define C400_HOST_BUFFER NCR53C400_register_offset-4 /* rw */
230:
231:
232: /* Note : PHASE_* macros are based on the values of the STATUS register */
233: #define PHASE_MASK (SR_MSG | SR_CD | SR_IO)
234:
235: #define PHASE_DATAOUT 0
236: #define PHASE_DATAIN SR_IO
237: #define PHASE_CMDOUT SR_CD
238: #define PHASE_STATIN (SR_CD | SR_IO)
239: #define PHASE_MSGOUT (SR_MSG | SR_CD)
240: #define PHASE_MSGIN (SR_MSG | SR_CD | SR_IO)
241: #define PHASE_UNKNOWN 0xff
242:
243: /*
244: * Convert status register phase to something we can use to set phase in
245: * the target register so we can get phase mismatch interrupts on DMA
246: * transfers.
247: */
248:
249: #define PHASE_SR_TO_TCR(phase) ((phase) >> 2)
250:
251: /*
252: * The internal should_disconnect() function returns these based on the
253: * expected length of a disconnect if a device supports disconnect/
254: * reconnect.
255: */
256:
257: #define DISCONNECT_NONE 0
258: #define DISCONNECT_TIME_TO_DATA 1
259: #define DISCONNECT_LONG 2
260:
261: /*
262: * These are "special" values for the tag parameter passed to NCR5380_select.
263: */
264:
265: #define TAG_NEXT -1 /* Use next free tag */
266: #define TAG_NONE -2 /*
267: * Establish I_T_L nexus instead of I_T_L_Q
268: * even on SCSI-II devices.
269: */
270:
271: /*
272: * These are "special" values for the irq and dma_channel fields of the
273: * Scsi_Host structure
274: */
275:
276: #define IRQ_NONE 255
277: #define DMA_NONE 255
278: #define IRQ_AUTO 254
279: #define DMA_AUTO 254
280:
281: #define FLAG_HAS_LAST_BYTE_SENT 1 /* NCR53c81 or better */
282: #define FLAG_CHECK_LAST_BYTE_SENT 2 /* Only test once */
283: #define FLAG_NCR53C400 4 /* NCR53c400 */
284: #define FLAG_NO_PSEUDO_DMA 8 /* Inhibit DMA */
285:
286: #ifndef ASM
287: struct NCR5380_hostdata {
288: NCR5380_implementation_fields; /* implementation specific */
289: unsigned char id_mask, id_higher_mask; /* 1 << id, all bits greater */
290: unsigned char targets_present; /* targets we have connected
291: to, so we can call a select
292: failure a retryable condition */
293: volatile unsigned char busy[8]; /* index = target, bit = lun */
294: #if defined(REAL_DMA) || defined(REAL_DMA_POLL)
295: volatile int dma_len; /* requested length of DMA */
296: #endif
297: volatile unsigned char last_message; /* last message OUT */
298: volatile Scsi_Cmnd *connected; /* currently connected command */
299: volatile Scsi_Cmnd *issue_queue; /* waiting to be issued */
300: volatile Scsi_Cmnd *disconnected_queue; /* waiting for reconnect */
301: volatile int restart_select; /* we have disconnected,
302: used to restart
303: NCR5380_select() */
304: volatile unsigned aborted:1; /* flag, says aborted */
305: int flags;
306: #ifdef USLEEP
307: unsigned long time_expires; /* in jiffies, set prior to sleeping */
308: struct Scsi_Host *next_timer;
309: #endif
310: #ifdef NCR5380_STATS
311: unsigned timebase; /* Base for time calcs */
312: long time_read[8]; /* time to do reads */
313: long time_write[8]; /* time to do writes */
314: unsigned long bytes_read[8]; /* bytes read */
315: unsigned long bytes_write[8]; /* bytes written */
316: unsigned pendingr;
317: unsigned pendingw;
318: #endif
319: };
320:
321: #ifdef __KERNEL__
322: static struct Scsi_Host *first_instance; /* linked list of 5380's */
323:
324: #if defined(AUTOPROBE_IRQ)
325: static int NCR5380_probe_irq (struct Scsi_Host *instance, int possible);
326: #endif
327: static void NCR5380_init (struct Scsi_Host *instance, int flags);
328: static void NCR5380_information_transfer (struct Scsi_Host *instance);
329: #ifndef DONT_USE_INTR
330: static void NCR5380_intr (int irq, void *dev_id, struct pt_regs * regs);
331: #endif
332: static void NCR5380_main (void);
333: static void NCR5380_print_options (struct Scsi_Host *instance);
334: static void NCR5380_print_phase (struct Scsi_Host *instance);
335: static void NCR5380_print (struct Scsi_Host *instance);
336: #ifndef NCR5380_abort
337: static
338: #endif
339: int NCR5380_abort (Scsi_Cmnd *cmd);
340: #ifndef NCR5380_reset
341: static
342: #endif
343: int NCR5380_reset (Scsi_Cmnd *cmd, unsigned int reset_flags);
344: #ifndef NCR5380_queue_command
345: static
346: #endif
347: int NCR5380_queue_command (Scsi_Cmnd *cmd, void (*done)(Scsi_Cmnd *));
348:
349:
350: static void NCR5380_reselect (struct Scsi_Host *instance);
351: static int NCR5380_select (struct Scsi_Host *instance, Scsi_Cmnd *cmd, int tag);
352: #if defined(PSEUDO_DMA) || defined(REAL_DMA) || defined(REAL_DMA_POLL)
353: static int NCR5380_transfer_dma (struct Scsi_Host *instance,
354: unsigned char *phase, int *count, unsigned char **data);
355: #endif
356: static int NCR5380_transfer_pio (struct Scsi_Host *instance,
357: unsigned char *phase, int *count, unsigned char **data);
358:
359: #if (defined(REAL_DMA) || defined(REAL_DMA_POLL))
360:
361: #if defined(i386) || defined(__alpha__)
362:
363: static __inline__ int NCR5380_pc_dma_setup (struct Scsi_Host *instance,
364: unsigned char *ptr, unsigned int count, unsigned char mode) {
365: unsigned limit;
366: unsigned long bus_addr = virt_to_bus(ptr);
367:
368: if (instance->dma_channel <=3) {
369: if (count > 65536)
370: count = 65536;
371: limit = 65536 - (bus_addr & 0xFFFF);
372: } else {
373: if (count > 65536 * 2)
374: count = 65536 * 2;
375: limit = 65536* 2 - (bus_addr & 0x1FFFF);
376: }
377:
378: if (count > limit) count = limit;
379:
380: if ((count & 1) || (bus_addr & 1))
381: panic ("scsi%d : attempted unaligned DMA transfer\n", instance->host_no);
382: cli();
383: disable_dma(instance->dma_channel);
384: clear_dma_ff(instance->dma_channel);
385: set_dma_addr(instance->dma_channel, bus_addr);
386: set_dma_count(instance->dma_channel, count);
387: set_dma_mode(instance->dma_channel, mode);
388: enable_dma(instance->dma_channel);
389: sti();
390: return count;
391: }
392:
393: static __inline__ int NCR5380_pc_dma_write_setup (struct Scsi_Host *instance,
394: unsigned char *src, unsigned int count) {
395: return NCR5380_pc_dma_setup (instance, src, count, DMA_MODE_WRITE);
396: }
397:
398: static __inline__ int NCR5380_pc_dma_read_setup (struct Scsi_Host *instance,
399: unsigned char *src, unsigned int count) {
400: return NCR5380_pc_dma_setup (instance, src, count, DMA_MODE_READ);
401: }
402:
403: static __inline__ int NCR5380_pc_dma_residual (struct Scsi_Host *instance) {
404: register int tmp;
405: cli();
406: clear_dma_ff(instance->dma_channel);
407: tmp = get_dma_residue(instance->dma_channel);
408: sti();
409: return tmp;
410: }
411: #endif /* defined(i386) || defined(__alpha__) */
412: #endif /* defined(REAL_DMA) */
413: #endif __KERNEL_
414: #endif /* ndef ASM */
415: #endif /* NCR5380_H */
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