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1.1 root 1: /*
2: * NCR 5380 defines
3: *
4: * Copyright 1993, Drew Eckhardt
5: * Visionary Computing
6: * (Unix consulting and custom programming)
7: * [email protected]
8: * +1 (303) 666-5836
9: *
10: * DISTRIBUTION RELEASE 7
11: *
12: * For more information, please consult
13: *
14: * NCR 5380 Family
15: * SCSI Protocol Controller
16: * Databook
17: * NCR Microelectronics
18: * 1635 Aeroplaza Drive
19: * Colorado Springs, CO 80916
20: * 1+ (719) 578-3400
21: * 1+ (800) 334-5454
22: */
23:
24: #ifndef NCR5380_H
25: #define NCR5380_H
26:
27: #define NCR5380_PUBLIC_RELEASE 7
28: #define NCR53C400_PUBLIC_RELEASE 2
29:
30: #define NDEBUG_ARBITRATION 0x1
31: #define NDEBUG_AUTOSENSE 0x2
32: #define NDEBUG_DMA 0x4
33: #define NDEBUG_HANDSHAKE 0x8
34: #define NDEBUG_INFORMATION 0x10
35: #define NDEBUG_INIT 0x20
36: #define NDEBUG_INTR 0x40
37: #define NDEBUG_LINKED 0x80
38: #define NDEBUG_MAIN 0x100
39: #define NDEBUG_NO_DATAOUT 0x200
40: #define NDEBUG_NO_WRITE 0x400
41: #define NDEBUG_PIO 0x800
42: #define NDEBUG_PSEUDO_DMA 0x1000
43: #define NDEBUG_QUEUES 0x2000
44: #define NDEBUG_RESELECTION 0x4000
45: #define NDEBUG_SELECTION 0x8000
46: #define NDEBUG_USLEEP 0x10000
47: #define NDEBUG_LAST_BYTE_SENT 0x20000
48: #define NDEBUG_RESTART_SELECT 0x40000
49: #define NDEBUG_EXTENDED 0x80000
50: #define NDEBUG_C400_PREAD 0x100000
51: #define NDEBUG_C400_PWRITE 0x200000
52: #define NDEBUG_LISTS 0x400000
53:
54: /*
55: * The contents of the OUTPUT DATA register are asserted on the bus when
56: * either arbitration is occurring or the phase-indicating signals (
57: * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
58: * bit in the INITIATOR COMMAND register is set.
59: */
60:
61: #define OUTPUT_DATA_REG 0 /* wo DATA lines on SCSI bus */
62: #define CURRENT_SCSI_DATA_REG 0 /* ro same */
63:
64: #define INITIATOR_COMMAND_REG 1 /* rw */
65: #define ICR_ASSERT_RST 0x80 /* rw Set to assert RST */
66: #define ICR_ARBITRATION_PROGRESS 0x40 /* ro Indicates arbitration complete */
67: #define ICR_TRI_STATE 0x40 /* wo Set to tri-state drivers */
68: #define ICR_ARBITRATION_LOST 0x20 /* ro Indicates arbitration lost */
69: #define ICR_DIFF_ENABLE 0x20 /* wo Set to enable diff. drivers */
70: #define ICR_ASSERT_ACK 0x10 /* rw ini Set to assert ACK */
71: #define ICR_ASSERT_BSY 0x08 /* rw Set to assert BSY */
72: #define ICR_ASSERT_SEL 0x04 /* rw Set to assert SEL */
73: #define ICR_ASSERT_ATN 0x02 /* rw Set to assert ATN */
74: #define ICR_ASSERT_DATA 0x01 /* rw SCSI_DATA_REG is asserted */
75:
76: #ifdef DIFFERENTIAL
77: #define ICR_BASE ICR_DIFF_ENABLE
78: #else
79: #define ICR_BASE 0
80: #endif
81:
82: #define MODE_REG 2
83: /*
84: * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the
85: * transfer, causing the chip to hog the bus. You probably don't want
86: * this.
87: */
88: #define MR_BLOCK_DMA_MODE 0x80 /* rw block mode DMA */
89: #define MR_TARGET 0x40 /* rw target mode */
90: #define MR_ENABLE_PAR_CHECK 0x20 /* rw enable parity checking */
91: #define MR_ENABLE_PAR_INTR 0x10 /* rw enable bad parity interrupt */
92: #define MR_ENABLE_EOP_INTR 0x08 /* rw enable eop interrupt */
93: #define MR_MONITOR_BSY 0x04 /* rw enable int on unexpected bsy fail */
94: #define MR_DMA_MODE 0x02 /* rw DMA / pseudo DMA mode */
95: #define MR_ARBITRATE 0x01 /* rw start arbitration */
96:
97: #ifdef PARITY
98: #define MR_BASE MR_ENABLE_PAR_CHECK
99: #else
100: #define MR_BASE 0
101: #endif
102:
103: #define TARGET_COMMAND_REG 3
104: #define TCR_LAST_BYTE_SENT 0x80 /* ro DMA done */
105: #define TCR_ASSERT_REQ 0x08 /* tgt rw assert REQ */
106: #define TCR_ASSERT_MSG 0x04 /* tgt rw assert MSG */
107: #define TCR_ASSERT_CD 0x02 /* tgt rw assert CD */
108: #define TCR_ASSERT_IO 0x01 /* tgt rw assert IO */
109:
110: #define STATUS_REG 4 /* ro */
111: /*
112: * Note : a set bit indicates an active signal, driven by us or another
113: * device.
114: */
115: #define SR_RST 0x80
116: #define SR_BSY 0x40
117: #define SR_REQ 0x20
118: #define SR_MSG 0x10
119: #define SR_CD 0x08
120: #define SR_IO 0x04
121: #define SR_SEL 0x02
122: #define SR_DBP 0x01
123:
124: /*
125: * Setting a bit in this register will cause an interrupt to be generated when
126: * BSY is false and SEL true and this bit is asserted on the bus.
127: */
128: #define SELECT_ENABLE_REG 4 /* wo */
129:
130: #define BUS_AND_STATUS_REG 5 /* ro */
131: #define BASR_END_DMA_TRANSFER 0x80 /* ro set on end of transfer */
132: #define BASR_DRQ 0x40 /* ro mirror of DRQ pin */
133: #define BASR_PARITY_ERROR 0x20 /* ro parity error detected */
134: #define BASR_IRQ 0x10 /* ro mirror of IRQ pin */
135: #define BASR_PHASE_MATCH 0x08 /* ro Set when MSG CD IO match TCR */
136: #define BASR_BUSY_ERROR 0x04 /* ro Unexpected change to inactive state */
137: #define BASR_ATN 0x02 /* ro BUS status */
138: #define BASR_ACK 0x01 /* ro BUS status */
139:
140: /* Write any value to this register to start a DMA send */
141: #define START_DMA_SEND_REG 5 /* wo */
142:
143: /*
144: * Used in DMA transfer mode, data is latched from the SCSI bus on
145: * the falling edge of REQ (ini) or ACK (tgt)
146: */
147: #define INPUT_DATA_REG 6 /* ro */
148:
149: /* Write any value to this register to start a DMA receive */
150: #define START_DMA_TARGET_RECEIVE_REG 6 /* wo */
151:
152: /* Read this register to clear interrupt conditions */
153: #define RESET_PARITY_INTERRUPT_REG 7 /* ro */
154:
155: /* Write any value to this register to start an ini mode DMA receive */
156: #define START_DMA_INITIATOR_RECEIVE_REG 7 /* wo */
157:
158: #define C400_CONTROL_STATUS_REG NCR53C400_register_offset-8 /* rw */
159:
160: #define CSR_RESET 0x80 /* wo Resets 53c400 */
161: #define CSR_53C80_REG 0x80 /* ro 5380 registers busy */
162: #define CSR_TRANS_DIR 0x40 /* rw Data transfer direction */
163: #define CSR_SCSI_BUFF_INTR 0x20 /* rw Enable int on transfer ready */
164: #define CSR_53C80_INTR 0x10 /* rw Enable 53c80 interrupts */
165: #define CSR_SHARED_INTR 0x08 /* rw Interrupt sharing */
166: #define CSR_HOST_BUF_NOT_RDY 0x04 /* ro Is Host buffer ready */
167: #define CSR_SCSI_BUF_RDY 0x02 /* ro SCSI buffer read */
168: #define CSR_GATED_53C80_IRQ 0x01 /* ro Last block xferred */
169:
170: #if 0
171: #define CSR_BASE CSR_SCSI_BUFF_INTR | CSR_53C80_INTR
172: #else
173: #define CSR_BASE CSR_53C80_INTR
174: #endif
175:
176: /* Number of 128-byte blocks to be transferred */
177: #define C400_BLOCK_COUNTER_REG NCR53C400_register_offset-7 /* rw */
178:
179: /* Resume transfer after disconnect */
180: #define C400_RESUME_TRANSFER_REG NCR53C400_register_offset-6 /* wo */
181:
182: /* Access to host buffer stack */
183: #define C400_HOST_BUFFER NCR53C400_register_offset-4 /* rw */
184:
185:
186: /* Note : PHASE_* macros are based on the values of the STATUS register */
187: #define PHASE_MASK (SR_MSG | SR_CD | SR_IO)
188:
189: #define PHASE_DATAOUT 0
190: #define PHASE_DATAIN SR_IO
191: #define PHASE_CMDOUT SR_CD
192: #define PHASE_STATIN (SR_CD | SR_IO)
193: #define PHASE_MSGOUT (SR_MSG | SR_CD)
194: #define PHASE_MSGIN (SR_MSG | SR_CD | SR_IO)
195: #define PHASE_UNKNOWN 0xff
196:
197: /*
198: * Convert status register phase to something we can use to set phase in
199: * the target register so we can get phase mismatch interrupts on DMA
200: * transfers.
201: */
202:
203: #define PHASE_SR_TO_TCR(phase) ((phase) >> 2)
204:
205: /*
206: * The internal should_disconnect() function returns these based on the
207: * expected length of a disconnect if a device supports disconnect/
208: * reconnect.
209: */
210:
211: #define DISCONNECT_NONE 0
212: #define DISCONNECT_TIME_TO_DATA 1
213: #define DISCONNECT_LONG 2
214:
215: /*
216: * These are "special" values for the tag parameter passed to NCR5380_select.
217: */
218:
219: #define TAG_NEXT -1 /* Use next free tag */
220: #define TAG_NONE -2 /*
221: * Establish I_T_L nexus instead of I_T_L_Q
222: * even on SCSI-II devices.
223: */
224:
225: /*
226: * These are "special" values for the irq and dma_channel fields of the
227: * Scsi_Host structure
228: */
229:
230: #define IRQ_NONE 255
231: #define DMA_NONE 255
232: #define IRQ_AUTO 254
233: #define DMA_AUTO 254
234:
235: #define FLAG_HAS_LAST_BYTE_SENT 1 /* NCR53c81 or better */
236: #define FLAG_CHECK_LAST_BYTE_SENT 2 /* Only test once */
237: #define FLAG_NCR53C400 4 /* NCR53c400 */
238: #define FLAG_NO_PSEUDO_DMA 8 /* Inhibit DMA */
239:
240: #ifndef ASM
241: struct NCR5380_hostdata {
242: NCR5380_implementation_fields; /* implementation specific */
243: unsigned char id_mask, id_higher_mask; /* 1 << id, all bits greater */
244: unsigned char targets_present; /* targets we have connected
245: to, so we can call a select
246: failure a retryable condition */
247: volatile unsigned char busy[8]; /* index = target, bit = lun */
248: #if defined(REAL_DMA) || defined(REAL_DMA_POLL)
249: volatile int dma_len; /* requested length of DMA */
250: #endif
251: volatile unsigned char last_message; /* last message OUT */
252: volatile Scsi_Cmnd *connected; /* currently connected command */
253: volatile Scsi_Cmnd *issue_queue; /* waiting to be issued */
254: volatile Scsi_Cmnd *disconnected_queue; /* waiting for reconnect */
255: volatile int restart_select; /* we have disconnected,
256: used to restart
257: NCR5380_select() */
258: volatile unsigned aborted:1; /* flag, says aborted */
259: int flags;
260: #ifdef USLEEP
261: unsigned long time_expires; /* in jiffies, set prior to sleeping */
262: struct Scsi_Host *next_timer;
263: #endif
264: #ifdef NCR5380_STATS
265: unsigned timebase; /* Base for time calcs */
266: long time_read[8]; /* time to do reads */
267: long time_write[8]; /* time to do writes */
268: unsigned long bytes_read[8]; /* bytes read */
269: unsigned long bytes_write[8]; /* bytes written */
270: unsigned pendingr;
271: unsigned pendingw;
272: #endif
273: };
274:
275: #ifdef __KERNEL__
276: static struct Scsi_Host *first_instance; /* linked list of 5380's */
277:
278: #if defined(AUTOPROBE_IRQ)
279: static int NCR5380_probe_irq (struct Scsi_Host *instance, int possible);
280: #endif
281: static void NCR5380_init (struct Scsi_Host *instance, int flags);
282: static void NCR5380_information_transfer (struct Scsi_Host *instance);
283: #ifndef DONT_USE_INTR
284: static void NCR5380_intr (int irq, void *dev_id, struct pt_regs * regs);
285: #endif
286: static void NCR5380_main (void);
287: static void NCR5380_print_options (struct Scsi_Host *instance);
288: static void NCR5380_print_phase (struct Scsi_Host *instance);
289: static void NCR5380_print (struct Scsi_Host *instance);
290: #ifndef NCR5380_abort
291: static
292: #endif
293: int NCR5380_abort (Scsi_Cmnd *cmd);
294: #ifndef NCR5380_reset
295: static
296: #endif
297: int NCR5380_reset (Scsi_Cmnd *cmd, unsigned int reset_flags);
298: #ifndef NCR5380_queue_command
299: static
300: #endif
301: int NCR5380_queue_command (Scsi_Cmnd *cmd, void (*done)(Scsi_Cmnd *));
302:
303:
304: static void NCR5380_reselect (struct Scsi_Host *instance);
305: static int NCR5380_select (struct Scsi_Host *instance, Scsi_Cmnd *cmd, int tag);
306: #if defined(PSEUDO_DMA) || defined(REAL_DMA) || defined(REAL_DMA_POLL)
307: static int NCR5380_transfer_dma (struct Scsi_Host *instance,
308: unsigned char *phase, int *count, unsigned char **data);
309: #endif
310: static int NCR5380_transfer_pio (struct Scsi_Host *instance,
311: unsigned char *phase, int *count, unsigned char **data);
312:
313: #if (defined(REAL_DMA) || defined(REAL_DMA_POLL))
314:
315: #if defined(i386) || defined(__alpha__)
316:
317: static __inline__ int NCR5380_pc_dma_setup (struct Scsi_Host *instance,
318: unsigned char *ptr, unsigned int count, unsigned char mode) {
319: unsigned limit;
320: unsigned long bus_addr = virt_to_bus(ptr);
321:
322: if (instance->dma_channel <=3) {
323: if (count > 65536)
324: count = 65536;
325: limit = 65536 - (bus_addr & 0xFFFF);
326: } else {
327: if (count > 65536 * 2)
328: count = 65536 * 2;
329: limit = 65536* 2 - (bus_addr & 0x1FFFF);
330: }
331:
332: if (count > limit) count = limit;
333:
334: if ((count & 1) || (bus_addr & 1))
335: panic ("scsi%d : attempted unaligned DMA transfer\n", instance->host_no);
336: cli();
337: disable_dma(instance->dma_channel);
338: clear_dma_ff(instance->dma_channel);
339: set_dma_addr(instance->dma_channel, bus_addr);
340: set_dma_count(instance->dma_channel, count);
341: set_dma_mode(instance->dma_channel, mode);
342: enable_dma(instance->dma_channel);
343: sti();
344: return count;
345: }
346:
347: static __inline__ int NCR5380_pc_dma_write_setup (struct Scsi_Host *instance,
348: unsigned char *src, unsigned int count) {
349: return NCR5380_pc_dma_setup (instance, src, count, DMA_MODE_WRITE);
350: }
351:
352: static __inline__ int NCR5380_pc_dma_read_setup (struct Scsi_Host *instance,
353: unsigned char *src, unsigned int count) {
354: return NCR5380_pc_dma_setup (instance, src, count, DMA_MODE_READ);
355: }
356:
357: static __inline__ int NCR5380_pc_dma_residual (struct Scsi_Host *instance) {
358: register int tmp;
359: cli();
360: clear_dma_ff(instance->dma_channel);
361: tmp = get_dma_residue(instance->dma_channel);
362: sti();
363: return tmp;
364: }
365: #endif /* defined(i386) || defined(__alpha__) */
366: #endif /* defined(REAL_DMA) */
367: #endif __KERNEL_
368: #endif /* ndef ASM */
369: #endif /* NCR5380_H */
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