![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to dtc.h CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [GnuMach] / Gnu-Mach / linux / src / drivers / scsi|
Return to dtc.h CVS log | Up to [GnuMach] / Gnu-Mach / linux / src / drivers / scsi |
1.1 root 1: /*
2: * DTC controller, taken from T128 driver by...
3: * Copyright 1993, Drew Eckhardt
4: * Visionary Computing
5: * (Unix and Linux consulting and custom programming)
6: * [email protected]
7: * +1 (303) 440-4894
8: *
9: * DISTRIBUTION RELEASE 1.
10: *
11: * For more information, please consult
12: *
13: *
14: *
15: * and
16: *
17: * NCR 5380 Family
18: * SCSI Protocol Controller
19: * Databook
20: *
21: * NCR Microelectronics
22: * 1635 Aeroplaza Drive
23: * Colorado Springs, CO 80916
24: * 1+ (719) 578-3400
25: * 1+ (800) 334-5454
26: */
27:
28: #ifndef DTC3280_H
29: #define DTC3280_H
30:
31: #define DTC_PUBLIC_RELEASE 1
32:
33: /*#define DTCDEBUG 0x1*/
34: #define DTCDEBUG_INIT 0x1
35: #define DTCDEBUG_TRANSFER 0x2
36:
37: /*
38: * The DTC3180 & 3280 boards are memory mapped.
39: *
40: */
41:
42: /*
43: */
44: /* Offset from DTC_5380_OFFSET */
45: #define DTC_CONTROL_REG 0x100 /* rw */
46: #define D_CR_ACCESS 0x80 /* ro set=can access 3280 registers */
47: #define CSR_DIR_READ 0x40 /* rw direction, 1 = read 0 = write */
48:
49: #define CSR_RESET 0x80 /* wo Resets 53c400 */
50: #define CSR_5380_REG 0x80 /* ro 5380 registers can be accessed */
51: #define CSR_TRANS_DIR 0x40 /* rw Data transfer direction */
52: #define CSR_SCSI_BUFF_INTR 0x20 /* rw Enable int on transfer ready */
53: #define CSR_5380_INTR 0x10 /* rw Enable 5380 interrupts */
54: #define CSR_SHARED_INTR 0x08 /* rw Interrupt sharing */
55: #define CSR_HOST_BUF_NOT_RDY 0x04 /* ro Host buffer not ready */
56: #define CSR_SCSI_BUF_RDY 0x02 /* ro SCSI buffer ready */
57: #define CSR_GATED_5380_IRQ 0x01 /* ro Last block xferred */
58: #define CSR_INT_BASE (CSR_SCSI_BUFF_INTR | CSR_5380_INTR)
59:
60:
61: #define DTC_BLK_CNT 0x101 /* rw
62: * # of 128-byte blocks to transfer */
63:
64:
65: #define D_CR_ACCESS 0x80 /* ro set=can access 3280 registers */
66:
67: #define DTC_SWITCH_REG 0x3982 /* ro - DIP switches */
68: #define DTC_RESUME_XFER 0x3982 /* wo - resume data xfer
69: * after disconnect/reconnect*/
70:
71: #define DTC_5380_OFFSET 0x3880 /* 8 registers here, see NCR5380.h */
72:
73: /*!!!! for dtc, it's a 128 byte buffer at 3900 !!! */
74: #define DTC_DATA_BUF 0x3900 /* rw 128 bytes long */
75:
76:
77: #ifndef ASM
78: int dtc_abort(Scsi_Cmnd *);
79: int dtc_biosparam(Disk *, kdev_t, int*);
80: int dtc_detect(Scsi_Host_Template *);
81: int dtc_queue_command(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
82: int dtc_reset(Scsi_Cmnd *, unsigned int reset_flags);
83: int dtc_proc_info (char *buffer, char **start, off_t offset,
84: int length, int hostno, int inout);
85:
86: #ifndef NULL
87: #define NULL 0
88: #endif
89:
90: #ifndef CMD_PER_LUN
91: #define CMD_PER_LUN 2
92: #endif
93:
94: #ifndef CAN_QUEUE
95: #define CAN_QUEUE 32
96: #endif
97:
98: /*
99: * I hadn't thought of this with the earlier drivers - but to prevent
100: * macro definition conflicts, we shouldn't define all of the internal
101: * macros when this is being used solely for the host stub.
102: */
103:
104: #if defined(HOSTS_C) || defined(MODULE)
105:
106: #define DTC3x80 {NULL, NULL, NULL, NULL, \
107: "DTC 3180/3280 ", dtc_detect, NULL, \
108: NULL, \
109: NULL, dtc_queue_command, dtc_abort, dtc_reset, NULL, \
110: dtc_biosparam, \
111: /* can queue */ CAN_QUEUE, /* id */ 7, SG_ALL, \
112: /* cmd per lun */ CMD_PER_LUN , 0, 0, DISABLE_CLUSTERING}
113:
114: #endif
115:
116: #ifndef HOSTS_C
117:
118: #define NCR5380_implementation_fields \
119: volatile unsigned char *base
120:
121: #define NCR5380_local_declare() \
122: volatile unsigned char *base
123:
124: #define NCR5380_setup(instance) \
125: base = (volatile unsigned char *) (instance)->base
126:
127: #define DTC_address(reg) (base + DTC_5380_OFFSET + reg)
128:
129: #define dbNCR5380_read(reg) \
130: (rval=*(DTC_address(reg)), \
131: (((unsigned char) printk("DTC : read register %d at addr %08x is: %02x\n"\
132: , (reg), (int)DTC_address(reg), rval)), rval ) )
133:
134: #define dbNCR5380_write(reg, value) do { \
135: printk("DTC : write %02x to register %d at address %08x\n", \
136: (value), (reg), (int)DTC_address(reg)); \
137: *(DTC_address(reg)) = (value);} while(0)
138:
139:
140: #if !(DTCDEBUG & DTCDEBUG_TRANSFER)
141: #define NCR5380_read(reg) (*(DTC_address(reg)))
142: #define NCR5380_write(reg, value) (*(DTC_address(reg)) = (value))
143: #else
144: #define NCR5380_read(reg) (*(DTC_address(reg)))
145: #define xNCR5380_read(reg) \
146: (((unsigned char) printk("DTC : read register %d at address %08x\n"\
147: , (reg), DTC_address(reg))), *(DTC_address(reg)))
148:
149: #define NCR5380_write(reg, value) do { \
150: printk("DTC : write %02x to register %d at address %08x\n", \
151: (value), (reg), (int)DTC_address(reg)); \
152: *(DTC_address(reg)) = (value); } while(0)
153: #endif
154:
155: #define NCR5380_intr dtc_intr
156: #define NCR5380_queue_command dtc_queue_command
157: #define NCR5380_abort dtc_abort
158: #define NCR5380_reset dtc_reset
159: #define NCR5380_proc_info dtc_proc_info
160:
161: /* 15 12 11 10
162: 1001 1100 0000 0000 */
163:
164: #define DTC_IRQS 0x9c00
165:
166:
167: #endif /* else def HOSTS_C */
168: #endif /* ndef ASM */
169: #endif /* DTC3280_H */
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.