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1.1 root 1: #ifndef _GDTH_H
2: #define _GDTH_H
3:
4: /*
5: * Header file for the GDT ISA/EISA/PCI Disk Array Controller driver for Linux
6: *
7: * gdth.h Copyright (C) 1995-98 ICP vortex Computersysteme GmbH, Achim Leubner
8: * See gdth.c for further informations and
9: * below for supported controller types
10: *
11: * <[email protected]>
12: *
13: * $Id: gdth.h,v 1.1 1999/04/26 05:54:37 tb Exp $
14: */
15:
16: #include <linux/version.h>
17: #include <linux/types.h>
18:
19: #ifndef NULL
20: #define NULL 0
21: #endif
22: #ifndef TRUE
23: #define TRUE 1
24: #endif
25: #ifndef FALSE
26: #define FALSE 0
27: #endif
28:
29: /* defines, macros */
30:
31: /* driver version */
32: #define GDTH_VERSION_STR "1.07"
33: #define GDTH_VERSION 1
34: #define GDTH_SUBVERSION 7
35:
36: /* protocol version */
37: #define PROTOCOL_VERSION 1
38:
39: /* controller classes */
40: #define GDT_ISA 0x01 /* ISA controller */
41: #define GDT_EISA 0x02 /* EISA controller */
42: #define GDT_PCI 0x03 /* PCI controller */
43: #define GDT_PCINEW 0x04 /* new PCI controller */
44: #define GDT_PCIMPR 0x05 /* PCI MPR controller */
45: /* GDT_EISA, controller subtypes EISA */
46: #define GDT3_ID 0x0130941c /* GDT3000/3020 */
47: #define GDT3A_ID 0x0230941c /* GDT3000A/3020A/3050A */
48: #define GDT3B_ID 0x0330941c /* GDT3000B/3010A */
49: /* GDT_ISA */
50: #define GDT2_ID 0x0120941c /* GDT2000/2020 */
51: /* vendor ID, device IDs (PCI) */
52: /* these defines should already exist in <linux/pci.h> */
53: #ifndef PCI_VENDOR_ID_VORTEX
54: #define PCI_VENDOR_ID_VORTEX 0x1119 /* PCI controller vendor ID */
55: #endif
56: #ifndef PCI_DEVICE_ID_VORTEX_GDT60x0
57: /* GDT_PCI */
58: #define PCI_DEVICE_ID_VORTEX_GDT60x0 0 /* GDT6000/6020/6050 */
59: #define PCI_DEVICE_ID_VORTEX_GDT6000B 1 /* GDT6000B/6010 */
60: /* GDT_PCINEW */
61: #define PCI_DEVICE_ID_VORTEX_GDT6x10 2 /* GDT6110/6510 */
62: #define PCI_DEVICE_ID_VORTEX_GDT6x20 3 /* GDT6120/6520 */
63: #define PCI_DEVICE_ID_VORTEX_GDT6530 4 /* GDT6530 */
64: #define PCI_DEVICE_ID_VORTEX_GDT6550 5 /* GDT6550 */
65: /* GDT_PCINEW, wide/ultra SCSI controllers */
66: #define PCI_DEVICE_ID_VORTEX_GDT6x17 6 /* GDT6117/6517 */
67: #define PCI_DEVICE_ID_VORTEX_GDT6x27 7 /* GDT6127/6527 */
68: #define PCI_DEVICE_ID_VORTEX_GDT6537 8 /* GDT6537 */
69: #define PCI_DEVICE_ID_VORTEX_GDT6557 9 /* GDT6557/6557-ECC */
70: /* GDT_PCINEW, wide SCSI controllers */
71: #define PCI_DEVICE_ID_VORTEX_GDT6x15 10 /* GDT6115/6515 */
72: #define PCI_DEVICE_ID_VORTEX_GDT6x25 11 /* GDT6125/6525 */
73: #define PCI_DEVICE_ID_VORTEX_GDT6535 12 /* GDT6535 */
74: #define PCI_DEVICE_ID_VORTEX_GDT6555 13 /* GDT6555/6555-ECC */
75: #endif
76:
77: #ifndef PCI_DEVICE_ID_VORTEX_GDT6x17RP
78: /* GDT_MPR, RP series, wide/ultra SCSI */
79: #define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x100 /* GDT6117RP/GDT6517RP */
80: #define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x101 /* GDT6127RP/GDT6527RP */
81: #define PCI_DEVICE_ID_VORTEX_GDT6537RP 0x102 /* GDT6537RP */
82: #define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x103 /* GDT6557RP */
83: /* GDT_MPR, RP series, narrow/ultra SCSI */
84: #define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x104 /* GDT6111RP/GDT6511RP */
85: #define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x105 /* GDT6121RP/GDT6521RP */
86: /* GDT_MPR, RP1 series, wide/ultra SCSI */
87: #define PCI_DEVICE_ID_VORTEX_GDT6x17RP1 0x110 /* GDT6117RP1/GDT6517RP1 */
88: #define PCI_DEVICE_ID_VORTEX_GDT6x27RP1 0x111 /* GDT6127RP1/GDT6527RP1 */
89: #define PCI_DEVICE_ID_VORTEX_GDT6537RP1 0x112 /* GDT6537RP1 */
90: #define PCI_DEVICE_ID_VORTEX_GDT6557RP1 0x113 /* GDT6557RP1 */
91: /* GDT_MPR, RP1 series, narrow/ultra SCSI */
92: #define PCI_DEVICE_ID_VORTEX_GDT6x11RP1 0x114 /* GDT6111RP1/GDT6511RP1 */
93: #define PCI_DEVICE_ID_VORTEX_GDT6x21RP1 0x115 /* GDT6121RP1/GDT6521RP1 */
94: /* GDT_MPR, RP2 series, wide/ultra SCSI */
95: #define PCI_DEVICE_ID_VORTEX_GDT6x17RP2 0x120 /* GDT6117RP2/GDT6517RP2 */
96: #define PCI_DEVICE_ID_VORTEX_GDT6x27RP2 0x121 /* GDT6127RP2/GDT6527RP2 */
97: #define PCI_DEVICE_ID_VORTEX_GDT6537RP2 0x122 /* GDT6537RP2 */
98: #define PCI_DEVICE_ID_VORTEX_GDT6557RP2 0x123 /* GDT6557RP2 */
99: /* GDT_MPR, RP2 series, narrow/ultra SCSI */
100: #define PCI_DEVICE_ID_VORTEX_GDT6x11RP2 0x124 /* GDT6111RP2/GDT6511RP2 */
101: #define PCI_DEVICE_ID_VORTEX_GDT6x21RP2 0x125 /* GDT6121RP2/GDT6521RP2 */
102: #endif
103:
104: #ifndef PCI_DEVICE_ID_VORTEX_GDT6519RD
105: /* GDT_MPR, Fibre Channel */
106: #define PCI_DEVICE_ID_VORTEX_GDT6519RD 0x210 /* GDT6519RD */
107: #define PCI_DEVICE_ID_VORTEX_GDT6529RD 0x211 /* GDT6529RD */
108: #endif
109:
110: #ifndef PCI_DEVICE_ID_VORTEX_GDTMAXRP
111: /* GDT_MPR, last device ID */
112: #define PCI_DEVICE_ID_VORTEX_GDTMAXRP 0x2ff
113: #endif
114:
115: /* limits */
116: #define GDTH_SCRATCH 4096 /* 4KB scratch buffer */
117: #define GDTH_MAXCMDS 124
118: #define GDTH_MAXC_P_L 16 /* max. cmds per lun */
119: #define MAXOFFSETS 128
120: #define MAXHA 8
121: #define MAXID 16
122: #define MAXLUN 8
123: #define MAXBUS 6
124: #define MAX_HDRIVES 35 /* max. host drive count */
125: #define MAX_EVENTS 100 /* event buffer count */
126: #define MAXCYLS 1024
127: #define HEADS 64
128: #define SECS 32 /* mapping 64*32 */
129: #define MEDHEADS 127
130: #define MEDSECS 63 /* mapping 127*63 */
131: #define BIGHEADS 255
132: #define BIGSECS 63 /* mapping 255*63 */
133:
134: /* special command ptr. */
135: #define UNUSED_CMND ((Scsi_Cmnd *)-1)
136: #define INTERNAL_CMND ((Scsi_Cmnd *)-2)
137: #define SCREEN_CMND ((Scsi_Cmnd *)-3)
138: #define SPECIAL_SCP(p) (p==UNUSED_CMND || p==INTERNAL_CMND || p==SCREEN_CMND)
139:
140: /* device types */
141: #define EMPTY_DTYP 0
142: #define CACHE_DTYP 1
143: #define RAW_DTYP 2
144: #define SIOP_DTYP 3 /* the SCSI processor */
145:
146: /* controller services */
147: #define SCSIRAWSERVICE 3
148: #define CACHESERVICE 9
149: #define SCREENSERVICE 11
150:
151: /* screenservice defines */
152: #define MSG_INV_HANDLE -1 /* special message handle */
153: #define MSGLEN 16 /* size of message text */
154: #define MSG_SIZE 34 /* size of message structure */
155: #define MSG_REQUEST 0 /* async. event: message */
156:
157: /* cacheservice defines */
158: #define SECTOR_SIZE 0x200 /* always 512 bytes per sector */
159:
160: /* DPMEM constants */
161: #define DPMEM_MAGIC 0xC0FFEE11
162: #define IC_HEADER_BYTES 48
163: #define IC_QUEUE_BYTES 4
164: #define DPMEM_COMMAND_OFFSET IC_HEADER_BYTES+IC_QUEUE_BYTES*MAXOFFSETS
165:
166: /* service commands */
167: #define GDT_INIT 0 /* service initialization */
168: #define GDT_READ 1 /* read command */
169: #define GDT_WRITE 2 /* write command */
170: #define GDT_INFO 3 /* information about devices */
171: #define GDT_FLUSH 4 /* flush dirty cache buffers */
172: #define GDT_IOCTL 5 /* ioctl command */
173: #define GDT_DEVTYPE 9 /* additional information */
174: #define GDT_MOUNT 10 /* mount cache device */
175: #define GDT_UNMOUNT 11 /* unmount cache device */
176: #define GDT_SET_FEAT 12 /* set feat. (scatter/gather) */
177: #define GDT_GET_FEAT 13 /* get features */
178: #define GDT_RESERVE 14 /* reserve dev. to raw service */
179: #define GDT_WRITE_THR 16 /* write through */
180: #define GDT_EXT_INFO 18 /* extended info */
181: #define GDT_RESET 19 /* controller reset */
182:
183: /* IOCTL command defines */
184: #define SCSI_CHAN_CNT 5 /* subfunctions */
185: #define GET_IOCHAN_DESC 0x5e
186: #define L_CTRL_PATTERN 0x20000000L
187: #define CACHE_INFO 4
188: #define CACHE_CONFIG 5
189: #define BOARD_INFO 0x28
190: #define IO_CHANNEL 0x00020000L /* channels */
191: #define INVALID_CHANNEL 0x0000ffffL
192:
193: /* IOCTLs */
194: #define GDTIOCTL_MASK ('J'<<8)
195: #define GDTIOCTL_GENERAL (GDTIOCTL_MASK | 0) /* general IOCTL */
196: #define GDTIOCTL_DRVERS (GDTIOCTL_MASK | 1) /* get driver version */
197: #define GDTIOCTL_CTRTYPE (GDTIOCTL_MASK | 2) /* get controller type */
198: #define GDTIOCTL_CTRCNT (GDTIOCTL_MASK | 5) /* get controller count */
199: #define GDTIOCTL_LOCKDRV (GDTIOCTL_MASK | 6) /* lock host drive */
200: #define GDTIOCTL_LOCKCHN (GDTIOCTL_MASK | 7) /* lock channel */
201: #define GDTIOCTL_EVENT (GDTIOCTL_MASK | 8) /* read controller events */
202:
203: /* service errors */
204: #define S_OK 1 /* no error */
205: #define S_BSY 7 /* controller busy */
206: #define S_RAW_SCSI 12 /* raw serv.: target error */
207: #define S_RAW_ILL 0xff /* raw serv.: illegal */
208:
209: /* timeout values */
210: #define INIT_RETRIES 10000 /* 10000 * 1ms = 10s */
211: #define INIT_TIMEOUT 100000 /* 1000 * 1ms = 1s */
212: #define POLL_TIMEOUT 10000 /* 10000 * 1ms = 10s */
213:
214: /* priorities */
215: #define DEFAULT_PRI 0x20
216: #define IOCTL_PRI 0x10
217:
218: /* data directions */
219: #define DATA_IN 0x01000000L /* data from target */
220: #define DATA_OUT 0x00000000L /* data to target */
221:
222: /* BMIC registers (EISA controllers) */
223: #define ID0REG 0x0c80 /* board ID */
224: #define EINTENABREG 0x0c89 /* interrupt enable */
225: #define SEMA0REG 0x0c8a /* command semaphore */
226: #define SEMA1REG 0x0c8b /* status semaphore */
227: #define LDOORREG 0x0c8d /* local doorbell */
228: #define EDENABREG 0x0c8e /* EISA system doorbell enable */
229: #define EDOORREG 0x0c8f /* EISA system doorbell */
230: #define MAILBOXREG 0x0c90 /* mailbox reg. (16 bytes) */
231: #define EISAREG 0x0cc0 /* EISA configuration */
232:
233: /* other defines */
234: #define LINUX_OS 8 /* used for cache optim. */
235: #define SCATTER_GATHER 1 /* s/g feature */
236: #define GDTH_MAXSG 32 /* max. s/g elements */
237: #define SECS32 0x1f /* round capacity */
238: #define BIOS_ID_OFFS 0x10 /* offset contr. ID in ISABIOS */
239: #define LOCALBOARD 0 /* board node always 0 */
240: #define ASYNCINDEX 0 /* cmd index async. event */
241: #define SPEZINDEX 1 /* cmd index unknown service */
242: #define GDT_WR_THROUGH 0x100 /* WRITE_THROUGH supported */
243:
244: /* typedefs */
245:
246: #pragma pack(1)
247:
248: typedef struct {
249: char buffer[GDTH_SCRATCH]; /* scratch buffer */
250: } gdth_scratch_str;
251:
252: /* screenservice message */
253: typedef struct {
254: ulong msg_handle; /* message handle */
255: ulong msg_len; /* size of message */
256: ulong msg_alen; /* answer length */
257: unchar msg_answer; /* answer flag */
258: unchar msg_ext; /* more messages */
259: unchar msg_reserved[2];
260: char msg_text[MSGLEN+2]; /* the message text */
261: } gdth_msg_str;
262:
263: /* get channel count IOCTL */
264: typedef struct {
265: ulong channel_no; /* number of channel */
266: ulong drive_cnt; /* number of drives */
267: unchar siop_id; /* SCSI processor ID */
268: unchar siop_state; /* SCSI processor state */
269: } gdth_getch_str;
270:
271: /* get raw channel count IOCTL (NEW!) */
272: typedef struct {
273: ulong version; /* version of information (-1UL: newest) */
274: unchar list_entries; /* list entry count */
275: unchar first_chan; /* first channel number */
276: unchar last_chan; /* last channel number */
277: unchar chan_count; /* (R) channel count */
278: ulong list_offset; /* offset of list[0] */
279: struct {
280: unchar proc_id; /* processor id */
281: unchar proc_defect; /* defect ? */
282: unchar reserved[2];
283: } list[MAXBUS];
284: } gdth_iochan_str;
285:
286: /* cache info/config IOCTL */
287: typedef struct {
288: ulong version; /* firmware version */
289: ushort state; /* cache state (on/off) */
290: ushort strategy; /* cache strategy */
291: ushort write_back; /* write back state (on/off) */
292: ushort block_size; /* cache block size */
293: } gdth_cpar_str;
294:
295: typedef struct {
296: ulong csize; /* cache size */
297: ulong read_cnt; /* read/write counter */
298: ulong write_cnt;
299: ulong tr_hits; /* hits */
300: ulong sec_hits;
301: ulong sec_miss; /* misses */
302: } gdth_cstat_str;
303:
304: typedef struct {
305: gdth_cpar_str cpar;
306: gdth_cstat_str cstat;
307: } gdth_cinfo_str;
308:
309: /* board info IOCTL */
310: typedef struct {
311: ulong ser_no; /* serial no. */
312: unchar oem_id[2]; /* OEM ID */
313: ushort ep_flags; /* eprom flags */
314: ulong proc_id; /* processor ID */
315: ulong memsize; /* memory size (bytes) */
316: unchar mem_banks; /* memory banks */
317: unchar chan_type; /* channel type */
318: unchar chan_count; /* channel count */
319: unchar rdongle_pres; /* dongle present? */
320: ulong epr_fw_ver; /* (eprom) firmware version */
321: ulong upd_fw_ver; /* (update) firmware version */
322: ulong upd_revision; /* update revision */
323: char type_string[16]; /* controller name */
324: char raid_string[16]; /* RAID firmware name */
325: unchar update_pres; /* update present? */
326: unchar xor_pres; /* XOR engine present? */
327: unchar prom_type; /* ROM type (eprom/flash eprom) */
328: unchar prom_count; /* number of ROM devices */
329: ulong dup_pres; /* duplexing module present? */
330: ulong chan_pres; /* number of expansion channels */
331: ulong mem_pres; /* memory expansion installed? */
332: unchar ft_bus_system; /* fault bus supported? */
333: unchar subtype_valid; /* board_subtype valid? */
334: unchar board_subtype; /* controller subtype/hardware level */
335: unchar ramparity_pres; /* RAM parity check hardware present? */
336: } gdth_binfo_str;
337:
338: /* scatter/gather element */
339: typedef struct {
340: ulong sg_ptr; /* address */
341: ulong sg_len; /* length */
342: } gdth_sg_str;
343:
344: /* command structure */
345: typedef struct {
346: ulong BoardNode; /* board node (always 0) */
347: ulong CommandIndex; /* command number */
348: ushort OpCode; /* the command (READ,..) */
349: union {
350: struct {
351: ushort DeviceNo; /* number of cache drive */
352: ulong BlockNo; /* block number */
353: ulong BlockCnt; /* block count */
354: ulong DestAddr; /* dest. addr. (if s/g: -1) */
355: ulong sg_canz; /* s/g element count */
356: gdth_sg_str sg_lst[GDTH_MAXSG]; /* s/g list */
357: } cache; /* cache service cmd. str. */
358: struct {
359: ushort param_size; /* size of p_param buffer */
360: ulong subfunc; /* IOCTL function */
361: ulong channel; /* device */
362: ulong p_param; /* buffer */
363: } ioctl; /* IOCTL command structure */
364: struct {
365: ushort reserved;
366: ulong msg_handle; /* message handle */
367: ulong msg_addr; /* message buffer address */
368: } screen; /* screen service cmd. str. */
369: struct {
370: ushort reserved;
371: ulong direction; /* data direction */
372: ulong mdisc_time; /* disc. time (0: no timeout)*/
373: ulong mcon_time; /* connect time(0: no to.) */
374: ulong sdata; /* dest. addr. (if s/g: -1) */
375: ulong sdlen; /* data length (bytes) */
376: ulong clen; /* SCSI cmd. length(6,10,12) */
377: unchar cmd[12]; /* SCSI command */
378: unchar target; /* target ID */
379: unchar lun; /* LUN */
380: unchar bus; /* SCSI bus number */
381: unchar priority; /* only 0 used */
382: ulong sense_len; /* sense data length */
383: ulong sense_data; /* sense data addr. */
384: struct raw *link_p; /* linked cmds (not supp.) */
385: ulong sg_ranz; /* s/g element count */
386: gdth_sg_str sg_lst[GDTH_MAXSG]; /* s/g list */
387: } raw; /* raw service cmd. struct. */
388: } u;
389: /* additional variables */
390: unchar Service; /* controller service */
391: ushort Status; /* command result */
392: ulong Info; /* additional information */
393: Scsi_Cmnd *RequestBuffer; /* request buffer */
394: } gdth_cmd_str;
395:
396: /* controller event structure */
397: #define ES_ASYNC 1
398: #define ES_DRIVER 2
399: #define ES_TEST 3
400: #define ES_SYNC 4
401: typedef struct {
402: ushort size; /* size of structure */
403: union {
404: char stream[16];
405: struct {
406: ushort ionode;
407: ushort service;
408: ulong index;
409: } driver;
410: struct {
411: ushort ionode;
412: ushort service;
413: ushort status;
414: ulong info;
415: unchar scsi_coord[3];
416: } async;
417: struct {
418: ushort ionode;
419: ushort service;
420: ushort status;
421: ulong info;
422: ushort hostdrive;
423: unchar scsi_coord[3];
424: unchar sense_key;
425: } sync;
426: struct {
427: ulong l1, l2, l3, l4;
428: } test;
429: } eu;
430: } gdth_evt_data;
431:
432: typedef struct {
433: ulong first_stamp;
434: ulong last_stamp;
435: ushort same_count;
436: ushort event_source;
437: ushort event_idx;
438: unchar application;
439: unchar reserved;
440: gdth_evt_data event_data;
441: } gdth_evt_str;
442:
443:
444: /* DPRAM structures */
445:
446: /* interface area ISA/PCI */
447: typedef struct {
448: unchar S_Cmd_Indx; /* special command */
449: unchar volatile S_Status; /* status special command */
450: ushort reserved1;
451: ulong S_Info[4]; /* add. info special command */
452: unchar volatile Sema0; /* command semaphore */
453: unchar reserved2[3];
454: unchar Cmd_Index; /* command number */
455: unchar reserved3[3];
456: ushort volatile Status; /* command status */
457: ushort Service; /* service(for async.events) */
458: ulong Info[2]; /* additional info */
459: struct {
460: ushort offset; /* command offs. in the DPRAM*/
461: ushort serv_id; /* service */
462: } comm_queue[MAXOFFSETS]; /* command queue */
463: ulong bios_reserved[2];
464: unchar gdt_dpr_cmd[1]; /* commands */
465: } gdt_dpr_if;
466:
467: /* SRAM structure PCI controllers */
468: typedef struct {
469: ulong magic; /* controller ID from BIOS */
470: ushort need_deinit; /* switch betw. BIOS/driver */
471: unchar switch_support; /* see need_deinit */
472: unchar padding[9];
473: unchar os_used[16]; /* OS code per service */
474: unchar unused[28];
475: unchar fw_magic; /* contr. ID from firmware */
476: } gdt_pci_sram;
477:
478: /* SRAM structure EISA controllers (but NOT GDT3000/3020) */
479: typedef struct {
480: unchar os_used[16]; /* OS code per service */
481: ushort need_deinit; /* switch betw. BIOS/driver */
482: unchar switch_support; /* see need_deinit */
483: unchar padding;
484: } gdt_eisa_sram;
485:
486:
487: /* DPRAM ISA controllers */
488: typedef struct {
489: union {
490: struct {
491: unchar bios_used[0x3c00-32]; /* 15KB - 32Bytes BIOS */
492: ulong magic; /* controller (EISA) ID */
493: ushort need_deinit; /* switch betw. BIOS/driver */
494: unchar switch_support; /* see need_deinit */
495: unchar padding[9];
496: unchar os_used[16]; /* OS code per service */
497: } dp_sram;
498: unchar bios_area[0x4000]; /* 16KB reserved for BIOS */
499: } bu;
500: union {
501: gdt_dpr_if ic; /* interface area */
502: unchar if_area[0x3000]; /* 12KB for interface */
503: } u;
504: struct {
505: unchar memlock; /* write protection DPRAM */
506: unchar event; /* release event */
507: unchar irqen; /* board interrupts enable */
508: unchar irqdel; /* acknowledge board int. */
509: unchar volatile Sema1; /* status semaphore */
510: unchar rq; /* IRQ/DRQ configuration */
511: } io;
512: } gdt2_dpram_str;
513:
514: /* DPRAM PCI controllers */
515: typedef struct {
516: union {
517: gdt_dpr_if ic; /* interface area */
518: unchar if_area[0xff0-sizeof(gdt_pci_sram)];
519: } u;
520: gdt_pci_sram gdt6sr; /* SRAM structure */
521: struct {
522: unchar unused0[1];
523: unchar volatile Sema1; /* command semaphore */
524: unchar unused1[3];
525: unchar irqen; /* board interrupts enable */
526: unchar unused2[2];
527: unchar event; /* release event */
528: unchar unused3[3];
529: unchar irqdel; /* acknowledge board int. */
530: unchar unused4[3];
531: } io;
532: } gdt6_dpram_str;
533:
534: /* PLX register structure (new PCI controllers) */
535: typedef struct {
536: unchar cfg_reg; /* DPRAM cfg.(2:below 1MB,0:anywhere)*/
537: unchar unused1[0x3f];
538: unchar volatile sema0_reg; /* command semaphore */
539: unchar volatile sema1_reg; /* status semaphore */
540: unchar unused2[2];
541: ushort volatile status; /* command status */
542: ushort service; /* service */
543: ulong info[2]; /* additional info */
544: unchar unused3[0x10];
545: unchar ldoor_reg; /* PCI to local doorbell */
546: unchar unused4[3];
547: unchar volatile edoor_reg; /* local to PCI doorbell */
548: unchar unused5[3];
549: unchar control0; /* control0 register(unused) */
550: unchar control1; /* board interrupts enable */
551: unchar unused6[0x16];
552: } gdt6c_plx_regs;
553:
554: /* DPRAM new PCI controllers */
555: typedef struct {
556: union {
557: gdt_dpr_if ic; /* interface area */
558: unchar if_area[0x4000-sizeof(gdt_pci_sram)];
559: } u;
560: gdt_pci_sram gdt6sr; /* SRAM structure */
561: } gdt6c_dpram_str;
562:
563: /* i960 register structure (PCI MPR controllers) */
564: typedef struct {
565: unchar unused1[16];
566: unchar volatile sema0_reg; /* command semaphore */
567: unchar unused2;
568: unchar volatile sema1_reg; /* status semaphore */
569: unchar unused3;
570: ushort volatile status; /* command status */
571: ushort service; /* service */
572: ulong info[2]; /* additional info */
573: unchar ldoor_reg; /* PCI to local doorbell */
574: unchar unused4[11];
575: unchar volatile edoor_reg; /* local to PCI doorbell */
576: unchar unused5[7];
577: unchar edoor_en_reg; /* board interrupts enable */
578: unchar unused6[27];
579: ulong unused7[1004]; /* size: 4 KB */
580: } gdt6m_i960_regs;
581:
582: /* DPRAM PCI MPR controllers */
583: typedef struct {
584: gdt6m_i960_regs i960r; /* 4KB i960 registers */
585: union {
586: gdt_dpr_if ic; /* interface area */
587: unchar if_area[0x3000-sizeof(gdt_pci_sram)];
588: } u;
589: gdt_pci_sram gdt6sr; /* SRAM structure */
590: } gdt6m_dpram_str;
591:
592:
593: /* PCI resources */
594: typedef struct {
595: ushort device_id; /* device ID (0,..,9) */
596: unchar bus; /* PCI bus */
597: unchar device_fn; /* PCI device/function no. */
598: ulong dpmem; /* DPRAM address */
599: ulong io; /* IO address */
600: ulong io_mm; /* IO address mem. mapped */
601: ulong bios; /* BIOS address */
602: unchar irq; /* IRQ */
603: } gdth_pci_str;
604:
605:
606: /* controller information structure */
607: typedef struct {
608: unchar bus_cnt; /* SCSI bus count */
609: unchar type; /* controller class */
610: ushort raw_feat; /* feat. raw service (s/g,..) */
611: ulong stype; /* controller subtype */
612: ushort cache_feat; /* feat. cache serv. (s/g,..) */
613: ushort bmic; /* BMIC address (EISA) */
614: void *brd; /* DPRAM address */
615: ulong brd_phys; /* slot number/BIOS address */
616: gdt6c_plx_regs *plx; /* PLX regs (new PCI contr.) */
617: gdth_cmd_str *pccb; /* address command structure */
618: gdth_scratch_str *pscratch;
619: unchar irq; /* IRQ */
620: unchar drq; /* DRQ (ISA controllers) */
621: ushort status; /* command status */
622: ulong info;
623: ulong info2; /* additional info */
624: Scsi_Cmnd *req_first; /* top of request queue */
625: struct {
626: unchar type; /* device type */
627: unchar heads; /* mapping */
628: unchar secs;
629: unchar lock; /* drive locked ? (hot plug) */
630: ushort hostdrive; /* host drive number */
631: ushort devtype; /* further information */
632: ulong size; /* capacity */
633: } id[MAXBUS][MAXID];
634: ushort cmd_cnt; /* command count in DPRAM */
635: ushort cmd_len; /* length of actual command */
636: ushort cmd_offs_dpmem; /* actual offset in DPRAM */
637: ushort ic_all_size; /* sizeof DPRAM interf. area */
638: unchar reserved;
639: unchar mode; /* information from /proc */
640: ushort param_size;
641: gdth_cpar_str cpar; /* controller cache par. */
642: char ctr_name[16]; /* controller name */
643: } gdth_ha_str;
644:
645: /* structure for scsi_register(), SCSI bus != 0 */
646: typedef struct {
647: ushort hanum;
648: ushort busnum;
649: } gdth_num_str;
650:
651: /* structure for scsi_register() */
652: typedef struct {
653: gdth_num_str numext; /* must be the first element */
654: gdth_ha_str haext;
655: gdth_cmd_str cmdext;
656: gdth_scratch_str dmaext;
657: } gdth_ext_str;
658:
659:
660: /* INQUIRY data format */
661: typedef struct {
662: unchar type_qual;
663: unchar modif_rmb;
664: unchar version;
665: unchar resp_aenc;
666: unchar add_length;
667: unchar reserved1;
668: unchar reserved2;
669: unchar misc;
670: unchar vendor[8];
671: unchar product[16];
672: unchar revision[4];
673: } gdth_inq_data;
674:
675: /* READ_CAPACITY data format */
676: typedef struct {
677: ulong last_block_no;
678: ulong block_length;
679: } gdth_rdcap_data;
680:
681: /* REQUEST_SENSE data format */
682: typedef struct {
683: unchar errorcode;
684: unchar segno;
685: unchar key;
686: ulong info;
687: unchar add_length;
688: ulong cmd_info;
689: unchar adsc;
690: unchar adsq;
691: unchar fruc;
692: unchar key_spec[3];
693: } gdth_sense_data;
694:
695: /* MODE_SENSE data format */
696: typedef struct {
697: struct {
698: unchar data_length;
699: unchar med_type;
700: unchar dev_par;
701: unchar bd_length;
702: } hd;
703: struct {
704: unchar dens_code;
705: unchar block_count[3];
706: unchar reserved;
707: unchar block_length[3];
708: } bd;
709: } gdth_modep_data;
710:
711: /* stack frame */
712: typedef struct {
713: ulong b[10]; /* 32 bit compiler ! */
714: } gdth_stackframe;
715:
716: #pragma pack()
717:
718:
719: /* data structure for reserve drives */
720: typedef struct {
721: unchar hanum;
722: unchar bus;
723: unchar id;
724: } gdth_reserve_str;
725:
726:
727: /* function prototyping */
728:
729: int gdth_detect(Scsi_Host_Template *);
730: int gdth_release(struct Scsi_Host *);
731: int gdth_command(Scsi_Cmnd *);
732: int gdth_queuecommand(Scsi_Cmnd *,void (*done)(Scsi_Cmnd *));
733: int gdth_abort(Scsi_Cmnd *);
734: #if LINUX_VERSION_CODE >= 0x010346
735: int gdth_reset(Scsi_Cmnd *, unsigned int reset_flags);
736: #else
737: int gdth_reset(Scsi_Cmnd *);
738: #endif
739: const char *gdth_info(struct Scsi_Host *);
740:
741: #if LINUX_VERSION_CODE >= 0x02015F
742: int gdth_bios_param(Disk *,kdev_t,int *);
743: extern struct proc_dir_entry proc_scsi_gdth;
744: int gdth_proc_info(char *,char **,off_t,int,int,int);
745: int gdth_eh_abort(Scsi_Cmnd *scp);
746: int gdth_eh_device_reset(Scsi_Cmnd *scp);
747: int gdth_eh_bus_reset(Scsi_Cmnd *scp);
748: int gdth_eh_host_reset(Scsi_Cmnd *scp);
749: #define GDTH { proc_dir: &proc_scsi_gdth, \
750: proc_info: gdth_proc_info, \
751: name: "GDT SCSI Disk Array Controller",\
752: detect: gdth_detect, \
753: release: gdth_release, \
754: info: gdth_info, \
755: command: gdth_command, \
756: queuecommand: gdth_queuecommand, \
757: eh_abort_handler: gdth_eh_abort, \
758: eh_device_reset_handler: gdth_eh_device_reset, \
759: eh_bus_reset_handler: gdth_eh_bus_reset, \
760: eh_host_reset_handler: gdth_eh_host_reset, \
761: abort: gdth_abort, \
762: reset: gdth_reset, \
763: bios_param: gdth_bios_param, \
764: can_queue: GDTH_MAXCMDS, \
765: this_id: -1, \
766: sg_tablesize: GDTH_MAXSG, \
767: cmd_per_lun: GDTH_MAXC_P_L, \
768: present: 0, \
769: unchecked_isa_dma: 1, \
770: use_clustering: ENABLE_CLUSTERING, \
771: use_new_eh_code: 1 /* use new error code */ }
772: #elif LINUX_VERSION_CODE >= 0x010300
773: int gdth_bios_param(Disk *,kdev_t,int *);
774: extern struct proc_dir_entry proc_scsi_gdth;
775: int gdth_proc_info(char *,char **,off_t,int,int,int);
776: #define GDTH { NULL, NULL, \
777: &proc_scsi_gdth, \
778: gdth_proc_info, \
779: "GDT SCSI Disk Array Controller", \
780: gdth_detect, \
781: gdth_release, \
782: gdth_info, \
783: gdth_command, \
784: gdth_queuecommand, \
785: gdth_abort, \
786: gdth_reset, \
787: NULL, \
788: gdth_bios_param, \
789: GDTH_MAXCMDS, \
790: -1, \
791: GDTH_MAXSG, \
792: GDTH_MAXC_P_L, \
793: 0, \
794: 1, \
795: ENABLE_CLUSTERING}
796: #else
797: int gdth_bios_param(Disk *,int,int *);
798: #define GDTH { NULL, NULL, \
799: "GDT SCSI Disk Array Controller", \
800: gdth_detect, \
801: gdth_release, \
802: gdth_info, \
803: gdth_command, \
804: gdth_queuecommand, \
805: gdth_abort, \
806: gdth_reset, \
807: NULL, \
808: gdth_bios_param, \
809: GDTH_MAXCMDS, \
810: -1, \
811: GDTH_MAXSG, \
812: GDTH_MAXC_P_L, \
813: 0, \
814: 1, \
815: ENABLE_CLUSTERING}
816: #endif
817:
818: #endif
819:
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