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1.1 root 1: /***********************************************************************
2: ;* File Name : SCRIPTS.H *
3: ;* Description:SCRIPT language for NCR53c825A,875 SCRIPT processor*
4: ;* *
5: ;***********************************************************************
6:
7: ;==========================================================
8: ; NCR 53C810,53C815,53C820,53C825,53C825A,53C860,53C875
9: ; Script language definition for assembly programming
10: ;==========================================================
11:
12: ;==========================================================
13: ; DMA Command
14: ;==========================================================
15: */
16: #define DCMD_BLOCK_MOVE 0
17: #define DCMD_IO 0x040000000 /*;BIT30 */
18: #define DCMD_RD_WRT 0x040000000 /*;BIT30 */
19: #define DCMD_XFER_CTRL 0x080000000 /*;BIT31 */
20: #define DCMD_MEM_MOVE 0x0C0000000 /*;(BIT31+BIT30) */
21: #define DCMD_LOAD_STORE 0x0E0000000 /*;(BIT31+BIT30+BIT29) */
22: /*;==========================================================*/
23: #define INDIRECT_ADDR 0x20000000 /*;BIT29 */
24: #define TABLE_INDIRECT 0x10000000 /*;BIT28 */
25: #define BLOCK_MOVE 0x08000000 /*;BIT27 */
26: #define CHAIN_MOVE 0
27: /*; SCSI phase definition */
28: #define DATA_OUT_ 0x00000000 /*;data out phase */
29: #define DATA_IN_ 0x01000000 /*;BIT24 ; data in phase */
30: #define COMMAND_ 0x02000000 /*;BIT25 ; command phase */
31: #define STATUS_ 0x03000000 /*;(BIT25+BIT24) ; status phase */
32: #define RESERVED_OUT 0x04000000 /*;BIT26 */
33: #define RESERVED_IN 0x05000000 /*;(BIT26+BIT24) */
34: #define MSG_OUT_ 0x06000000 /*;(BIT26+BIT25) ; message in phase */
35: #define MSG_IN_ 0x07000000 /*;(BIT26+BIT25+BIT24);message out phase */
36: /*;----------------------------------------------------------*/
37: #define DCMD_SELECT 0x40000000 /*;DCMD_IO+0 */
38: #define DCMD_SELECT_ATN 0x41000000 /*;(DCMD_IO+BIT24) */
39: #define DCMD_WAIT_DISC 0x48000000 /*;(DCMD_IO+BIT27) */
40: #define DCMD_WAIT_RESEL 0x50000000 /*;(DCMD_IO+BIT28) */
41: #define DCMD_SET_CARRY 0x58000400 /*;(DCMD_IO+BIT28+BIT27+BIT10) */
42: #define DCMD_SET_ACK 0x58000040 /*;(DCMD_IO+BIT28+BIT27+BIT6) */
43: #define DCMD_SET_ATN 0x58000008 /*;(DCMD_IO+BIT28+BIT27+BIT3) */
44: #define DCMD_CLR_CARRY 0x60000400 /*;(DCMD_IO+BIT29+BIT10) */
45: #define DCMD_CLR_ACK 0x60000040 /*;(DCMD_IO+BIT29+BIT6) */
46: #define DCMD_CLR_ATN 0x60000008 /*;(DCMD_IO+BIT29+BIT3) */
47: #define RELATIVE_ADDR 0x04000000 /*;BIT26 */
48: #define IO_TABLE_INDIR 0x02000000 /*;BIT25 */
49: /*;----------------------------------------------------------*/
50: #define MOVE_FROM_SFBR 0x68000000 /*;(DCMD_RD_WRT+BIT29+BIT27) */
51: #define MOVE_TO_SFBR 0x70000000 /*;(DCMD_RD_WRT+BIT29+BIT28) */
52: #define RD_MODIFY_WRT 0x78000000 /*;(DCMD_RD_WRT+BIT29+BIT28+BIT27) */
53: #define OP_MOVE_DATA 0
54: #define OP_SHIFT_LEFT_C 0x01000000 /*;BIT24 */
55: #define OP_OR 0x02000000 /*;BIT25 */
56: #define OP_XOR 0x03000000 /*;(BIT25+BIT24) */
57: #define OP_AND 0x04000000 /*;BIT26 */
58: #define OP_SHIFT_RIGHT_C 0x05000000 /*;(BIT26+BIT24) */
59: #define OP_ADD_DATA 0x06000000 /*;(BIT26+BIT25) */
60: #define OP_ADD_DATA_C 0x07000000 /*;(BIT26+BIT25+BIT24) */
61: #define USE_SFBR 0x00800000 /*;BIT23 */
62: /*;----------------------------------------------------------*/
63: #define DCMD_JUMP 0x80000000 /*;DCMD_XFER_CTRL+0 */
64: #define DCMD_CALL 0x88000000 /*;(DCMD_XFER_CTRL+BIT27) */
65: #define DCMD_RETURN 0x90000000 /*;(DCMD_XFER_CTRL+BIT28) */
66: #define DCMD_INT 0x98000000 /*;(DCMD_XFER_CTRL+BIT28+BIT27) */
67: #define RELATIVE_ 0x00800000 /*;BIT23 */
68: #define IF_CARRY 0x00200000 /*;BIT21 */
69: #define INT_ON_FLY_ 0x00100000 /*;BIT20 */
70: #define IF_TRUE 0x00080000 /*;BIT19 */
71: #define IF_NOT 0
72: #define DATA_CMP 0x00040000 /*;BIT18 */
73: #define PHASE_CMP 0x00020000 /*;BIT17 */
74: #define WAIT_PHASE_VALID 0x00010000 /*;BIT16 */
75: /*;----------------------------------------------------------*/
76: #define DSA_RELATIVE 0x10000000 /*;BIT28 */
77: #define FLUSH_PREFETCH 0x02000000 /*;BIT25 */
78: #define DCMD_LOAD 0x0E1000000 /*;(DCMD_LOAD_STORE+BIT24) */
79: #define DCMD_STORE 0x0E0000000 /*;DCMD_LOAD_STORE */
80: /*
81: ;==========================================================
82: ; SCSI message EQUATES
83: ;==========================================================
84: */
85: #define CMD_COMPLETE 0
86: #define EXT_MSG 1
87: #define SAVE_PTR 2
88: #define RESTORE_PTR 3
89: #define DISCONNECTMSG 4
90: #define INITIATOR_ERR 5
91: #define ABORTMSG 6
92: #define MSG_REJECT 7
93: #define NOPMSG 8
94: #define MSG_PARITY 9
95: #define LINK_CMD_CPL 0x0a
96: #define LINK_CMD_FLAG 0x0b
97: #define RESET_DEVICE 0x0c
98: #define IDENTIFYMSG 0x80
99: #define SIMPLE_TAG 0x20
100: #define IGNORE_WIDE_RES 0x23
101: /*
102: ;==========================================================
103: ; Operation assumption
104: ; 1. If phase mismatch during Xfer PAD ==> do nothing
105: ; Else compute FIXUP needed
106: ; 2. After phase mismatch ==> Set to Xfer PAD
107: ; 3. At disconnection ==> Modify return address
108: ; 4. 1st restore ptr after reselection is ignored
109: ; 5. If Xfer PAD is done ==> Error
110: ;==========================================================
111: */
112: /* static start_script
113: static reselected
114: static reselecttag
115: static select0
116: static select1
117: static check_phase
118: static status1_phase
119: static command_phase
120: static jump_table0
121: static jump_tableB
122: static din_phase
123: static din_phaseB
124: static din_pad_0
125: static din_pad_addrB
126: static dout_phase
127: static dout_phaseB
128: static dout_pad_0
129: static dout_pad_addrB
130: static jump_tablew
131: static jump_tableW
132: static din_phase1
133: static din_phaseW
134: static din_pad_1
135: static din_pad_addrW
136: static dout_phase1
137: static dout_phaseW
138: static dout_pad_1
139: static dout_pad_addrW
140: static mout_phase
141: static status_phase
142: static min_phase
143: static set_atn
144: static clr_atn
145: static end_script
146: static start_mov
147: static SrcPhysAddr
148: static DesPhysAddr
149: */
150: ULONG start_script[]={
151: /*
152: ;==========================================================
153: ; Wait for reselection
154: ;==========================================================
155: */
156: DCMD_WAIT_RESEL
157: };
158: ULONG jmp_select0[]={
159: 0 /* offset select0 */
160: };
161: ULONG reselected[]={
162: RD_MODIFY_WRT+OP_OR+0x200+0x340000, /* (2 shl 8) or (__scratcha shl 16) */
163: 0,
164:
165: DCMD_INT+WAIT_PHASE_VALID+IF_NOT+PHASE_CMP+MSG_IN_,
166: __RESELECTED,
167:
168: BLOCK_MOVE+MSG_IN_+1 /* ;move in ID byte */
169: };
170: ULONG ACB_msgin123_1[]={
171: 0, /* offset ACB.msgin123,*/
172:
173: DCMD_INT+IF_TRUE,
174: __RESELECTED1
175: };
176: ULONG reselecttag[]={
177: DCMD_CLR_ACK,
178: 0,
179:
180: BLOCK_MOVE+MSG_IN_+2 /* ;move 2 msg bytes */
181: };
182: ULONG ACB_msgin123_2[]={
183: 0, /* offset ACB.msgin123,*/
184:
185: DCMD_INT+IF_TRUE,
186: __RESELECTEDT
187: };
188: /*
189: ;==========================================================
190: ; Select
191: ; Case 1 : Only identify message is to be sent
192: ; Case 2 : Synchronous negotiation is requested
193: ;==========================================================
194: */
195: ULONG select0[]={
196: DCMD_INT+IF_TRUE,
197: __SIGNAL
198: };
199: ULONG select1[]={ /* ; Select with ATN */
200:
201: DCMD_SELECT_ATN+IO_TABLE_INDIR /* +offset SRB.__select ;4200h or 0100H */
202: };
203: ULONG jmp_reselected[]={
204: 0, /* offset reselected, */
205:
206: DCMD_JUMP+WAIT_PHASE_VALID+IF_NOT+PHASE_CMP+MSG_OUT_
207: };
208: ULONG jmp_check_phase[]={
209: 0, /* offset check_phase, */
210:
211: TABLE_INDIRECT+BLOCK_MOVE+MSG_OUT_
212: };
213: ULONG SRB_msgout0[]={
214: 0 /* offset SRB.__msgout0 */
215: };
216: ULONG check_phase[]={
217: DCMD_RETURN+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
218: 0,
219:
220: DCMD_RETURN+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
221: 0
222: };
223: ULONG status1_phase[]={
224: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+STATUS_
225: };
226: ULONG jmp_status_phase[]={
227: 0, /* offset status_phase,*/
228:
229: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+COMMAND_
230: };
231: ULONG jmp_command_phase[]={
232: 0, /* offset command_phase, */
233:
234: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+MSG_IN_
235: };
236: ULONG jmp_min_phase[]={
237: 0, /* offset min_phase,*/
238:
239: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+MSG_OUT_
240: };
241: ULONG jmp_mout_phase[]={
242: 0, /* offset mout_phase,*/
243:
244: DCMD_INT+IF_TRUE,
245: __FATALERROR
246: };
247: /*
248: ;==========================================================
249: ; Command phase
250: ;==========================================================
251: */
252: ULONG command_phase[]={
253: DCMD_CLR_ATN,
254: 0,
255: TABLE_INDIRECT+BLOCK_MOVE+COMMAND_
256: };
257: ULONG SRB_command[]={
258: 0, /* offset SRB.__command,*/
259:
260: DCMD_JUMP+IF_TRUE
261: };
262: ULONG jmp_check_phase1[]={
263: 0 /* offset check_phase */
264: };
265: /*
266: ;==========================================================
267: ; Data phase jump table for 8 bit operation
268: ;==========================================================
269: */
270: ULONG jmp_dio_phaseB[]={
271: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
272: 0, /* offset din_phaseB+ 0,*/
273:
274: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
275: 0, /* offset dout_phaseB+ 0,*/
276:
277: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
278: 0, /* offset din_phaseB+ 8,*/
279:
280: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
281: 0, /* offset dout_phaseB+ 8,*/
282:
283: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
284: 0, /* offset din_phaseB+ 16,*/
285:
286: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
287: 0, /* offset dout_phaseB+ 16,*/
288:
289: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
290: 0, /* offset din_phaseB+ 24,*/
291:
292: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
293: 0, /* offset dout_phaseB+ 24,*/
294:
295: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
296: 0, /* offset din_phaseB+ 32,*/
297:
298: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
299: 0, /* offset dout_phaseB+ 32,*/
300:
301: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
302: 0, /* offset din_phaseB+ 40,*/
303:
304: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
305: 0, /* offset dout_phaseB+ 40,*/
306:
307: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
308: 0, /* offset din_phaseB+ 48,*/
309:
310: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
311: 0, /* offset dout_phaseB+ 48,*/
312:
313: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
314: 0, /* offset din_phaseB+ 56,*/
315:
316: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
317: 0, /* offset dout_phaseB+ 56,*/
318:
319: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
320: 0, /* offset din_phaseB+ 64,*/
321:
322: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
323: 0, /* offset dout_phaseB+ 64,*/
324:
325: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
326: 0, /* offset din_phaseB+ 72,*/
327:
328: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
329: 0, /* offset dout_phaseB+ 72,*/
330:
331: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
332: 0, /* offset din_phaseB+ 80,*/
333:
334: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
335: 0, /* offset dout_phaseB+ 80,*/
336:
337: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
338: 0, /* offset din_phaseB+ 88,*/
339:
340: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
341: 0, /* offset dout_phaseB+ 88,*/
342:
343: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
344: 0, /* offset din_phaseB+ 96,*/
345:
346: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
347: 0, /* offset dout_phaseB+ 96,*/
348:
349: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
350: 0, /* offset din_phaseB+ 104,*/
351:
352: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
353: 0, /* offset dout_phaseB+ 104,*/
354:
355: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
356: 0, /* offset din_phaseB+ 112,*/
357:
358: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
359: 0, /* offset dout_phaseB+ 112,*/
360:
361: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
362: 0, /* offset din_phaseB+ 120,*/
363:
364: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
365: 0, /* offset dout_phaseB+ 120,*/
366:
367: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
368: 0, /* offset din_phaseB+ 0,*/
369:
370: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
371: 0, /* offset dout_phaseB+ 0,*/
372:
373: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
374: 0, /* offset din_phaseB+ 8,*/
375:
376: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
377: 0, /* offset dout_phaseB+ 8,*/
378:
379: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
380: 0, /* offset din_phaseB+ 16,*/
381:
382: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
383: 0, /* offset dout_phaseB+ 16,*/
384:
385: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
386: 0, /* offset din_phaseB+ 24,*/
387:
388: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
389: 0, /* offset dout_phaseB+ 24,*/
390:
391: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
392: 0, /* offset din_phaseB+ 32,*/
393:
394: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
395: 0, /* offset dout_phaseB+ 32,*/
396:
397: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
398: 0, /* offset din_phaseB+ 40,*/
399:
400: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
401: 0, /* offset dout_phaseB+ 40,*/
402:
403: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
404: 0, /* offset din_phaseB+ 48,*/
405:
406: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
407: 0, /* offset dout_phaseB+ 48,*/
408:
409: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
410: 0, /* offset din_phaseB+ 56,*/
411:
412: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
413: 0, /* offset dout_phaseB+ 56,*/
414:
415: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
416: 0, /* offset din_phaseB+ 64,*/
417:
418: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
419: 0, /* offset dout_phaseB+ 64,*/
420:
421: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
422: 0, /* offset din_phaseB+ 72,*/
423:
424: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
425: 0, /* offset dout_phaseB+ 72,*/
426:
427: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
428: 0, /* offset din_phaseB+ 80,*/
429:
430: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
431: 0, /* offset dout_phaseB+ 80,*/
432:
433: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
434: 0, /* offset din_phaseB+ 88,*/
435:
436: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
437: 0, /* offset dout_phaseB+ 88,*/
438:
439: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
440: 0, /* offset din_phaseB+ 96,*/
441:
442: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
443: 0, /* offset dout_phaseB+ 96,*/
444:
445: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
446: 0, /* offset din_phaseB+ 104,*/
447:
448: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
449: 0, /* offset dout_phaseB+ 104,*/
450:
451: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
452: 0, /* offset din_phaseB+ 112,*/
453:
454: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
455: 0, /* offset dout_phaseB+ 112,*/
456:
457: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
458: 0, /* offset din_phaseB+ 120,*/
459:
460: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
461: 0, /* offset dout_phaseB+ 120,*/
462:
463: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
464: 0, /* offset din_phaseB+ 128,*/
465:
466: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
467: 0 /* offset dout_phaseB+ 128 */
468: };
469: ULONG jump_table0[]={
470: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_
471: };
472: ULONG jmp_din_pad_0[]={
473: 0, /* offset din_pad_0,*/
474:
475: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_
476: };
477: ULONG jmp_dout_pad_0[]={
478: 0 /* offset dout_pad_0 */
479: };
480:
481: #define jump_tableB jump_table0
482: /*
483: ;==========================================================
484: ; Data in phase
485: ;==========================================================
486: */
487: ULONG din_phaseB[]={
488: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
489: 0, /* offset SRB.Segment0,*/
490: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
491: 0, /* offset SRB.Segment1,*/
492: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
493: 0, /* offset SRB.Segment2,*/
494: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
495: 0, /* offset SRB.Segment3,*/
496: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
497: 0, /* offset SRB.Segment4,*/
498: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
499: 0, /* offset SRB.Segment5,*/
500: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
501: 0, /* offset SRB.Segment6,*/
502: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
503: 0, /* offset SRB.Segment7,*/
504: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
505: 0, /* offset SRB.Segment8,*/
506: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
507: 0, /* offset SRB.Segment9,*/
508: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
509: 0, /* offset SRB.Segment10,*/
510: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
511: 0, /* offset SRB.Segment11,*/
512: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
513: 0, /* offset SRB.Segment12,*/
514: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
515: 0, /* offset SRB.Segment13,*/
516: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
517: 0, /* offset SRB.Segment14,*/
518: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
519: 0, /* offset SRB.Segment15,*/
520: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
521: 0, /* offset SRB.Segment0,*/
522: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
523: 0, /* offset SRB.Segment1,*/
524: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
525: 0, /* offset SRB.Segment2,*/
526: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
527: 0, /* offset SRB.Segment3,*/
528: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
529: 0, /* offset SRB.Segment4,*/
530: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
531: 0, /* offset SRB.Segment5,*/
532: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
533: 0, /* offset SRB.Segment6,*/
534: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
535: 0, /* offset SRB.Segment7,*/
536: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
537: 0, /* offset SRB.Segment8,*/
538: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
539: 0, /* offset SRB.Segment9,*/
540: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
541: 0, /* offset SRB.Segment10,*/
542: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
543: 0, /* offset SRB.Segment11,*/
544: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
545: 0, /* offset SRB.Segment12,*/
546: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
547: 0, /* offset SRB.Segment13,*/
548: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
549: 0, /* offset SRB.Segment14,*/
550: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
551: 0, /* offset SRB.Segment15,*/
552: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,
553: 0, /* offset SRB.Segment16,*/
554:
555: RD_MODIFY_WRT+OP_OR+0x100+0x340000, /*;(1 shl 8) or (__scratcha shl 16)*/
556: 0,
557:
558: DCMD_JUMP+WAIT_PHASE_VALID+IF_NOT+PHASE_CMP+DATA_IN_
559: };
560: ULONG jmp_status1_phase[]={
561: 0 /* offset status1_phase */
562: };
563:
564: #define din_phase din_phaseB
565:
566: ULONG din_pad_0[]={
567: RD_MODIFY_WRT+OP_OR+0x340000+0x400, /*;(4 shl 8) or (__scratcha shl 16)*/
568: 0
569: };
570: ULONG din_pad_addrB[]={
571: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_
572: };
573: ULONG SRB_SegmentPad[]={
574: 0, /* offset SRB.SegmentPad,*/
575:
576: DCMD_JUMP+IF_TRUE
577: };
578: ULONG jmp_din_pad_addrB[]={
579: 0 /* offset din_pad_addrB */
580: };
581: /*
582: ;==========================================================
583: ; Data out phase
584: ;==========================================================
585: */
586: ULONG dout_phaseB[]={
587: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
588: 0, /* offset SRB.Segment0,*/
589: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
590: 0, /* offset SRB.Segment1,*/
591: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
592: 0, /* offset SRB.Segment2,*/
593: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
594: 0, /* offset SRB.Segment3,*/
595: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
596: 0, /* offset SRB.Segment4,*/
597: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
598: 0, /* offset SRB.Segment5,*/
599: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
600: 0, /* offset SRB.Segment6,*/
601: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
602: 0, /* offset SRB.Segment7,*/
603: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
604: 0, /* offset SRB.Segment8,*/
605: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
606: 0, /* offset SRB.Segment9,*/
607: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
608: 0, /* offset SRB.Segment10,*/
609: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
610: 0, /* offset SRB.Segment11,*/
611: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
612: 0, /* offset SRB.Segment12,*/
613: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
614: 0, /* offset SRB.Segment13,*/
615: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
616: 0, /* offset SRB.Segment14,*/
617: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
618: 0, /* offset SRB.Segment15,*/
619: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
620: 0, /* offset SRB.Segment0,*/
621: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
622: 0, /* offset SRB.Segment1,*/
623: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
624: 0, /* offset SRB.Segment2,*/
625: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
626: 0, /* offset SRB.Segment3,*/
627: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
628: 0, /* offset SRB.Segment4,*/
629: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
630: 0, /* offset SRB.Segment5,*/
631: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
632: 0, /* offset SRB.Segment6,*/
633: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
634: 0, /* offset SRB.Segment7,*/
635: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
636: 0, /* offset SRB.Segment8,*/
637: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
638: 0, /* offset SRB.Segment9,*/
639: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
640: 0, /* offset SRB.Segment10,*/
641: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
642: 0, /* offset SRB.Segment11,*/
643: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
644: 0, /* offset SRB.Segment12,*/
645: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
646: 0, /* offset SRB.Segment13,*/
647: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
648: 0, /* offset SRB.Segment14,*/
649: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
650: 0, /* offset SRB.Segment15,*/
651: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
652: 0, /* offset SRB.Segment16,*/
653:
654: RD_MODIFY_WRT+OP_OR+0x100+0x340000, /*;(1 shl 8) or (__scratcha shl 16)*/
655: 0,
656:
657: DCMD_JUMP+WAIT_PHASE_VALID+IF_NOT+PHASE_CMP+DATA_OUT_
658: };
659: ULONG jmp_status1_phase1[]={
660: 0 /* offset status1_phase */
661: };
662:
663: #define dout_phase dout_phaseB
664:
665: ULONG dout_pad_0[]={
666: RD_MODIFY_WRT+OP_OR+0x340000+0x400, /*;(4 shl 8) or (__scratcha shl 16)*/
667: 0
668: };
669: ULONG dout_pad_addrB[]={
670: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_
671: };
672: ULONG SRB_SegmentPad1[]={
673: 0, /* offset SRB.SegmentPad,*/
674:
675: DCMD_JUMP+IF_TRUE
676: };
677: ULONG jmp_dout_pad_addrB[]={
678: 0 /* offset dout_pad_addrB */
679: };
680: /*
681: ;==========================================================
682: ; Data phase jump table for WIDE SCSI operation
683: ;==========================================================
684: */
685: ULONG jmp_dio_phaseW[]={
686:
687: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
688: 0, /* offset din_phaseW+ 0,*/
689:
690: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
691: 0, /* offset dout_phaseW+ 0,*/
692:
693: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
694: 0, /* offset din_phaseW+ 8,*/
695:
696: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
697: 0, /* offset dout_phaseW+ 8,*/
698:
699: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
700: 0, /* offset din_phaseW+ 16,*/
701:
702: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
703: 0, /* offset dout_phaseW+ 16,*/
704:
705: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
706: 0, /* offset din_phaseW+ 24,*/
707:
708: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
709: 0, /* offset dout_phaseW+ 24,*/
710:
711: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
712: 0, /* offset din_phaseW+ 32,*/
713:
714: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
715: 0, /* offset dout_phaseW+ 32,*/
716:
717: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
718: 0, /* offset din_phaseW+ 40,*/
719:
720: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
721: 0, /* offset dout_phaseW+ 40,*/
722:
723: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
724: 0, /* offset din_phaseW+ 48,*/
725:
726: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
727: 0, /* offset dout_phaseW+ 48,*/
728:
729: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
730: 0, /* offset din_phaseW+ 56,*/
731:
732: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
733: 0, /* offset dout_phaseW+ 56,*/
734:
735: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
736: 0, /* offset din_phaseW+ 64,*/
737:
738: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
739: 0, /* offset dout_phaseW+ 64,*/
740:
741: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
742: 0, /* offset din_phaseW+ 72,*/
743:
744: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
745: 0, /* offset dout_phaseW+ 72,*/
746:
747: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
748: 0, /* offset din_phaseW+ 80,*/
749:
750: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
751: 0, /* offset dout_phaseW+ 80,*/
752:
753: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
754: 0, /* offset din_phaseW+ 88,*/
755:
756: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
757: 0, /* offset dout_phaseW+ 88,*/
758:
759: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
760: 0, /* offset din_phaseW+ 96,*/
761:
762: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
763: 0, /* offset dout_phaseW+ 96,*/
764:
765: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
766: 0, /* offset din_phaseW+ 104,*/
767:
768: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
769: 0, /* offset dout_phaseW+ 104,*/
770:
771: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
772: 0, /* offset din_phaseW+ 112,*/
773:
774: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
775: 0, /* offset dout_phaseW+ 112,*/
776:
777: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
778: 0, /* offset din_phaseW+ 120,*/
779:
780: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
781: 0, /* offset dout_phaseW+ 120,*/
782:
783: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
784: 0, /* offset din_phaseW+ 0,*/
785:
786: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
787: 0, /* offset dout_phaseW+ 0,*/
788:
789: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
790: 0, /* offset din_phaseW+ 8,*/
791:
792: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
793: 0, /* offset dout_phaseW+ 8,*/
794:
795: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
796: 0, /* offset din_phaseW+ 16,*/
797:
798: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
799: 0, /* offset dout_phaseW+ 16,*/
800:
801: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
802: 0, /* offset din_phaseW+ 24,*/
803:
804: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
805: 0, /* offset dout_phaseW+ 24,*/
806:
807: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
808: 0, /* offset din_phaseW+ 32,*/
809:
810: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
811: 0, /* offset dout_phaseW+ 32,*/
812:
813: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
814: 0, /* offset din_phaseW+ 40,*/
815:
816: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
817: 0, /* offset dout_phaseW+ 40,*/
818:
819: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
820: 0, /* offset din_phaseW+ 48,*/
821:
822: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
823: 0, /* offset dout_phaseW+ 48,*/
824:
825: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
826: 0, /* offset din_phaseW+ 56,*/
827:
828: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
829: 0, /* offset dout_phaseW+ 56,*/
830:
831: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
832: 0, /* offset din_phaseW+ 64,*/
833:
834: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
835: 0, /* offset dout_phaseW+ 64,*/
836:
837: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
838: 0, /* offset din_phaseW+ 72,*/
839:
840: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
841: 0, /* offset dout_phaseW+ 72,*/
842:
843: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
844: 0, /* offset din_phaseW+ 80,*/
845:
846: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
847: 0, /* offset dout_phaseW+ 80,*/
848:
849: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
850: 0, /* offset din_phaseW+ 88,*/
851:
852: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
853: 0, /* offset dout_phaseW+ 88,*/
854:
855: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
856: 0, /* offset din_phaseW+ 96,*/
857:
858: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
859: 0, /* offset dout_phaseW+ 96,*/
860:
861: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
862: 0, /* offset din_phaseW+ 104,*/
863:
864: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
865: 0, /* offset dout_phaseW+ 104,*/
866:
867: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
868: 0, /* offset din_phaseW+ 112,*/
869:
870: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
871: 0, /* offset dout_phaseW+ 112,*/
872:
873: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
874: 0, /* offset din_phaseW+ 120,*/
875:
876: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
877: 0, /* offset dout_phaseW+ 120,*/
878:
879: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,
880: 0, /* offset din_phaseW+ 128,*/
881:
882: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,
883: 0 /* offset dout_phaseW+ 128 */
884: };
885: ULONG jump_tablew[]={
886: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_
887: };
888: ULONG jmp_din_pad_1[]={
889: 0, /* offset din_pad_1,*/
890:
891: DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_
892: };
893: ULONG jmp_dout_pad_1[]={
894: 0 /* offset dout_pad_1 */
895: };
896:
897: #define jump_tableW jump_tablew
898: /*
899: ;==========================================================
900: ; Data in phase
901: ;==========================================================
902: */
903: ULONG din_phaseW[]={
904: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
905: 0, /* offset SRB.Segment0,*/
906: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
907: 0, /* offset SRB.Segment1,*/
908: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
909: 0, /* offset SRB.Segment2,*/
910: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
911: 0, /* offset SRB.Segment3,*/
912: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
913: 0, /* offset SRB.Segment4,*/
914: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
915: 0, /* offset SRB.Segment5,*/
916: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
917: 0, /* offset SRB.Segment6,*/
918: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
919: 0, /* offset SRB.Segment7,*/
920: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
921: 0, /* offset SRB.Segment8,*/
922: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
923: 0, /* offset SRB.Segment9,*/
924: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
925: 0, /* offset SRB.Segment10,*/
926: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
927: 0, /* offset SRB.Segment11,*/
928: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
929: 0, /* offset SRB.Segment12,*/
930: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
931: 0, /* offset SRB.Segment13,*/
932: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
933: 0, /* offset SRB.Segment14,*/
934: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
935: 0, /* offset SRB.Segment15,*/
936: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
937: 0, /* offset SRB.Segment0,*/
938: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
939: 0, /* offset SRB.Segment1,*/
940: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
941: 0, /* offset SRB.Segment2,*/
942: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
943: 0, /* offset SRB.Segment3,*/
944: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
945: 0, /* offset SRB.Segment4,*/
946: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
947: 0, /* offset SRB.Segment5,*/
948: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
949: 0, /* offset SRB.Segment6,*/
950: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
951: 0, /* offset SRB.Segment7,*/
952: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
953: 0, /* offset SRB.Segment8,*/
954: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
955: 0, /* offset SRB.Segment9,*/
956: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
957: 0, /* offset SRB.Segment10,*/
958: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
959: 0, /* offset SRB.Segment11,*/
960: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
961: 0, /* offset SRB.Segment12,*/
962: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
963: 0, /* offset SRB.Segment13,*/
964: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
965: 0, /* offset SRB.Segment14,*/
966: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
967: 0, /* offset SRB.Segment15,*/
968: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
969: 0, /* offset SRB.Segment16,*/
970:
971: RD_MODIFY_WRT+OP_OR+0x340000+0x100, /*;(1 shl 8) or (__scratcha shl 16)*/
972: 0,
973:
974: DCMD_JUMP+WAIT_PHASE_VALID+IF_NOT+PHASE_CMP+DATA_IN_
975: };
976: ULONG jmp_status1_phase2[]={
977: 0 /* offset status1_phase */
978: };
979:
980: #define din_phase1 din_phaseW
981:
982: ULONG din_pad_1[]={
983: RD_MODIFY_WRT+OP_OR+0x340000+0x400, /*;(4 shl 8) or (__scratcha shl 16)*/
984: 0
985: };
986: ULONG din_pad_addrW[]={
987: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_
988: };
989: ULONG SRB_SegmentPad2[]={
990: 0, /* offset SRB.SegmentPad,*/
991:
992: DCMD_JUMP+IF_TRUE
993: };
994: ULONG jmp_din_pad_addrW[]={
995: 0 /* offset din_pad_addrW */
996: };
997: /*
998: ;==========================================================
999: ; Data out phase
1000: ;==========================================================
1001: */
1002: ULONG dout_phaseW[]={
1003: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1004: 0, /* offset SRB.Segment0,*/
1005: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1006: 0, /* offset SRB.Segment1,*/
1007: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1008: 0, /* offset SRB.Segment2,*/
1009: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1010: 0, /* offset SRB.Segment3,*/
1011: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1012: 0, /* offset SRB.Segment4,*/
1013: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1014: 0, /* offset SRB.Segment5,*/
1015: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1016: 0, /* offset SRB.Segment6,*/
1017: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1018: 0, /* offset SRB.Segment7,*/
1019: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1020: 0, /* offset SRB.Segment8,*/
1021: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1022: 0, /* offset SRB.Segment9,*/
1023: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1024: 0, /* offset SRB.Segment10,*/
1025: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1026: 0, /* offset SRB.Segment11,*/
1027: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1028: 0, /* offset SRB.Segment12,*/
1029: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1030: 0, /* offset SRB.Segment13,*/
1031: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1032: 0, /* offset SRB.Segment14,*/
1033: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1034: 0, /* offset SRB.Segment15,*/
1035: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1036: 0, /* offset SRB.Segment0,*/
1037: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1038: 0, /* offset SRB.Segment1,*/
1039: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1040: 0, /* offset SRB.Segment2,*/
1041: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1042: 0, /* offset SRB.Segment3,*/
1043: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1044: 0, /* offset SRB.Segment4,*/
1045: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1046: 0, /* offset SRB.Segment5,*/
1047: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1048: 0, /* offset SRB.Segment6,*/
1049: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1050: 0, /* offset SRB.Segment7,*/
1051: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1052: 0, /* offset SRB.Segment8,*/
1053: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1054: 0, /* offset SRB.Segment9,*/
1055: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1056: 0, /* offset SRB.Segment10,*/
1057: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1058: 0, /* offset SRB.Segment11,*/
1059: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1060: 0, /* offset SRB.Segment12,*/
1061: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1062: 0, /* offset SRB.Segment13,*/
1063: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1064: 0, /* offset SRB.Segment14,*/
1065: DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_OUT_,
1066: 0, /* offset SRB.Segment15,*/
1067: /*; 18000000h or DATA_OUT_ */
1068: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,
1069: 0, /* offset SRB.Segment16,*/
1070:
1071: RD_MODIFY_WRT+OP_OR+0x340000+0x100, /*;(1 shl 8) or (__scratcha shl 16)*/
1072: 0,
1073:
1074: DCMD_JUMP+WAIT_PHASE_VALID+IF_NOT+PHASE_CMP+DATA_OUT_
1075: };
1076: ULONG jmp_status1_phase3[]={
1077: 0 /* offset status1_phase */
1078: };
1079:
1080: #define dout_phase1 dout_phaseW
1081:
1082: ULONG dout_pad_1[]={
1083: RD_MODIFY_WRT+OP_OR+0x340000+0x400, /*;(4 shl 8) or (__scratcha shl 16)*/
1084: 0
1085: };
1086: ULONG dout_pad_addrW[]={
1087: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_
1088: };
1089: ULONG SRB_SegmentPad3[]={
1090: 0, /* offset SRB.SegmentPad,*/
1091:
1092: DCMD_JUMP+IF_TRUE
1093: };
1094: ULONG jmp_dout_pad_addrW[]={
1095: 0 /* offset dout_pad_addrW */
1096: };
1097: /*
1098: ;==========================================================
1099: ; message out phase
1100: ;==========================================================
1101: */
1102: ULONG mout_phase[]={
1103: DCMD_SET_ATN,
1104: 0,
1105:
1106: DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+MSG_OUT_
1107: };
1108: ULONG SRB_msgout01[]={
1109: 0, /* offset SRB.__msgout0,*/
1110:
1111: DCMD_JUMP+IF_TRUE
1112: };
1113: ULONG jmp_check_phase2[]={
1114: 0 /* offset check_phase */
1115: };
1116: /*
1117: ;==========================================================
1118: ; Status phase process
1119: ;==========================================================
1120: */
1121: ULONG status_phase[]={
1122: DCMD_BLOCK_MOVE+BLOCK_MOVE+STATUS_+1
1123: };
1124: ULONG ACB_status[]={
1125: 0 /* offset ACB.status */
1126: };
1127: /*
1128: ;==========================================================
1129: ; message in phase
1130: ;==========================================================
1131: */
1132: ULONG min_phase[]={
1133: DCMD_BLOCK_MOVE+BLOCK_MOVE+MSG_IN_+1
1134: };
1135: ULONG ACB_msgin123_3[]={
1136: 0, /* offset ACB.msgin123,*/
1137:
1138: DCMD_JUMP+IF_NOT+DATA_CMP+CMD_COMPLETE
1139: };
1140: ULONG jmp_jump_msgok[]={
1141: 0 /* offset jump_msgok */
1142: };
1143: /*
1144: ;==========================================================
1145: ; command complete message
1146: ;==========================================================
1147: */
1148: ULONG msg__0[]={
1149: RD_MODIFY_WRT+OP_AND+0x20000+0x7F00, /*;(7FH shl 8) or (__scntl2 shl 16)*/
1150: 0,
1151:
1152: DCMD_CLR_ACK,
1153: 0,
1154:
1155: DCMD_WAIT_DISC,
1156: 0,
1157:
1158: DCMD_INT+IF_TRUE,
1159: __COMPLETE
1160: };
1161: /*
1162: ;==========================================================
1163: ; Other message
1164: ;==========================================================
1165: */
1166: ULONG jump_msgok[]={
1167: DCMD_JUMP+IF_TRUE+DATA_CMP+SAVE_PTR
1168: };
1169: ULONG jmp_msg__a[]={
1170: 0, /* offset msg__a,*/
1171:
1172: DCMD_JUMP+IF_TRUE+DATA_CMP+RESTORE_PTR
1173: };
1174: ULONG jmp_msg__3[]={
1175: 0, /* offset msg__3,*/
1176:
1177: DCMD_JUMP+IF_TRUE+DATA_CMP+DISCONNECTMSG
1178: };
1179: ULONG jmp_msg__4[]={
1180: 0, /* offset msg__4,*/
1181:
1182: DCMD_JUMP+IF_TRUE+DATA_CMP+EXT_MSG
1183: };
1184: ULONG jmp_msg__1[]={
1185: 0, /* offset msg__1,*/
1186:
1187: DCMD_INT+IF_TRUE+DATA_CMP+MSG_REJECT,
1188: __MSGREJECT,
1189:
1190: DCMD_JUMP+IF_TRUE+DATA_CMP+LINK_CMD_CPL
1191: };
1192: ULONG jmp_msg__a1[]={
1193: 0, /* offset msg__a,*/
1194:
1195: DCMD_JUMP+IF_TRUE+DATA_CMP+LINK_CMD_FLAG
1196: };
1197: ULONG jmp_msg__a2[]={
1198: 0, /* offset msg__a,*/
1199:
1200: DCMD_JUMP+IF_TRUE+DATA_CMP+IGNORE_WIDE_RES
1201: };
1202: ULONG jmp_msg__23[]={
1203: 0, /* offset msg__23,*/
1204:
1205: DCMD_INT+IF_TRUE,
1206: __MSGUNKNOWN
1207: };
1208: /*
1209: ;==========================================================
1210: ; Extended message
1211: ;==========================================================
1212: */
1213: ULONG msg__1[]={
1214: DCMD_CLR_ACK,
1215: 0,
1216:
1217: DCMD_BLOCK_MOVE+BLOCK_MOVE+MSG_IN_+1 /* ;ext msg len */
1218: };
1219: ULONG ACB_msgin123_4[]={
1220: 0, /* offset ACB.msgin123,*/
1221:
1222: DCMD_JUMP+IF_TRUE+DATA_CMP+3
1223: };
1224: ULONG jmp_msg___3[]={
1225: 0, /* offset msg___3,*/
1226:
1227: DCMD_JUMP+IF_TRUE+DATA_CMP+2
1228: };
1229: ULONG jmp_msg___2[]={
1230: 0, /* offset msg___2,*/
1231:
1232: DCMD_INT+IF_TRUE,
1233: __MSGEXTEND
1234: };
1235:
1236: ULONG msg___3[]={
1237: DCMD_CLR_ACK,
1238: 0,
1239:
1240: DCMD_BLOCK_MOVE+BLOCK_MOVE+MSG_IN_+3
1241: };
1242: ULONG ACB_msgin123_5[]={
1243: 0, /* offset ACB.msgin123,*/
1244:
1245: DCMD_INT+IF_TRUE,
1246: __MSGSYNC
1247: };
1248:
1249: ULONG msg___2[]={
1250: DCMD_CLR_ACK,
1251: 0,
1252:
1253: DCMD_BLOCK_MOVE+BLOCK_MOVE+MSG_IN_+2
1254: };
1255: ULONG ACB_msgin123_6[]={
1256: 0, /* offset ACB.msgin123,*/
1257:
1258: DCMD_INT+IF_TRUE,
1259: __MSGWIDE
1260: };
1261: /*
1262: ;############################################################
1263: ; for synchronous negotiation
1264: ; 1. Active ==> INT3, restart at data__1_2
1265: ; 2. Passive ==> INT3, prepare message out, restart at data__1_1
1266: ; 3. Disable ==> INT3, prepare message out, restart at data__1_1
1267: ;############################################################
1268: */
1269: ULONG set_atn[]={
1270: DCMD_SET_ATN,
1271: 0
1272: };
1273: ULONG msg__a[]={
1274: DCMD_CLR_ACK,
1275: 0,
1276:
1277: DCMD_JUMP+IF_TRUE
1278: };
1279: ULONG jmp_check_phase3[]={
1280: 0 /* offset check_phase */
1281: };
1282:
1283: ULONG msg__23[]={ /* ; ignore wide residue */
1284: DCMD_CLR_ACK,
1285: 0,
1286:
1287: DCMD_BLOCK_MOVE+BLOCK_MOVE+MSG_IN_+1
1288: };
1289: ULONG ACB_msgin123_7[]={
1290: 0, /* offset ACB.msgin123,*/
1291:
1292: DCMD_CLR_ACK,
1293: 0,
1294:
1295: DCMD_JUMP+IF_TRUE
1296: };
1297: ULONG jmp_check_phase4[]={
1298: 0 /* offset check_phase */
1299: };
1300:
1301: ULONG msg__3[]={
1302: DCMD_CLR_ACK,
1303: 0,
1304:
1305: DCMD_JUMP+IF_TRUE
1306: };
1307: ULONG jmp_check_phase5[]={
1308: 0 /* offset check_phase */
1309: };
1310:
1311: ULONG msg__4[]={ /* ; disconnect */
1312: RD_MODIFY_WRT+OP_AND+0x20000+0x7F00, /*;(7FH shl 8) or (__scntl2 shl 16)*/
1313: 0,
1314:
1315: DCMD_CLR_ACK,
1316: 0,
1317:
1318: DCMD_WAIT_DISC,
1319: 0,
1320:
1321: DCMD_INT+IF_TRUE,
1322: __DISCONNECTED
1323: };
1324:
1325: ULONG clr_atn[]={
1326: DCMD_CLR_ATN,
1327: 0,
1328:
1329: DCMD_JUMP+IF_TRUE
1330: };
1331: ULONG jmp_check_phase6[]={
1332: 0 /* offset check_phase */
1333: };
1334: /*
1335: ;==========================================================
1336: ; Used for script operation
1337: ;==========================================================
1338: */
1339: ULONG start_mov[]={
1340: /*; DCMD_MEM_MOVE+(OFFSET DGROUP:end_script - OFFSET DGROUP:start_script) ;Memory move SCRIPTS instruction*/
1341: DCMD_MEM_MOVE+0x1000 /*;Memory move SCRIPTS instruction ( 4K )*/
1342: };
1343: ULONG SrcPhysAddr[]={
1344: 0 /*; source */
1345: };
1346: ULONG DesPhysAddr[]={
1347: 0, /*; destination */
1348:
1349: DCMD_INT+IF_TRUE, /*; script interrupt, */
1350: 0,
1351:
1352: DCMD_INT+IF_NOT, /*; script interrupt */
1353: 0
1354: };
1355: ULONG end_script[]={0};
1356: /***********************************************************************/
1357:
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