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1.1 ! root 1: /****************************************************************************** ! 2: ** High Performance device driver for the Symbios 53C896 controller. ! 3: ** ! 4: ** Copyright (C) 1998-2000 Gerard Roudier <[email protected]> ! 5: ** ! 6: ** This driver also supports all the Symbios 53C8XX controller family, ! 7: ** except 53C810 revisions < 16, 53C825 revisions < 16 and all ! 8: ** revisions of 53C815 controllers. ! 9: ** ! 10: ** This driver is based on the Linux port of the FreeBSD ncr driver. ! 11: ** ! 12: ** Copyright (C) 1994 Wolfgang Stanglmeier ! 13: ** ! 14: **----------------------------------------------------------------------------- ! 15: ** ! 16: ** This program is free software; you can redistribute it and/or modify ! 17: ** it under the terms of the GNU General Public License as published by ! 18: ** the Free Software Foundation; either version 2 of the License, or ! 19: ** (at your option) any later version. ! 20: ** ! 21: ** This program is distributed in the hope that it will be useful, ! 22: ** but WITHOUT ANY WARRANTY; without even the implied warranty of ! 23: ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! 24: ** GNU General Public License for more details. ! 25: ** ! 26: ** You should have received a copy of the GNU General Public License ! 27: ** along with this program; if not, write to the Free Software ! 28: ** Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ! 29: ** ! 30: **----------------------------------------------------------------------------- ! 31: ** ! 32: ** The Linux port of the FreeBSD ncr driver has been achieved in ! 33: ** november 1995 by: ! 34: ** ! 35: ** Gerard Roudier <[email protected]> ! 36: ** ! 37: ** Being given that this driver originates from the FreeBSD version, and ! 38: ** in order to keep synergy on both, any suggested enhancements and corrections ! 39: ** received on Linux are automatically a potential candidate for the FreeBSD ! 40: ** version. ! 41: ** ! 42: ** The original driver has been written for 386bsd and FreeBSD by ! 43: ** Wolfgang Stanglmeier <[email protected]> ! 44: ** Stefan Esser <[email protected]> ! 45: ** ! 46: **----------------------------------------------------------------------------- ! 47: ** ! 48: ** Major contributions: ! 49: ** -------------------- ! 50: ** ! 51: ** NVRAM detection and reading. ! 52: ** Copyright (C) 1997 Richard Waltham <[email protected]> ! 53: ** ! 54: ******************************************************************************* ! 55: */ ! 56: ! 57: #ifndef SYM53C8XX_DEFS_H ! 58: #define SYM53C8XX_DEFS_H ! 59: ! 60: /* ! 61: ** Check supported Linux versions ! 62: */ ! 63: ! 64: #if !defined(LINUX_VERSION_CODE) ! 65: #include <linux/version.h> ! 66: #endif ! 67: #include <linux/config.h> ! 68: ! 69: #ifndef LinuxVersionCode ! 70: #define LinuxVersionCode(v, p, s) (((v)<<16)+((p)<<8)+(s)) ! 71: #endif ! 72: ! 73: /* ! 74: * NCR PQS/PDS special device support. ! 75: */ ! 76: #ifdef CONFIG_SCSI_NCR53C8XX_PQS_PDS ! 77: #define SCSI_NCR_PQS_PDS_SUPPORT ! 78: #endif ! 79: ! 80: /* ! 81: * No more an option, enabled by default. ! 82: */ ! 83: #ifndef CONFIG_SCSI_NCR53C8XX_NVRAM_DETECT ! 84: #define CONFIG_SCSI_NCR53C8XX_NVRAM_DETECT ! 85: #endif ! 86: ! 87: /* ! 88: ** These options are not tunable from 'make config' ! 89: */ ! 90: //#define SCSI_NCR_PROC_INFO_SUPPORT ! 91: ! 92: /* ! 93: ** If you want a driver as small as possible, donnot define the ! 94: ** following options. ! 95: */ ! 96: #define SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT ! 97: #define SCSI_NCR_DEBUG_INFO_SUPPORT ! 98: #define SCSI_NCR_PCI_FIX_UP_SUPPORT ! 99: #ifdef SCSI_NCR_PROC_INFO_SUPPORT ! 100: # define SCSI_NCR_USER_COMMAND_SUPPORT ! 101: # define SCSI_NCR_USER_INFO_SUPPORT ! 102: #endif ! 103: ! 104: /* ! 105: ** To disable integrity checking, do not define the ! 106: ** following option. ! 107: */ ! 108: #ifdef CONFIG_SCSI_NCR53C8XX_INTEGRITY_CHECK ! 109: # define SCSI_NCR_ENABLE_INTEGRITY_CHECK ! 110: #endif ! 111: ! 112: /*========================================================== ! 113: ** ! 114: ** nvram settings - #define SCSI_NCR_NVRAM_SUPPORT to enable ! 115: ** ! 116: **========================================================== ! 117: */ ! 118: ! 119: #ifdef CONFIG_SCSI_NCR53C8XX_NVRAM_DETECT ! 120: #define SCSI_NCR_NVRAM_SUPPORT ! 121: /* #define SCSI_NCR_DEBUG_NVRAM */ ! 122: #endif ! 123: ! 124: /* --------------------------------------------------------------------- ! 125: ** Take into account kernel configured parameters. ! 126: ** Most of these options can be overridden at startup by a command line. ! 127: ** --------------------------------------------------------------------- ! 128: */ ! 129: ! 130: /* ! 131: * For Ultra2 and Ultra3 SCSI support option, use special features. ! 132: * ! 133: * Value (default) means: ! 134: * bit 0 : all features enabled, except: ! 135: * bit 1 : PCI Write And Invalidate. ! 136: * bit 2 : Data Phase Mismatch handling from SCRIPTS. ! 137: * ! 138: * Use boot options ncr53c8xx=specf:1 if you want all chip features to be ! 139: * enabled by the driver. ! 140: */ ! 141: #define SCSI_NCR_SETUP_SPECIAL_FEATURES (3) ! 142: ! 143: /* ! 144: * For Ultra2 and Ultra3 SCSI support allow 80Mhz synchronous data transfers. ! 145: * Value means: ! 146: * 0 - Ultra speeds disabled ! 147: * 1 - Ultra enabled (Maximum 20Mtrans/sec) ! 148: * 2 - Ultra2 enabled (Maximum 40Mtrans/sec) ! 149: * 3 - Ultra3 enabled (Maximum 80Mtrans/sec) ! 150: * ! 151: * Use boot options sym53c8xx=ultra:3 to enable Ultra3 support. ! 152: */ ! 153: ! 154: #define SCSI_NCR_SETUP_ULTRA_SCSI (3) ! 155: #define SCSI_NCR_MAX_SYNC (80) ! 156: ! 157: /* ! 158: * Allow tags from 2 to 256, default 8 ! 159: */ ! 160: #ifdef CONFIG_SCSI_NCR53C8XX_MAX_TAGS ! 161: #if CONFIG_SCSI_NCR53C8XX_MAX_TAGS < 2 ! 162: #define SCSI_NCR_MAX_TAGS (2) ! 163: #elif CONFIG_SCSI_NCR53C8XX_MAX_TAGS > 256 ! 164: #define SCSI_NCR_MAX_TAGS (256) ! 165: #else ! 166: #define SCSI_NCR_MAX_TAGS CONFIG_SCSI_NCR53C8XX_MAX_TAGS ! 167: #endif ! 168: #else ! 169: #define SCSI_NCR_MAX_TAGS (8) ! 170: #endif ! 171: ! 172: /* ! 173: * Allow tagged command queuing support if configured with default number ! 174: * of tags set to max (see above). ! 175: */ ! 176: #ifdef CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS ! 177: #define SCSI_NCR_SETUP_DEFAULT_TAGS CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS ! 178: #elif defined CONFIG_SCSI_NCR53C8XX_TAGGED_QUEUE ! 179: #define SCSI_NCR_SETUP_DEFAULT_TAGS SCSI_NCR_MAX_TAGS ! 180: #else ! 181: #define SCSI_NCR_SETUP_DEFAULT_TAGS (0) ! 182: #endif ! 183: ! 184: /* ! 185: * Use normal IO if configured. Forced for alpha and powerpc. ! 186: * Powerpc fails copying to on-chip RAM using memcpy_toio(). ! 187: */ ! 188: #if defined(CONFIG_SCSI_NCR53C8XX_IOMAPPED) ! 189: #define SCSI_NCR_IOMAPPED ! 190: #elif defined(__alpha__) ! 191: #define SCSI_NCR_IOMAPPED ! 192: #elif defined(__powerpc__) ! 193: #define SCSI_NCR_IOMAPPED ! 194: #define SCSI_NCR_PCI_MEM_NOT_SUPPORTED ! 195: #elif defined(__sparc__) ! 196: #undef SCSI_NCR_IOMAPPED ! 197: #endif ! 198: ! 199: /* ! 200: * Should we enable DAC cycles on this platform? ! 201: * Until further investigation we do not enable it ! 202: * anywhere at the moment. ! 203: */ ! 204: #undef SCSI_NCR_USE_64BIT_DAC ! 205: ! 206: /* ! 207: * Immediate arbitration ! 208: */ ! 209: #if defined(CONFIG_SCSI_NCR53C8XX_IARB) ! 210: #define SCSI_NCR_IARB_SUPPORT ! 211: #endif ! 212: ! 213: /* ! 214: * Should we enable DAC cycles on sparc64 platforms? ! 215: * Until further investigation we do not enable it ! 216: * anywhere at the moment. ! 217: */ ! 218: #undef SCSI_NCR_USE_64BIT_DAC ! 219: ! 220: /* ! 221: * Sync transfer frequency at startup. ! 222: * Allow from 5Mhz to 80Mhz default 20 Mhz. ! 223: */ ! 224: #ifndef CONFIG_SCSI_NCR53C8XX_SYNC ! 225: #define CONFIG_SCSI_NCR53C8XX_SYNC (20) ! 226: #elif CONFIG_SCSI_NCR53C8XX_SYNC > SCSI_NCR_MAX_SYNC ! 227: #undef CONFIG_SCSI_NCR53C8XX_SYNC ! 228: #define CONFIG_SCSI_NCR53C8XX_SYNC SCSI_NCR_MAX_SYNC ! 229: #endif ! 230: ! 231: #if CONFIG_SCSI_NCR53C8XX_SYNC == 0 ! 232: #define SCSI_NCR_SETUP_DEFAULT_SYNC (255) ! 233: #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 5 ! 234: #define SCSI_NCR_SETUP_DEFAULT_SYNC (50) ! 235: #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 20 ! 236: #define SCSI_NCR_SETUP_DEFAULT_SYNC (250/(CONFIG_SCSI_NCR53C8XX_SYNC)) ! 237: #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 33 ! 238: #define SCSI_NCR_SETUP_DEFAULT_SYNC (11) ! 239: #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 40 ! 240: #define SCSI_NCR_SETUP_DEFAULT_SYNC (10) ! 241: #else ! 242: #define SCSI_NCR_SETUP_DEFAULT_SYNC (9) ! 243: #endif ! 244: ! 245: /* ! 246: * Disallow disconnections at boot-up ! 247: */ ! 248: #ifdef CONFIG_SCSI_NCR53C8XX_NO_DISCONNECT ! 249: #define SCSI_NCR_SETUP_DISCONNECTION (0) ! 250: #else ! 251: #define SCSI_NCR_SETUP_DISCONNECTION (1) ! 252: #endif ! 253: ! 254: /* ! 255: * Force synchronous negotiation for all targets ! 256: */ ! 257: #ifdef CONFIG_SCSI_NCR53C8XX_FORCE_SYNC_NEGO ! 258: #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (1) ! 259: #else ! 260: #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (0) ! 261: #endif ! 262: ! 263: /* ! 264: * Disable master parity checking (flawed hardwares need that) ! 265: */ ! 266: #ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_MPARITY_CHECK ! 267: #define SCSI_NCR_SETUP_MASTER_PARITY (0) ! 268: #else ! 269: #define SCSI_NCR_SETUP_MASTER_PARITY (1) ! 270: #endif ! 271: ! 272: /* ! 273: * Disable scsi parity checking (flawed devices may need that) ! 274: */ ! 275: #ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_PARITY_CHECK ! 276: #define SCSI_NCR_SETUP_SCSI_PARITY (0) ! 277: #else ! 278: #define SCSI_NCR_SETUP_SCSI_PARITY (1) ! 279: #endif ! 280: ! 281: /* ! 282: * Vendor specific stuff ! 283: */ ! 284: #ifdef CONFIG_SCSI_NCR53C8XX_SYMBIOS_COMPAT ! 285: #define SCSI_NCR_SETUP_LED_PIN (1) ! 286: #define SCSI_NCR_SETUP_DIFF_SUPPORT (4) ! 287: #else ! 288: #define SCSI_NCR_SETUP_LED_PIN (0) ! 289: #define SCSI_NCR_SETUP_DIFF_SUPPORT (0) ! 290: #endif ! 291: ! 292: /* ! 293: * Settle time after reset at boot-up ! 294: */ ! 295: #define SCSI_NCR_SETUP_SETTLE_TIME (2) ! 296: ! 297: /* ! 298: ** Bridge quirks work-around option defaulted to 1. ! 299: */ ! 300: #ifndef SCSI_NCR_PCIQ_WORK_AROUND_OPT ! 301: #define SCSI_NCR_PCIQ_WORK_AROUND_OPT 1 ! 302: #endif ! 303: ! 304: /* ! 305: ** Work-around common bridge misbehaviour. ! 306: ** ! 307: ** - Do not flush posted writes in the opposite ! 308: ** direction on read. ! 309: ** - May reorder DMA writes to memory. ! 310: ** ! 311: ** This option should not affect performances ! 312: ** significantly, so it is the default. ! 313: */ ! 314: #if SCSI_NCR_PCIQ_WORK_AROUND_OPT == 1 ! 315: #define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM ! 316: #define SCSI_NCR_PCIQ_MAY_REORDER_WRITES ! 317: #define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS ! 318: ! 319: /* ! 320: ** Same as option 1, but also deal with ! 321: ** misconfigured interrupts. ! 322: ** ! 323: ** - Edge triggerred instead of level sensitive. ! 324: ** - No interrupt line connected. ! 325: ** - IRQ number misconfigured. ! 326: ** ! 327: ** If no interrupt is delivered, the driver will ! 328: ** catch the interrupt conditions 10 times per ! 329: ** second. No need to say that this option is ! 330: ** not recommended. ! 331: */ ! 332: #elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 2 ! 333: #define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM ! 334: #define SCSI_NCR_PCIQ_MAY_REORDER_WRITES ! 335: #define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS ! 336: #define SCSI_NCR_PCIQ_BROKEN_INTR ! 337: ! 338: /* ! 339: ** Some bridge designers decided to flush ! 340: ** everything prior to deliver the interrupt. ! 341: ** This option tries to deal with such a ! 342: ** behaviour. ! 343: */ ! 344: #elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 3 ! 345: #define SCSI_NCR_PCIQ_SYNC_ON_INTR ! 346: #endif ! 347: ! 348: /* ! 349: ** Other parameters not configurable with "make config" ! 350: ** Avoid to change these constants, unless you know what you are doing. ! 351: */ ! 352: ! 353: #define SCSI_NCR_ALWAYS_SIMPLE_TAG ! 354: #define SCSI_NCR_MAX_SCATTER (127) ! 355: #define SCSI_NCR_MAX_TARGET (16) ! 356: ! 357: /* ! 358: ** Compute some desirable value for CAN_QUEUE ! 359: ** and CMD_PER_LUN. ! 360: ** The driver will use lower values if these ! 361: ** ones appear to be too large. ! 362: */ ! 363: #define SCSI_NCR_CAN_QUEUE (8*SCSI_NCR_MAX_TAGS + 2*SCSI_NCR_MAX_TARGET) ! 364: #define SCSI_NCR_CMD_PER_LUN (SCSI_NCR_MAX_TAGS) ! 365: ! 366: #define SCSI_NCR_SG_TABLESIZE (SCSI_NCR_MAX_SCATTER) ! 367: #define SCSI_NCR_TIMER_INTERVAL (HZ) ! 368: ! 369: #if 1 /* defined CONFIG_SCSI_MULTI_LUN */ ! 370: #define SCSI_NCR_MAX_LUN (16) ! 371: #else ! 372: #define SCSI_NCR_MAX_LUN (1) ! 373: #endif ! 374: ! 375: #ifndef HOSTS_C ! 376: ! 377: /* ! 378: ** These simple macros limit expression involving ! 379: ** kernel time values (jiffies) to some that have ! 380: ** chance not to be too much incorrect. :-) ! 381: */ ! 382: #define ktime_get(o) (jiffies + (u_long) o) ! 383: #define ktime_exp(b) ((long)(jiffies) - (long)(b) >= 0) ! 384: #define ktime_dif(a, b) ((long)(a) - (long)(b)) ! 385: /* These ones are not used in this driver */ ! 386: #define ktime_add(a, o) ((a) + (u_long)(o)) ! 387: #define ktime_sub(a, o) ((a) - (u_long)(o)) ! 388: ! 389: ! 390: /* ! 391: * IO functions definition for big/little endian CPU support. ! 392: * For now, the NCR is only supported in little endian addressing mode, ! 393: */ ! 394: ! 395: #ifdef __BIG_ENDIAN ! 396: ! 397: #if LINUX_VERSION_CODE < LinuxVersionCode(2,1,0) ! 398: #error "BIG ENDIAN byte ordering needs kernel version >= 2.1.0" ! 399: #endif ! 400: ! 401: #define inw_l2b inw ! 402: #define inl_l2b inl ! 403: #define outw_b2l outw ! 404: #define outl_b2l outl ! 405: #define readw_l2b readw ! 406: #define readl_l2b readl ! 407: #define writew_b2l writew ! 408: #define writel_b2l writel ! 409: ! 410: #else /* little endian */ ! 411: ! 412: #if defined(__i386__) /* i386 implements full FLAT memory/MMIO model */ ! 413: #define inw_raw inw ! 414: #define inl_raw inl ! 415: #define outw_raw outw ! 416: #define outl_raw outl ! 417: #define readb_raw(a) (*(volatile unsigned char *) (a)) ! 418: #define readw_raw(a) (*(volatile unsigned short *) (a)) ! 419: #define readl_raw(a) (*(volatile unsigned int *) (a)) ! 420: #define writeb_raw(b,a) ((*(volatile unsigned char *) (a)) = (b)) ! 421: #define writew_raw(b,a) ((*(volatile unsigned short *) (a)) = (b)) ! 422: #define writel_raw(b,a) ((*(volatile unsigned int *) (a)) = (b)) ! 423: ! 424: #else /* Other little-endian */ ! 425: #define inw_raw inw ! 426: #define inl_raw inl ! 427: #define outw_raw outw ! 428: #define outl_raw outl ! 429: #define readw_raw readw ! 430: #define readl_raw readl ! 431: #define writew_raw writew ! 432: #define writel_raw writel ! 433: ! 434: #endif ! 435: #endif ! 436: ! 437: #ifdef SCSI_NCR_BIG_ENDIAN ! 438: #error "The NCR in BIG ENDIAN addressing mode is not (yet) supported" ! 439: #endif ! 440: ! 441: ! 442: /* ! 443: * IA32 architecture does not reorder STORES and prevents ! 444: * LOADS from passing STORES. It is called `program order' ! 445: * by Intel and allows device drivers to deal with memory ! 446: * ordering by only ensuring that the code is not reordered ! 447: * by the compiler when ordering is required. ! 448: * Other architectures implement a weaker ordering that ! 449: * requires memory barriers (and also IO barriers when they ! 450: * make sense) to be used. ! 451: * We want to be paranoid for ppc and ia64. :) ! 452: */ ! 453: ! 454: #if defined __i386__ ! 455: #define MEMORY_BARRIER() do { ; } while(0) ! 456: #elif defined __powerpc__ ! 457: #define MEMORY_BARRIER() __asm__ volatile("eieio; sync" : : : "memory") ! 458: #elif defined __ia64__ ! 459: #define MEMORY_BARRIER() __asm__ volatile("mf.a; mf" : : : "memory") ! 460: #else ! 461: #define MEMORY_BARRIER() mb() ! 462: #endif ! 463: ! 464: ! 465: /* ! 466: * If the NCR uses big endian addressing mode over the ! 467: * PCI, actual io register addresses for byte and word ! 468: * accesses must be changed according to lane routing. ! 469: * Btw, ncr_offb() and ncr_offw() macros only apply to ! 470: * constants and so donnot generate bloated code. ! 471: */ ! 472: ! 473: #if defined(SCSI_NCR_BIG_ENDIAN) ! 474: ! 475: #define ncr_offb(o) (((o)&~3)+((~((o)&3))&3)) ! 476: #define ncr_offw(o) (((o)&~3)+((~((o)&3))&2)) ! 477: ! 478: #else ! 479: ! 480: #define ncr_offb(o) (o) ! 481: #define ncr_offw(o) (o) ! 482: ! 483: #endif ! 484: ! 485: /* ! 486: * If the CPU and the NCR use same endian-ness addressing, ! 487: * no byte reordering is needed for script patching. ! 488: * Macro cpu_to_scr() is to be used for script patching. ! 489: * Macro scr_to_cpu() is to be used for getting a DWORD ! 490: * from the script. ! 491: */ ! 492: ! 493: #if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN) ! 494: ! 495: #define cpu_to_scr(dw) cpu_to_le32(dw) ! 496: #define scr_to_cpu(dw) le32_to_cpu(dw) ! 497: ! 498: #elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN) ! 499: ! 500: #define cpu_to_scr(dw) cpu_to_be32(dw) ! 501: #define scr_to_cpu(dw) be32_to_cpu(dw) ! 502: ! 503: #else ! 504: ! 505: #define cpu_to_scr(dw) (dw) ! 506: #define scr_to_cpu(dw) (dw) ! 507: ! 508: #endif ! 509: ! 510: /* ! 511: * Access to the controller chip. ! 512: * ! 513: * If SCSI_NCR_IOMAPPED is defined, the driver will use ! 514: * normal IOs instead of the MEMORY MAPPED IO method ! 515: * recommended by PCI specifications. ! 516: * If all PCI bridges, host brigdes and architectures ! 517: * would have been correctly designed for PCI, this ! 518: * option would be useless. ! 519: * ! 520: * If the CPU and the NCR use same endian-ness addressing, ! 521: * no byte reordering is needed for accessing chip io ! 522: * registers. Functions suffixed by '_raw' are assumed ! 523: * to access the chip over the PCI without doing byte ! 524: * reordering. Functions suffixed by '_l2b' are ! 525: * assumed to perform little-endian to big-endian byte ! 526: * reordering, those suffixed by '_b2l' blah, blah, ! 527: * blah, ... ! 528: */ ! 529: ! 530: #if defined(SCSI_NCR_IOMAPPED) ! 531: ! 532: /* ! 533: * IO mapped only input / ouput ! 534: */ ! 535: ! 536: #define INB_OFF(o) inb (np->base_io + ncr_offb(o)) ! 537: #define OUTB_OFF(o, val) outb ((val), np->base_io + ncr_offb(o)) ! 538: ! 539: #if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN) ! 540: ! 541: #define INW_OFF(o) inw_l2b (np->base_io + ncr_offw(o)) ! 542: #define INL_OFF(o) inl_l2b (np->base_io + (o)) ! 543: ! 544: #define OUTW_OFF(o, val) outw_b2l ((val), np->base_io + ncr_offw(o)) ! 545: #define OUTL_OFF(o, val) outl_b2l ((val), np->base_io + (o)) ! 546: ! 547: #elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN) ! 548: ! 549: #define INW_OFF(o) inw_b2l (np->base_io + ncr_offw(o)) ! 550: #define INL_OFF(o) inl_b2l (np->base_io + (o)) ! 551: ! 552: #define OUTW_OFF(o, val) outw_l2b ((val), np->base_io + ncr_offw(o)) ! 553: #define OUTL_OFF(o, val) outl_l2b ((val), np->base_io + (o)) ! 554: ! 555: #else ! 556: ! 557: #define INW_OFF(o) inw_raw (np->base_io + ncr_offw(o)) ! 558: #define INL_OFF(o) inl_raw (np->base_io + (o)) ! 559: ! 560: #define OUTW_OFF(o, val) outw_raw ((val), np->base_io + ncr_offw(o)) ! 561: #define OUTL_OFF(o, val) outl_raw ((val), np->base_io + (o)) ! 562: ! 563: #endif /* ENDIANs */ ! 564: ! 565: #else /* defined SCSI_NCR_IOMAPPED */ ! 566: ! 567: /* ! 568: * MEMORY mapped IO input / output ! 569: */ ! 570: ! 571: #define INB_OFF(o) readb((char *)np->reg + ncr_offb(o)) ! 572: #define OUTB_OFF(o, val) writeb((val), (char *)np->reg + ncr_offb(o)) ! 573: ! 574: #if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN) ! 575: ! 576: #define INW_OFF(o) readw_l2b((char *)np->reg + ncr_offw(o)) ! 577: #define INL_OFF(o) readl_l2b((char *)np->reg + (o)) ! 578: ! 579: #define OUTW_OFF(o, val) writew_b2l((val), (char *)np->reg + ncr_offw(o)) ! 580: #define OUTL_OFF(o, val) writel_b2l((val), (char *)np->reg + (o)) ! 581: ! 582: #elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN) ! 583: ! 584: #define INW_OFF(o) readw_b2l((char *)np->reg + ncr_offw(o)) ! 585: #define INL_OFF(o) readl_b2l((char *)np->reg + (o)) ! 586: ! 587: #define OUTW_OFF(o, val) writew_l2b((val), (char *)np->reg + ncr_offw(o)) ! 588: #define OUTL_OFF(o, val) writel_l2b((val), (char *)np->reg + (o)) ! 589: ! 590: #else ! 591: ! 592: #define INW_OFF(o) readw_raw((char *)np->reg + ncr_offw(o)) ! 593: #define INL_OFF(o) readl_raw((char *)np->reg + (o)) ! 594: ! 595: #define OUTW_OFF(o, val) writew_raw((val), (char *)np->reg + ncr_offw(o)) ! 596: #define OUTL_OFF(o, val) writel_raw((val), (char *)np->reg + (o)) ! 597: ! 598: #endif ! 599: ! 600: #endif /* defined SCSI_NCR_IOMAPPED */ ! 601: ! 602: #define INB(r) INB_OFF (offsetof(struct ncr_reg,r)) ! 603: #define INW(r) INW_OFF (offsetof(struct ncr_reg,r)) ! 604: #define INL(r) INL_OFF (offsetof(struct ncr_reg,r)) ! 605: ! 606: #define OUTB(r, val) OUTB_OFF (offsetof(struct ncr_reg,r), (val)) ! 607: #define OUTW(r, val) OUTW_OFF (offsetof(struct ncr_reg,r), (val)) ! 608: #define OUTL(r, val) OUTL_OFF (offsetof(struct ncr_reg,r), (val)) ! 609: ! 610: /* ! 611: * Set bit field ON, OFF ! 612: */ ! 613: ! 614: #define OUTONB(r, m) OUTB(r, INB(r) | (m)) ! 615: #define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m)) ! 616: #define OUTONW(r, m) OUTW(r, INW(r) | (m)) ! 617: #define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m)) ! 618: #define OUTONL(r, m) OUTL(r, INL(r) | (m)) ! 619: #define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m)) ! 620: ! 621: /* ! 622: * We normally want the chip to have a consistent view ! 623: * of driver internal data structures when we restart it. ! 624: * Thus these macros. ! 625: */ ! 626: #define OUTL_DSP(v) \ ! 627: do { \ ! 628: MEMORY_BARRIER(); \ ! 629: OUTL (nc_dsp, (v)); \ ! 630: } while (0) ! 631: ! 632: #define OUTONB_STD() \ ! 633: do { \ ! 634: MEMORY_BARRIER(); \ ! 635: OUTONB (nc_dcntl, (STD|NOCOM)); \ ! 636: } while (0) ! 637: ! 638: ! 639: /* ! 640: ** NCR53C8XX Device Ids ! 641: */ ! 642: ! 643: #ifndef PCI_DEVICE_ID_NCR_53C810 ! 644: #define PCI_DEVICE_ID_NCR_53C810 1 ! 645: #endif ! 646: ! 647: #ifndef PCI_DEVICE_ID_NCR_53C810AP ! 648: #define PCI_DEVICE_ID_NCR_53C810AP 5 ! 649: #endif ! 650: ! 651: #ifndef PCI_DEVICE_ID_NCR_53C815 ! 652: #define PCI_DEVICE_ID_NCR_53C815 4 ! 653: #endif ! 654: ! 655: #ifndef PCI_DEVICE_ID_NCR_53C820 ! 656: #define PCI_DEVICE_ID_NCR_53C820 2 ! 657: #endif ! 658: ! 659: #ifndef PCI_DEVICE_ID_NCR_53C825 ! 660: #define PCI_DEVICE_ID_NCR_53C825 3 ! 661: #endif ! 662: ! 663: #ifndef PCI_DEVICE_ID_NCR_53C860 ! 664: #define PCI_DEVICE_ID_NCR_53C860 6 ! 665: #endif ! 666: ! 667: #ifndef PCI_DEVICE_ID_NCR_53C875 ! 668: #define PCI_DEVICE_ID_NCR_53C875 0xf ! 669: #endif ! 670: ! 671: #ifndef PCI_DEVICE_ID_NCR_53C875J ! 672: #define PCI_DEVICE_ID_NCR_53C875J 0x8f ! 673: #endif ! 674: ! 675: #ifndef PCI_DEVICE_ID_NCR_53C885 ! 676: #define PCI_DEVICE_ID_NCR_53C885 0xd ! 677: #endif ! 678: ! 679: #ifndef PCI_DEVICE_ID_NCR_53C895 ! 680: #define PCI_DEVICE_ID_NCR_53C895 0xc ! 681: #endif ! 682: ! 683: #ifndef PCI_DEVICE_ID_NCR_53C896 ! 684: #define PCI_DEVICE_ID_NCR_53C896 0xb ! 685: #endif ! 686: ! 687: #ifndef PCI_DEVICE_ID_NCR_53C895A ! 688: #define PCI_DEVICE_ID_NCR_53C895A 0x12 ! 689: #endif ! 690: ! 691: #ifndef PCI_DEVICE_ID_NCR_53C1510D ! 692: #define PCI_DEVICE_ID_NCR_53C1510D 0xa ! 693: #endif ! 694: ! 695: #ifndef PCI_DEVICE_ID_LSI_53C1010 ! 696: #define PCI_DEVICE_ID_LSI_53C1010 0x20 ! 697: #endif ! 698: ! 699: #ifndef PCI_DEVICE_ID_LSI_53C1010_66 ! 700: #define PCI_DEVICE_ID_LSI_53C1010_66 0x21 ! 701: #endif ! 702: ! 703: ! 704: /* ! 705: ** NCR53C8XX devices features table. ! 706: */ ! 707: typedef struct { ! 708: unsigned short device_id; ! 709: unsigned short revision_id; ! 710: char *name; ! 711: unsigned char burst_max; /* log-base-2 of max burst */ ! 712: unsigned char offset_max; ! 713: unsigned char nr_divisor; ! 714: unsigned int features; ! 715: #define FE_LED0 (1<<0) ! 716: #define FE_WIDE (1<<1) /* Wide data transfers */ ! 717: #define FE_ULTRA (1<<2) /* Ultra speed 20Mtrans/sec */ ! 718: #define FE_ULTRA2 (1<<3) /* Ultra 2 - 40 Mtrans/sec */ ! 719: #define FE_DBLR (1<<4) /* Clock doubler present */ ! 720: #define FE_QUAD (1<<5) /* Clock quadrupler present */ ! 721: #define FE_ERL (1<<6) /* Enable read line */ ! 722: #define FE_CLSE (1<<7) /* Cache line size enable */ ! 723: #define FE_WRIE (1<<8) /* Write & Invalidate enable */ ! 724: #define FE_ERMP (1<<9) /* Enable read multiple */ ! 725: #define FE_BOF (1<<10) /* Burst opcode fetch */ ! 726: #define FE_DFS (1<<11) /* DMA fifo size */ ! 727: #define FE_PFEN (1<<12) /* Prefetch enable */ ! 728: #define FE_LDSTR (1<<13) /* Load/Store supported */ ! 729: #define FE_RAM (1<<14) /* On chip RAM present */ ! 730: #define FE_CLK80 (1<<15) /* Board clock is 80 MHz */ ! 731: #define FE_RAM8K (1<<16) /* On chip RAM sized 8Kb */ ! 732: #define FE_64BIT (1<<17) /* Supports 64-bit addressing */ ! 733: #define FE_IO256 (1<<18) /* Requires full 256 bytes in PCI space */ ! 734: #define FE_NOPM (1<<19) /* Scripts handles phase mismatch */ ! 735: #define FE_LEDC (1<<20) /* Hardware control of LED */ ! 736: #define FE_DIFF (1<<21) /* Support Differential SCSI */ ! 737: #define FE_ULTRA3 (1<<22) /* Ultra-3 80Mtrans/sec */ ! 738: #define FE_66MHZ (1<<23) /* 66MHz PCI Support */ ! 739: ! 740: #define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP) ! 741: #define FE_SCSI_SET (FE_WIDE|FE_ULTRA|FE_ULTRA2|FE_DBLR|FE_QUAD|F_CLK80) ! 742: #define FE_SPECIAL_SET (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM) ! 743: } ncr_chip; ! 744: ! 745: /* ! 746: ** DEL 397 - 53C875 Rev 3 - Part Number 609-0392410 - ITEM 3. ! 747: ** Memory Read transaction terminated by a retry followed by ! 748: ** Memory Read Line command. ! 749: */ ! 750: #define FE_CACHE0_SET (FE_CACHE_SET & ~FE_ERL) ! 751: ! 752: /* ! 753: ** DEL 397 - 53C875 Rev 3 - Part Number 609-0392410 - ITEM 5. ! 754: ** On paper, this errata is harmless. But it is a good reason for ! 755: ** using a shorter programmed burst length (64 DWORDS instead of 128). ! 756: */ ! 757: ! 758: #define SCSI_NCR_CHIP_TABLE \ ! 759: { \ ! 760: {PCI_DEVICE_ID_NCR_53C810, 0x0f, "810", 4, 8, 4, \ ! 761: FE_ERL} \ ! 762: , \ ! 763: {PCI_DEVICE_ID_NCR_53C810, 0xff, "810a", 4, 8, 4, \ ! 764: FE_CACHE_SET|FE_LDSTR|FE_PFEN|FE_BOF} \ ! 765: , \ ! 766: {PCI_DEVICE_ID_NCR_53C815, 0xff, "815", 4, 8, 4, \ ! 767: FE_ERL|FE_BOF} \ ! 768: , \ ! 769: {PCI_DEVICE_ID_NCR_53C820, 0xff, "820", 4, 8, 4, \ ! 770: FE_WIDE|FE_ERL} \ ! 771: , \ ! 772: {PCI_DEVICE_ID_NCR_53C825, 0x0f, "825", 4, 8, 4, \ ! 773: FE_WIDE|FE_ERL|FE_BOF|FE_DIFF} \ ! 774: , \ ! 775: {PCI_DEVICE_ID_NCR_53C825, 0xff, "825a", 6, 8, 4, \ ! 776: FE_WIDE|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM|FE_DIFF} \ ! 777: , \ ! 778: {PCI_DEVICE_ID_NCR_53C860, 0xff, "860", 4, 8, 5, \ ! 779: FE_ULTRA|FE_CLK80|FE_CACHE_SET|FE_BOF|FE_LDSTR|FE_PFEN} \ ! 780: , \ ! 781: {PCI_DEVICE_ID_NCR_53C875, 0x01, "875", 6, 16, 5, \ ! 782: FE_WIDE|FE_ULTRA|FE_CLK80|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|\ ! 783: FE_RAM|FE_DIFF} \ ! 784: , \ ! 785: {PCI_DEVICE_ID_NCR_53C875, 0x0f, "875", 6, 16, 5, \ ! 786: FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \ ! 787: FE_RAM|FE_DIFF} \ ! 788: , \ ! 789: {PCI_DEVICE_ID_NCR_53C875, 0x1f, "876", 6, 16, 5, \ ! 790: FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \ ! 791: FE_RAM|FE_DIFF} \ ! 792: , \ ! 793: {PCI_DEVICE_ID_NCR_53C875, 0x2f, "875E", 6, 16, 5, \ ! 794: FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \ ! 795: FE_RAM|FE_DIFF} \ ! 796: , \ ! 797: {PCI_DEVICE_ID_NCR_53C875, 0xff, "876", 6, 16, 5, \ ! 798: FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \ ! 799: FE_RAM|FE_DIFF} \ ! 800: , \ ! 801: {PCI_DEVICE_ID_NCR_53C875J,0xff, "875J", 6, 16, 5, \ ! 802: FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \ ! 803: FE_RAM} \ ! 804: , \ ! 805: {PCI_DEVICE_ID_NCR_53C885, 0xff, "885", 6, 16, 5, \ ! 806: FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \ ! 807: FE_RAM|FE_DIFF} \ ! 808: , \ ! 809: {PCI_DEVICE_ID_NCR_53C895, 0xff, "895", 6, 31, 7, \ ! 810: FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \ ! 811: FE_RAM} \ ! 812: , \ ! 813: {PCI_DEVICE_ID_NCR_53C896, 0xff, "896", 6, 31, 7, \ ! 814: FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \ ! 815: FE_RAM|FE_RAM8K|FE_64BIT|FE_IO256|FE_NOPM|FE_LEDC} \ ! 816: , \ ! 817: {PCI_DEVICE_ID_NCR_53C895A, 0xff, "895a", 6, 31, 7, \ ! 818: FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \ ! 819: FE_RAM|FE_RAM8K|FE_64BIT|FE_IO256|FE_NOPM|FE_LEDC} \ ! 820: , \ ! 821: {PCI_DEVICE_ID_NCR_53C1510D, 0xff, "1510D", 7, 31, 7, \ ! 822: FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \ ! 823: FE_RAM|FE_IO256} \ ! 824: , \ ! 825: {PCI_DEVICE_ID_LSI_53C1010, 0xff, "1010", 6, 31, 7, \ ! 826: FE_WIDE|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \ ! 827: FE_RAM|FE_RAM8K|FE_64BIT|FE_IO256|FE_NOPM|FE_LEDC|FE_ULTRA3} \ ! 828: , \ ! 829: {PCI_DEVICE_ID_LSI_53C1010_66, 0xff, "1010_66", 6, 31, 7, \ ! 830: FE_WIDE|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \ ! 831: FE_RAM|FE_RAM8K|FE_64BIT|FE_IO256|FE_NOPM|FE_LEDC|FE_ULTRA3|FE_66MHZ} \ ! 832: } ! 833: ! 834: /* ! 835: * List of supported NCR chip ids ! 836: */ ! 837: #define SCSI_NCR_CHIP_IDS \ ! 838: { \ ! 839: PCI_DEVICE_ID_NCR_53C810, \ ! 840: PCI_DEVICE_ID_NCR_53C815, \ ! 841: PCI_DEVICE_ID_NCR_53C820, \ ! 842: PCI_DEVICE_ID_NCR_53C825, \ ! 843: PCI_DEVICE_ID_NCR_53C860, \ ! 844: PCI_DEVICE_ID_NCR_53C875, \ ! 845: PCI_DEVICE_ID_NCR_53C875J, \ ! 846: PCI_DEVICE_ID_NCR_53C885, \ ! 847: PCI_DEVICE_ID_NCR_53C895, \ ! 848: PCI_DEVICE_ID_NCR_53C896, \ ! 849: PCI_DEVICE_ID_NCR_53C895A, \ ! 850: PCI_DEVICE_ID_NCR_53C1510D, \ ! 851: PCI_DEVICE_ID_LSI_53C1010, \ ! 852: PCI_DEVICE_ID_LSI_53C1010_66 \ ! 853: } ! 854: ! 855: /* ! 856: ** Driver setup structure. ! 857: ** ! 858: ** This structure is initialized from linux config options. ! 859: ** It can be overridden at boot-up by the boot command line. ! 860: */ ! 861: #define SCSI_NCR_MAX_EXCLUDES 8 ! 862: struct ncr_driver_setup { ! 863: u_char master_parity; ! 864: u_char scsi_parity; ! 865: u_char disconnection; ! 866: u_char special_features; ! 867: u_char ultra_scsi; ! 868: u_char force_sync_nego; ! 869: u_char reverse_probe; ! 870: u_char pci_fix_up; ! 871: u_char use_nvram; ! 872: u_char verbose; ! 873: u_char default_tags; ! 874: u_short default_sync; ! 875: u_short debug; ! 876: u_char burst_max; ! 877: u_char led_pin; ! 878: u_char max_wide; ! 879: u_char settle_delay; ! 880: u_char diff_support; ! 881: u_char irqm; ! 882: u_char bus_check; ! 883: u_char optimize; ! 884: u_char recovery; ! 885: u_char host_id; ! 886: u_short iarb; ! 887: u_long excludes[SCSI_NCR_MAX_EXCLUDES]; ! 888: char tag_ctrl[100]; ! 889: }; ! 890: ! 891: /* ! 892: ** Initial setup. ! 893: ** Can be overriden at startup by a command line. ! 894: */ ! 895: #define SCSI_NCR_DRIVER_SETUP \ ! 896: { \ ! 897: SCSI_NCR_SETUP_MASTER_PARITY, \ ! 898: SCSI_NCR_SETUP_SCSI_PARITY, \ ! 899: SCSI_NCR_SETUP_DISCONNECTION, \ ! 900: SCSI_NCR_SETUP_SPECIAL_FEATURES, \ ! 901: SCSI_NCR_SETUP_ULTRA_SCSI, \ ! 902: SCSI_NCR_SETUP_FORCE_SYNC_NEGO, \ ! 903: 0, \ ! 904: 0, \ ! 905: 1, \ ! 906: 0, \ ! 907: SCSI_NCR_SETUP_DEFAULT_TAGS, \ ! 908: SCSI_NCR_SETUP_DEFAULT_SYNC, \ ! 909: 0x00, \ ! 910: 7, \ ! 911: SCSI_NCR_SETUP_LED_PIN, \ ! 912: 1, \ ! 913: SCSI_NCR_SETUP_SETTLE_TIME, \ ! 914: SCSI_NCR_SETUP_DIFF_SUPPORT, \ ! 915: 0, \ ! 916: 1, \ ! 917: 0, \ ! 918: 0, \ ! 919: 255, \ ! 920: 0x00 \ ! 921: } ! 922: ! 923: /* ! 924: ** Boot fail safe setup. ! 925: ** Override initial setup from boot command line: ! 926: ** ncr53c8xx=safe:y ! 927: */ ! 928: #define SCSI_NCR_DRIVER_SAFE_SETUP \ ! 929: { \ ! 930: 0, \ ! 931: 1, \ ! 932: 0, \ ! 933: 0, \ ! 934: 0, \ ! 935: 0, \ ! 936: 0, \ ! 937: 0, \ ! 938: 1, \ ! 939: 2, \ ! 940: 0, \ ! 941: 255, \ ! 942: 0x00, \ ! 943: 255, \ ! 944: 0, \ ! 945: 0, \ ! 946: 10, \ ! 947: 1, \ ! 948: 1, \ ! 949: 1, \ ! 950: 0, \ ! 951: 0, \ ! 952: 255 \ ! 953: } ! 954: ! 955: #ifdef SCSI_NCR_NVRAM_SUPPORT ! 956: /* ! 957: ** Symbios NvRAM data format ! 958: */ ! 959: #define SYMBIOS_NVRAM_SIZE 368 ! 960: #define SYMBIOS_NVRAM_ADDRESS 0x100 ! 961: ! 962: struct Symbios_nvram { ! 963: /* Header 6 bytes */ ! 964: u_short type; /* 0x0000 */ ! 965: u_short byte_count; /* excluding header/trailer */ ! 966: u_short checksum; ! 967: ! 968: /* Controller set up 20 bytes */ ! 969: u_char v_major; /* 0x00 */ ! 970: u_char v_minor; /* 0x30 */ ! 971: u_int32 boot_crc; ! 972: u_short flags; ! 973: #define SYMBIOS_SCAM_ENABLE (1) ! 974: #define SYMBIOS_PARITY_ENABLE (1<<1) ! 975: #define SYMBIOS_VERBOSE_MSGS (1<<2) ! 976: #define SYMBIOS_CHS_MAPPING (1<<3) ! 977: #define SYMBIOS_NO_NVRAM (1<<3) /* ??? */ ! 978: u_short flags1; ! 979: #define SYMBIOS_SCAN_HI_LO (1) ! 980: u_short term_state; ! 981: #define SYMBIOS_TERM_CANT_PROGRAM (0) ! 982: #define SYMBIOS_TERM_ENABLED (1) ! 983: #define SYMBIOS_TERM_DISABLED (2) ! 984: u_short rmvbl_flags; ! 985: #define SYMBIOS_RMVBL_NO_SUPPORT (0) ! 986: #define SYMBIOS_RMVBL_BOOT_DEVICE (1) ! 987: #define SYMBIOS_RMVBL_MEDIA_INSTALLED (2) ! 988: u_char host_id; ! 989: u_char num_hba; /* 0x04 */ ! 990: u_char num_devices; /* 0x10 */ ! 991: u_char max_scam_devices; /* 0x04 */ ! 992: u_char num_valid_scam_devives; /* 0x00 */ ! 993: u_char rsvd; ! 994: ! 995: /* Boot order 14 bytes * 4 */ ! 996: struct Symbios_host{ ! 997: u_short type; /* 4:8xx / 0:nok */ ! 998: u_short device_id; /* PCI device id */ ! 999: u_short vendor_id; /* PCI vendor id */ ! 1000: u_char bus_nr; /* PCI bus number */ ! 1001: u_char device_fn; /* PCI device/function number << 3*/ ! 1002: u_short word8; ! 1003: u_short flags; ! 1004: #define SYMBIOS_INIT_SCAN_AT_BOOT (1) ! 1005: u_short io_port; /* PCI io_port address */ ! 1006: } host[4]; ! 1007: ! 1008: /* Targets 8 bytes * 16 */ ! 1009: struct Symbios_target { ! 1010: u_char flags; ! 1011: #define SYMBIOS_DISCONNECT_ENABLE (1) ! 1012: #define SYMBIOS_SCAN_AT_BOOT_TIME (1<<1) ! 1013: #define SYMBIOS_SCAN_LUNS (1<<2) ! 1014: #define SYMBIOS_QUEUE_TAGS_ENABLED (1<<3) ! 1015: u_char rsvd; ! 1016: u_char bus_width; /* 0x08/0x10 */ ! 1017: u_char sync_offset; ! 1018: u_short sync_period; /* 4*period factor */ ! 1019: u_short timeout; ! 1020: } target[16]; ! 1021: /* Scam table 8 bytes * 4 */ ! 1022: struct Symbios_scam { ! 1023: u_short id; ! 1024: u_short method; ! 1025: #define SYMBIOS_SCAM_DEFAULT_METHOD (0) ! 1026: #define SYMBIOS_SCAM_DONT_ASSIGN (1) ! 1027: #define SYMBIOS_SCAM_SET_SPECIFIC_ID (2) ! 1028: #define SYMBIOS_SCAM_USE_ORDER_GIVEN (3) ! 1029: u_short status; ! 1030: #define SYMBIOS_SCAM_UNKNOWN (0) ! 1031: #define SYMBIOS_SCAM_DEVICE_NOT_FOUND (1) ! 1032: #define SYMBIOS_SCAM_ID_NOT_SET (2) ! 1033: #define SYMBIOS_SCAM_ID_VALID (3) ! 1034: u_char target_id; ! 1035: u_char rsvd; ! 1036: } scam[4]; ! 1037: ! 1038: u_char spare_devices[15*8]; ! 1039: u_char trailer[6]; /* 0xfe 0xfe 0x00 0x00 0x00 0x00 */ ! 1040: }; ! 1041: typedef struct Symbios_nvram Symbios_nvram; ! 1042: typedef struct Symbios_host Symbios_host; ! 1043: typedef struct Symbios_target Symbios_target; ! 1044: typedef struct Symbios_scam Symbios_scam; ! 1045: ! 1046: /* ! 1047: ** Tekram NvRAM data format. ! 1048: */ ! 1049: #define TEKRAM_NVRAM_SIZE 64 ! 1050: #define TEKRAM_93C46_NVRAM_ADDRESS 0 ! 1051: #define TEKRAM_24C16_NVRAM_ADDRESS 0x40 ! 1052: ! 1053: struct Tekram_nvram { ! 1054: struct Tekram_target { ! 1055: u_char flags; ! 1056: #define TEKRAM_PARITY_CHECK (1) ! 1057: #define TEKRAM_SYNC_NEGO (1<<1) ! 1058: #define TEKRAM_DISCONNECT_ENABLE (1<<2) ! 1059: #define TEKRAM_START_CMD (1<<3) ! 1060: #define TEKRAM_TAGGED_COMMANDS (1<<4) ! 1061: #define TEKRAM_WIDE_NEGO (1<<5) ! 1062: u_char sync_index; ! 1063: u_short word2; ! 1064: } target[16]; ! 1065: u_char host_id; ! 1066: u_char flags; ! 1067: #define TEKRAM_MORE_THAN_2_DRIVES (1) ! 1068: #define TEKRAM_DRIVES_SUP_1GB (1<<1) ! 1069: #define TEKRAM_RESET_ON_POWER_ON (1<<2) ! 1070: #define TEKRAM_ACTIVE_NEGATION (1<<3) ! 1071: #define TEKRAM_IMMEDIATE_SEEK (1<<4) ! 1072: #define TEKRAM_SCAN_LUNS (1<<5) ! 1073: #define TEKRAM_REMOVABLE_FLAGS (3<<6) /* 0: disable; 1: boot device; 2:all */ ! 1074: u_char boot_delay_index; ! 1075: u_char max_tags_index; ! 1076: u_short flags1; ! 1077: #define TEKRAM_F2_F6_ENABLED (1) ! 1078: u_short spare[29]; ! 1079: }; ! 1080: typedef struct Tekram_nvram Tekram_nvram; ! 1081: typedef struct Tekram_target Tekram_target; ! 1082: ! 1083: #endif /* SCSI_NCR_NVRAM_SUPPORT */ ! 1084: ! 1085: /**************** ORIGINAL CONTENT of ncrreg.h from FreeBSD ******************/ ! 1086: ! 1087: /*----------------------------------------------------------------- ! 1088: ** ! 1089: ** The ncr 53c810 register structure. ! 1090: ** ! 1091: **----------------------------------------------------------------- ! 1092: */ ! 1093: ! 1094: struct ncr_reg { ! 1095: /*00*/ u_char nc_scntl0; /* full arb., ena parity, par->ATN */ ! 1096: ! 1097: /*01*/ u_char nc_scntl1; /* no reset */ ! 1098: #define ISCON 0x10 /* connected to scsi */ ! 1099: #define CRST 0x08 /* force reset */ ! 1100: #define IARB 0x02 /* immediate arbitration */ ! 1101: ! 1102: /*02*/ u_char nc_scntl2; /* no disconnect expected */ ! 1103: #define SDU 0x80 /* cmd: disconnect will raise error */ ! 1104: #define CHM 0x40 /* sta: chained mode */ ! 1105: #define WSS 0x08 /* sta: wide scsi send [W]*/ ! 1106: #define WSR 0x01 /* sta: wide scsi received [W]*/ ! 1107: ! 1108: /*03*/ u_char nc_scntl3; /* cnf system clock dependent */ ! 1109: #define EWS 0x08 /* cmd: enable wide scsi [W]*/ ! 1110: #define ULTRA 0x80 /* cmd: ULTRA enable */ ! 1111: /* bits 0-2, 7 rsvd for C1010 */ ! 1112: ! 1113: /*04*/ u_char nc_scid; /* cnf host adapter scsi address */ ! 1114: #define RRE 0x40 /* r/w:e enable response to resel. */ ! 1115: #define SRE 0x20 /* r/w:e enable response to select */ ! 1116: ! 1117: /*05*/ u_char nc_sxfer; /* ### Sync speed and count */ ! 1118: /* bits 6-7 rsvd for C1010 */ ! 1119: ! 1120: /*06*/ u_char nc_sdid; /* ### Destination-ID */ ! 1121: ! 1122: /*07*/ u_char nc_gpreg; /* ??? IO-Pins */ ! 1123: ! 1124: /*08*/ u_char nc_sfbr; /* ### First byte in phase */ ! 1125: ! 1126: /*09*/ u_char nc_socl; ! 1127: #define CREQ 0x80 /* r/w: SCSI-REQ */ ! 1128: #define CACK 0x40 /* r/w: SCSI-ACK */ ! 1129: #define CBSY 0x20 /* r/w: SCSI-BSY */ ! 1130: #define CSEL 0x10 /* r/w: SCSI-SEL */ ! 1131: #define CATN 0x08 /* r/w: SCSI-ATN */ ! 1132: #define CMSG 0x04 /* r/w: SCSI-MSG */ ! 1133: #define CC_D 0x02 /* r/w: SCSI-C_D */ ! 1134: #define CI_O 0x01 /* r/w: SCSI-I_O */ ! 1135: ! 1136: /*0a*/ u_char nc_ssid; ! 1137: ! 1138: /*0b*/ u_char nc_sbcl; ! 1139: ! 1140: /*0c*/ u_char nc_dstat; ! 1141: #define DFE 0x80 /* sta: dma fifo empty */ ! 1142: #define MDPE 0x40 /* int: master data parity error */ ! 1143: #define BF 0x20 /* int: script: bus fault */ ! 1144: #define ABRT 0x10 /* int: script: command aborted */ ! 1145: #define SSI 0x08 /* int: script: single step */ ! 1146: #define SIR 0x04 /* int: script: interrupt instruct. */ ! 1147: #define IID 0x01 /* int: script: illegal instruct. */ ! 1148: ! 1149: /*0d*/ u_char nc_sstat0; ! 1150: #define ILF 0x80 /* sta: data in SIDL register lsb */ ! 1151: #define ORF 0x40 /* sta: data in SODR register lsb */ ! 1152: #define OLF 0x20 /* sta: data in SODL register lsb */ ! 1153: #define AIP 0x10 /* sta: arbitration in progress */ ! 1154: #define LOA 0x08 /* sta: arbitration lost */ ! 1155: #define WOA 0x04 /* sta: arbitration won */ ! 1156: #define IRST 0x02 /* sta: scsi reset signal */ ! 1157: #define SDP 0x01 /* sta: scsi parity signal */ ! 1158: ! 1159: /*0e*/ u_char nc_sstat1; ! 1160: #define FF3210 0xf0 /* sta: bytes in the scsi fifo */ ! 1161: ! 1162: /*0f*/ u_char nc_sstat2; ! 1163: #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/ ! 1164: #define ORF1 0x40 /* sta: data in SODR register msb[W]*/ ! 1165: #define OLF1 0x20 /* sta: data in SODL register msb[W]*/ ! 1166: #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */ ! 1167: #define LDSC 0x02 /* sta: disconnect & reconnect */ ! 1168: ! 1169: /*10*/ u_char nc_dsa; /* --> Base page */ ! 1170: /*11*/ u_char nc_dsa1; ! 1171: /*12*/ u_char nc_dsa2; ! 1172: /*13*/ u_char nc_dsa3; ! 1173: ! 1174: /*14*/ u_char nc_istat; /* --> Main Command and status */ ! 1175: #define CABRT 0x80 /* cmd: abort current operation */ ! 1176: #define SRST 0x40 /* mod: reset chip */ ! 1177: #define SIGP 0x20 /* r/w: message from host to ncr */ ! 1178: #define SEM 0x10 /* r/w: message between host + ncr */ ! 1179: #define CON 0x08 /* sta: connected to scsi */ ! 1180: #define INTF 0x04 /* sta: int on the fly (reset by wr)*/ ! 1181: #define SIP 0x02 /* sta: scsi-interrupt */ ! 1182: #define DIP 0x01 /* sta: host/script interrupt */ ! 1183: ! 1184: /*15*/ u_char nc_istat1; /* 896 only */ ! 1185: /*16*/ u_char nc_mbox0; /* 896 only */ ! 1186: /*17*/ u_char nc_mbox1; /* 896 only */ ! 1187: ! 1188: /*18*/ u_char nc_ctest0; ! 1189: /*19*/ u_char nc_ctest1; ! 1190: ! 1191: /*1a*/ u_char nc_ctest2; ! 1192: #define CSIGP 0x40 ! 1193: /* bits 0-2,7 rsvd for C1010 */ ! 1194: ! 1195: /*1b*/ u_char nc_ctest3; ! 1196: #define FLF 0x08 /* cmd: flush dma fifo */ ! 1197: #define CLF 0x04 /* cmd: clear dma fifo */ ! 1198: #define FM 0x02 /* mod: fetch pin mode */ ! 1199: #define WRIE 0x01 /* mod: write and invalidate enable */ ! 1200: /* bits 4-7 rsvd for C1010 */ ! 1201: ! 1202: /*1c*/ u_int32 nc_temp; /* ### Temporary stack */ ! 1203: ! 1204: /*20*/ u_char nc_dfifo; ! 1205: /*21*/ u_char nc_ctest4; ! 1206: #define BDIS 0x80 /* mod: burst disable */ ! 1207: #define MPEE 0x08 /* mod: master parity error enable */ ! 1208: ! 1209: /*22*/ u_char nc_ctest5; ! 1210: #define DFS 0x20 /* mod: dma fifo size */ ! 1211: /* bits 0-1, 3-7 rsvd for C1010 */ ! 1212: /*23*/ u_char nc_ctest6; ! 1213: ! 1214: /*24*/ u_int32 nc_dbc; /* ### Byte count and command */ ! 1215: /*28*/ u_int32 nc_dnad; /* ### Next command register */ ! 1216: /*2c*/ u_int32 nc_dsp; /* --> Script Pointer */ ! 1217: /*30*/ u_int32 nc_dsps; /* --> Script pointer save/opcode#2 */ ! 1218: ! 1219: /*34*/ u_char nc_scratcha; /* Temporary register a */ ! 1220: /*35*/ u_char nc_scratcha1; ! 1221: /*36*/ u_char nc_scratcha2; ! 1222: /*37*/ u_char nc_scratcha3; ! 1223: ! 1224: /*38*/ u_char nc_dmode; ! 1225: #define BL_2 0x80 /* mod: burst length shift value +2 */ ! 1226: #define BL_1 0x40 /* mod: burst length shift value +1 */ ! 1227: #define ERL 0x08 /* mod: enable read line */ ! 1228: #define ERMP 0x04 /* mod: enable read multiple */ ! 1229: #define BOF 0x02 /* mod: burst op code fetch */ ! 1230: ! 1231: /*39*/ u_char nc_dien; ! 1232: /*3a*/ u_char nc_sbr; ! 1233: ! 1234: /*3b*/ u_char nc_dcntl; /* --> Script execution control */ ! 1235: #define CLSE 0x80 /* mod: cache line size enable */ ! 1236: #define PFF 0x40 /* cmd: pre-fetch flush */ ! 1237: #define PFEN 0x20 /* mod: pre-fetch enable */ ! 1238: #define SSM 0x10 /* mod: single step mode */ ! 1239: #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */ ! 1240: #define STD 0x04 /* cmd: start dma mode */ ! 1241: #define IRQD 0x02 /* mod: irq disable */ ! 1242: #define NOCOM 0x01 /* cmd: protect sfbr while reselect */ ! 1243: /* bits 0-1 rsvd for C1010 */ ! 1244: ! 1245: /*3c*/ u_int32 nc_adder; ! 1246: ! 1247: /*40*/ u_short nc_sien; /* -->: interrupt enable */ ! 1248: /*42*/ u_short nc_sist; /* <--: interrupt status */ ! 1249: #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */ ! 1250: #define STO 0x0400/* sta: timeout (select) */ ! 1251: #define GEN 0x0200/* sta: timeout (general) */ ! 1252: #define HTH 0x0100/* sta: timeout (handshake) */ ! 1253: #define MA 0x80 /* sta: phase mismatch */ ! 1254: #define CMP 0x40 /* sta: arbitration complete */ ! 1255: #define SEL 0x20 /* sta: selected by another device */ ! 1256: #define RSL 0x10 /* sta: reselected by another device*/ ! 1257: #define SGE 0x08 /* sta: gross error (over/underflow)*/ ! 1258: #define UDC 0x04 /* sta: unexpected disconnect */ ! 1259: #define RST 0x02 /* sta: scsi bus reset detected */ ! 1260: #define PAR 0x01 /* sta: scsi parity error */ ! 1261: ! 1262: /*44*/ u_char nc_slpar; ! 1263: /*45*/ u_char nc_swide; ! 1264: /*46*/ u_char nc_macntl; ! 1265: /*47*/ u_char nc_gpcntl; ! 1266: /*48*/ u_char nc_stime0; /* cmd: timeout for select&handshake*/ ! 1267: /*49*/ u_char nc_stime1; /* cmd: timeout user defined */ ! 1268: /*4a*/ u_short nc_respid; /* sta: Reselect-IDs */ ! 1269: ! 1270: /*4c*/ u_char nc_stest0; ! 1271: ! 1272: /*4d*/ u_char nc_stest1; ! 1273: #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ ! 1274: #define DBLEN 0x08 /* clock doubler running */ ! 1275: #define DBLSEL 0x04 /* clock doubler selected */ ! 1276: ! 1277: ! 1278: /*4e*/ u_char nc_stest2; ! 1279: #define ROF 0x40 /* reset scsi offset (after gross error!) */ ! 1280: #define EXT 0x02 /* extended filtering */ ! 1281: ! 1282: /*4f*/ u_char nc_stest3; ! 1283: #define TE 0x80 /* c: tolerAnt enable */ ! 1284: #define HSC 0x20 /* c: Halt SCSI Clock */ ! 1285: #define CSF 0x02 /* c: clear scsi fifo */ ! 1286: ! 1287: /*50*/ u_short nc_sidl; /* Lowlevel: latched from scsi data */ ! 1288: /*52*/ u_char nc_stest4; ! 1289: #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */ ! 1290: #define SMODE_HVD 0x40 /* High Voltage Differential */ ! 1291: #define SMODE_SE 0x80 /* Single Ended */ ! 1292: #define SMODE_LVD 0xc0 /* Low Voltage Differential */ ! 1293: #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */ ! 1294: /* bits 0-5 rsvd for C1010 */ ! 1295: ! 1296: /*53*/ u_char nc_53_; ! 1297: /*54*/ u_short nc_sodl; /* Lowlevel: data out to scsi data */ ! 1298: /*56*/ u_char nc_ccntl0; /* Chip Control 0 (896) */ ! 1299: #define ENPMJ 0x80 /* Enable Phase Mismatch Jump */ ! 1300: #define PMJCTL 0x40 /* Phase Mismatch Jump Control */ ! 1301: #define ENNDJ 0x20 /* Enable Non Data PM Jump */ ! 1302: #define DISFC 0x10 /* Disable Auto FIFO Clear */ ! 1303: #define DILS 0x02 /* Disable Internal Load/Store */ ! 1304: #define DPR 0x01 /* Disable Pipe Req */ ! 1305: ! 1306: /*57*/ u_char nc_ccntl1; /* Chip Control 1 (896) */ ! 1307: #define ZMOD 0x80 /* High Impedance Mode */ ! 1308: #define DIC 0x10 /* Disable Internal Cycles */ ! 1309: #define DDAC 0x08 /* Disable Dual Address Cycle */ ! 1310: #define XTIMOD 0x04 /* 64-bit Table Ind. Indexing Mode */ ! 1311: #define EXTIBMV 0x02 /* Enable 64-bit Table Ind. BMOV */ ! 1312: #define EXDBMV 0x01 /* Enable 64-bit Direct BMOV */ ! 1313: ! 1314: /*58*/ u_short nc_sbdl; /* Lowlevel: data from scsi data */ ! 1315: /*5a*/ u_short nc_5a_; ! 1316: ! 1317: /*5c*/ u_char nc_scr0; /* Working register B */ ! 1318: /*5d*/ u_char nc_scr1; /* */ ! 1319: /*5e*/ u_char nc_scr2; /* */ ! 1320: /*5f*/ u_char nc_scr3; /* */ ! 1321: ! 1322: /*60*/ u_char nc_scrx[64]; /* Working register C-R */ ! 1323: /*a0*/ u_int32 nc_mmrs; /* Memory Move Read Selector */ ! 1324: /*a4*/ u_int32 nc_mmws; /* Memory Move Write Selector */ ! 1325: /*a8*/ u_int32 nc_sfs; /* Script Fetch Selector */ ! 1326: /*ac*/ u_int32 nc_drs; /* DSA Relative Selector */ ! 1327: /*b0*/ u_int32 nc_sbms; /* Static Block Move Selector */ ! 1328: /*b4*/ u_int32 nc_dbms; /* Dynamic Block Move Selector */ ! 1329: /*b8*/ u_int32 nc_dnad64; /* DMA Next Address 64 */ ! 1330: /*bc*/ u_short nc_scntl4; /* C1010 only */ ! 1331: #define U3EN 0x80 /* Enable Ultra 3 */ ! 1332: #define AIPEN 0x40 /* Allow check upper byte lanes */ ! 1333: #define XCLKH_DT 0x08 /* Extra clock of data hold on DT ! 1334: transfer edge */ ! 1335: #define XCLKH_ST 0x04 /* Extra clock of data hold on ST ! 1336: transfer edge */ ! 1337: ! 1338: /*be*/ u_char nc_aipcntl0; /* Epat Control 1 C1010 only */ ! 1339: /*bf*/ u_char nc_aipcntl1; /* AIP Control C1010_66 Only */ ! 1340: ! 1341: /*c0*/ u_int32 nc_pmjad1; /* Phase Mismatch Jump Address 1 */ ! 1342: /*c4*/ u_int32 nc_pmjad2; /* Phase Mismatch Jump Address 2 */ ! 1343: /*c8*/ u_char nc_rbc; /* Remaining Byte Count */ ! 1344: /*c9*/ u_char nc_rbc1; /* */ ! 1345: /*ca*/ u_char nc_rbc2; /* */ ! 1346: /*cb*/ u_char nc_rbc3; /* */ ! 1347: ! 1348: /*cc*/ u_char nc_ua; /* Updated Address */ ! 1349: /*cd*/ u_char nc_ua1; /* */ ! 1350: /*ce*/ u_char nc_ua2; /* */ ! 1351: /*cf*/ u_char nc_ua3; /* */ ! 1352: /*d0*/ u_int32 nc_esa; /* Entry Storage Address */ ! 1353: /*d4*/ u_char nc_ia; /* Instruction Address */ ! 1354: /*d5*/ u_char nc_ia1; ! 1355: /*d6*/ u_char nc_ia2; ! 1356: /*d7*/ u_char nc_ia3; ! 1357: /*d8*/ u_int32 nc_sbc; /* SCSI Byte Count (3 bytes only) */ ! 1358: /*dc*/ u_int32 nc_csbc; /* Cumulative SCSI Byte Count */ ! 1359: ! 1360: /* Following for C1010 only */ ! 1361: /*e0*/ u_short nc_crcpad; /* CRC Value */ ! 1362: /*e2*/ u_char nc_crccntl0; /* CRC control register */ ! 1363: #define SNDCRC 0x10 /* Send CRC Request */ ! 1364: /*e3*/ u_char nc_crccntl1; /* CRC control register */ ! 1365: /*e4*/ u_int32 nc_crcdata; /* CRC data register */ ! 1366: /*e8*/ u_int32 nc_e8_; /* rsvd */ ! 1367: /*ec*/ u_int32 nc_ec_; /* rsvd */ ! 1368: /*f0*/ u_short nc_dfbc; /* DMA FIFO byte count */ ! 1369: ! 1370: }; ! 1371: ! 1372: /*----------------------------------------------------------- ! 1373: ** ! 1374: ** Utility macros for the script. ! 1375: ** ! 1376: **----------------------------------------------------------- ! 1377: */ ! 1378: ! 1379: #define REGJ(p,r) (offsetof(struct ncr_reg, p ## r)) ! 1380: #define REG(r) REGJ (nc_, r) ! 1381: ! 1382: typedef u_int32 ncrcmd; ! 1383: ! 1384: /*----------------------------------------------------------- ! 1385: ** ! 1386: ** SCSI phases ! 1387: ** ! 1388: ** DT phases illegal for ncr driver. ! 1389: ** ! 1390: **----------------------------------------------------------- ! 1391: */ ! 1392: ! 1393: #define SCR_DATA_OUT 0x00000000 ! 1394: #define SCR_DATA_IN 0x01000000 ! 1395: #define SCR_COMMAND 0x02000000 ! 1396: #define SCR_STATUS 0x03000000 ! 1397: #define SCR_DT_DATA_OUT 0x04000000 ! 1398: #define SCR_DT_DATA_IN 0x05000000 ! 1399: #define SCR_MSG_OUT 0x06000000 ! 1400: #define SCR_MSG_IN 0x07000000 ! 1401: ! 1402: #define SCR_ILG_OUT 0x04000000 ! 1403: #define SCR_ILG_IN 0x05000000 ! 1404: ! 1405: /*----------------------------------------------------------- ! 1406: ** ! 1407: ** Data transfer via SCSI. ! 1408: ** ! 1409: **----------------------------------------------------------- ! 1410: ** ! 1411: ** MOVE_ABS (LEN) ! 1412: ** <<start address>> ! 1413: ** ! 1414: ** MOVE_IND (LEN) ! 1415: ** <<dnad_offset>> ! 1416: ** ! 1417: ** MOVE_TBL ! 1418: ** <<dnad_offset>> ! 1419: ** ! 1420: **----------------------------------------------------------- ! 1421: */ ! 1422: ! 1423: #define OPC_MOVE 0x08000000 ! 1424: ! 1425: #define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l)) ! 1426: #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l)) ! 1427: #define SCR_MOVE_TBL (0x10000000 | OPC_MOVE) ! 1428: ! 1429: #define SCR_CHMOV_ABS(l) ((0x00000000) | (l)) ! 1430: #define SCR_CHMOV_IND(l) ((0x20000000) | (l)) ! 1431: #define SCR_CHMOV_TBL (0x10000000) ! 1432: ! 1433: struct scr_tblmove { ! 1434: u_int32 size; ! 1435: u_int32 addr; ! 1436: }; ! 1437: ! 1438: /*----------------------------------------------------------- ! 1439: ** ! 1440: ** Selection ! 1441: ** ! 1442: **----------------------------------------------------------- ! 1443: ** ! 1444: ** SEL_ABS | SCR_ID (0..15) [ | REL_JMP] ! 1445: ** <<alternate_address>> ! 1446: ** ! 1447: ** SEL_TBL | << dnad_offset>> [ | REL_JMP] ! 1448: ** <<alternate_address>> ! 1449: ** ! 1450: **----------------------------------------------------------- ! 1451: */ ! 1452: ! 1453: #define SCR_SEL_ABS 0x40000000 ! 1454: #define SCR_SEL_ABS_ATN 0x41000000 ! 1455: #define SCR_SEL_TBL 0x42000000 ! 1456: #define SCR_SEL_TBL_ATN 0x43000000 ! 1457: ! 1458: struct scr_tblsel { ! 1459: u_char sel_scntl4; ! 1460: u_char sel_sxfer; ! 1461: u_char sel_id; ! 1462: u_char sel_scntl3; ! 1463: }; ! 1464: ! 1465: #define SCR_JMP_REL 0x04000000 ! 1466: #define SCR_ID(id) (((u_int32)(id)) << 16) ! 1467: ! 1468: /*----------------------------------------------------------- ! 1469: ** ! 1470: ** Waiting for Disconnect or Reselect ! 1471: ** ! 1472: **----------------------------------------------------------- ! 1473: ** ! 1474: ** WAIT_DISC ! 1475: ** dummy: <<alternate_address>> ! 1476: ** ! 1477: ** WAIT_RESEL ! 1478: ** <<alternate_address>> ! 1479: ** ! 1480: **----------------------------------------------------------- ! 1481: */ ! 1482: ! 1483: #define SCR_WAIT_DISC 0x48000000 ! 1484: #define SCR_WAIT_RESEL 0x50000000 ! 1485: ! 1486: /*----------------------------------------------------------- ! 1487: ** ! 1488: ** Bit Set / Reset ! 1489: ** ! 1490: **----------------------------------------------------------- ! 1491: ** ! 1492: ** SET (flags {|.. }) ! 1493: ** ! 1494: ** CLR (flags {|.. }) ! 1495: ** ! 1496: **----------------------------------------------------------- ! 1497: */ ! 1498: ! 1499: #define SCR_SET(f) (0x58000000 | (f)) ! 1500: #define SCR_CLR(f) (0x60000000 | (f)) ! 1501: ! 1502: #define SCR_CARRY 0x00000400 ! 1503: #define SCR_TRG 0x00000200 ! 1504: #define SCR_ACK 0x00000040 ! 1505: #define SCR_ATN 0x00000008 ! 1506: ! 1507: ! 1508: ! 1509: ! 1510: /*----------------------------------------------------------- ! 1511: ** ! 1512: ** Memory to memory move ! 1513: ** ! 1514: **----------------------------------------------------------- ! 1515: ** ! 1516: ** COPY (bytecount) ! 1517: ** << source_address >> ! 1518: ** << destination_address >> ! 1519: ** ! 1520: ** SCR_COPY sets the NO FLUSH option by default. ! 1521: ** SCR_COPY_F does not set this option. ! 1522: ** ! 1523: ** For chips which do not support this option, ! 1524: ** ncr_copy_and_bind() will remove this bit. ! 1525: **----------------------------------------------------------- ! 1526: */ ! 1527: ! 1528: #define SCR_NO_FLUSH 0x01000000 ! 1529: ! 1530: #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n)) ! 1531: #define SCR_COPY_F(n) (0xc0000000 | (n)) ! 1532: ! 1533: /*----------------------------------------------------------- ! 1534: ** ! 1535: ** Register move and binary operations ! 1536: ** ! 1537: **----------------------------------------------------------- ! 1538: ** ! 1539: ** SFBR_REG (reg, op, data) reg = SFBR op data ! 1540: ** << 0 >> ! 1541: ** ! 1542: ** REG_SFBR (reg, op, data) SFBR = reg op data ! 1543: ** << 0 >> ! 1544: ** ! 1545: ** REG_REG (reg, op, data) reg = reg op data ! 1546: ** << 0 >> ! 1547: ** ! 1548: **----------------------------------------------------------- ! 1549: ** On 810A, 860, 825A, 875, 895 and 896 chips the content ! 1550: ** of SFBR register can be used as data (SCR_SFBR_DATA). ! 1551: ** The 896 has additionnal IO registers starting at ! 1552: ** offset 0x80. Bit 7 of register offset is stored in ! 1553: ** bit 7 of the SCRIPTS instruction first DWORD. ! 1554: **----------------------------------------------------------- ! 1555: */ ! 1556: ! 1557: #define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80)) ! 1558: ! 1559: #define SCR_SFBR_REG(reg,op,data) \ ! 1560: (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) ! 1561: ! 1562: #define SCR_REG_SFBR(reg,op,data) \ ! 1563: (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) ! 1564: ! 1565: #define SCR_REG_REG(reg,op,data) \ ! 1566: (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) ! 1567: ! 1568: ! 1569: #define SCR_LOAD 0x00000000 ! 1570: #define SCR_SHL 0x01000000 ! 1571: #define SCR_OR 0x02000000 ! 1572: #define SCR_XOR 0x03000000 ! 1573: #define SCR_AND 0x04000000 ! 1574: #define SCR_SHR 0x05000000 ! 1575: #define SCR_ADD 0x06000000 ! 1576: #define SCR_ADDC 0x07000000 ! 1577: ! 1578: #define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */ ! 1579: ! 1580: /*----------------------------------------------------------- ! 1581: ** ! 1582: ** FROM_REG (reg) SFBR = reg ! 1583: ** << 0 >> ! 1584: ** ! 1585: ** TO_REG (reg) reg = SFBR ! 1586: ** << 0 >> ! 1587: ** ! 1588: ** LOAD_REG (reg, data) reg = <data> ! 1589: ** << 0 >> ! 1590: ** ! 1591: ** LOAD_SFBR(data) SFBR = <data> ! 1592: ** << 0 >> ! 1593: ** ! 1594: **----------------------------------------------------------- ! 1595: */ ! 1596: ! 1597: #define SCR_FROM_REG(reg) \ ! 1598: SCR_REG_SFBR(reg,SCR_OR,0) ! 1599: ! 1600: #define SCR_TO_REG(reg) \ ! 1601: SCR_SFBR_REG(reg,SCR_OR,0) ! 1602: ! 1603: #define SCR_LOAD_REG(reg,data) \ ! 1604: SCR_REG_REG(reg,SCR_LOAD,data) ! 1605: ! 1606: #define SCR_LOAD_SFBR(data) \ ! 1607: (SCR_REG_SFBR (gpreg, SCR_LOAD, data)) ! 1608: ! 1609: /*----------------------------------------------------------- ! 1610: ** ! 1611: ** LOAD from memory to register. ! 1612: ** STORE from register to memory. ! 1613: ** ! 1614: ** Only supported by 810A, 860, 825A, 875, 895 and 896. ! 1615: ** ! 1616: **----------------------------------------------------------- ! 1617: ** ! 1618: ** LOAD_ABS (LEN) ! 1619: ** <<start address>> ! 1620: ** ! 1621: ** LOAD_REL (LEN) (DSA relative) ! 1622: ** <<dsa_offset>> ! 1623: ** ! 1624: **----------------------------------------------------------- ! 1625: */ ! 1626: ! 1627: #define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul) ! 1628: #define SCR_NO_FLUSH2 0x02000000 ! 1629: #define SCR_DSA_REL2 0x10000000 ! 1630: ! 1631: #define SCR_LOAD_R(reg, how, n) \ ! 1632: (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) ! 1633: ! 1634: #define SCR_STORE_R(reg, how, n) \ ! 1635: (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) ! 1636: ! 1637: #define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n) ! 1638: #define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n) ! 1639: #define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n) ! 1640: #define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n) ! 1641: ! 1642: #define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n) ! 1643: #define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n) ! 1644: #define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n) ! 1645: #define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n) ! 1646: ! 1647: ! 1648: /*----------------------------------------------------------- ! 1649: ** ! 1650: ** Waiting for Disconnect or Reselect ! 1651: ** ! 1652: **----------------------------------------------------------- ! 1653: ** ! 1654: ** JUMP [ | IFTRUE/IFFALSE ( ... ) ] ! 1655: ** <<address>> ! 1656: ** ! 1657: ** JUMPR [ | IFTRUE/IFFALSE ( ... ) ] ! 1658: ** <<distance>> ! 1659: ** ! 1660: ** CALL [ | IFTRUE/IFFALSE ( ... ) ] ! 1661: ** <<address>> ! 1662: ** ! 1663: ** CALLR [ | IFTRUE/IFFALSE ( ... ) ] ! 1664: ** <<distance>> ! 1665: ** ! 1666: ** RETURN [ | IFTRUE/IFFALSE ( ... ) ] ! 1667: ** <<dummy>> ! 1668: ** ! 1669: ** INT [ | IFTRUE/IFFALSE ( ... ) ] ! 1670: ** <<ident>> ! 1671: ** ! 1672: ** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ] ! 1673: ** <<ident>> ! 1674: ** ! 1675: ** Conditions: ! 1676: ** WHEN (phase) ! 1677: ** IF (phase) ! 1678: ** CARRYSET ! 1679: ** DATA (data, mask) ! 1680: ** ! 1681: **----------------------------------------------------------- ! 1682: */ ! 1683: ! 1684: #define SCR_NO_OP 0x80000000 ! 1685: #define SCR_JUMP 0x80080000 ! 1686: #define SCR_JUMP64 0x80480000 ! 1687: #define SCR_JUMPR 0x80880000 ! 1688: #define SCR_CALL 0x88080000 ! 1689: #define SCR_CALLR 0x88880000 ! 1690: #define SCR_RETURN 0x90080000 ! 1691: #define SCR_INT 0x98080000 ! 1692: #define SCR_INT_FLY 0x98180000 ! 1693: ! 1694: #define IFFALSE(arg) (0x00080000 | (arg)) ! 1695: #define IFTRUE(arg) (0x00000000 | (arg)) ! 1696: ! 1697: #define WHEN(phase) (0x00030000 | (phase)) ! 1698: #define IF(phase) (0x00020000 | (phase)) ! 1699: ! 1700: #define DATA(D) (0x00040000 | ((D) & 0xff)) ! 1701: #define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff)) ! 1702: ! 1703: #define CARRYSET (0x00200000) ! 1704: ! 1705: /*----------------------------------------------------------- ! 1706: ** ! 1707: ** SCSI constants. ! 1708: ** ! 1709: **----------------------------------------------------------- ! 1710: */ ! 1711: ! 1712: /* ! 1713: ** Messages ! 1714: */ ! 1715: ! 1716: #define M_COMPLETE (0x00) ! 1717: #define M_EXTENDED (0x01) ! 1718: #define M_SAVE_DP (0x02) ! 1719: #define M_RESTORE_DP (0x03) ! 1720: #define M_DISCONNECT (0x04) ! 1721: #define M_ID_ERROR (0x05) ! 1722: #define M_ABORT (0x06) ! 1723: #define M_REJECT (0x07) ! 1724: #define M_NOOP (0x08) ! 1725: #define M_PARITY (0x09) ! 1726: #define M_LCOMPLETE (0x0a) ! 1727: #define M_FCOMPLETE (0x0b) ! 1728: #define M_RESET (0x0c) ! 1729: #define M_ABORT_TAG (0x0d) ! 1730: #define M_CLEAR_QUEUE (0x0e) ! 1731: #define M_INIT_REC (0x0f) ! 1732: #define M_REL_REC (0x10) ! 1733: #define M_TERMINATE (0x11) ! 1734: #define M_SIMPLE_TAG (0x20) ! 1735: #define M_HEAD_TAG (0x21) ! 1736: #define M_ORDERED_TAG (0x22) ! 1737: #define M_IGN_RESIDUE (0x23) ! 1738: #define M_IDENTIFY (0x80) ! 1739: ! 1740: #define M_X_MODIFY_DP (0x00) ! 1741: #define M_X_SYNC_REQ (0x01) ! 1742: #define M_X_WIDE_REQ (0x03) ! 1743: #define M_X_PPR_REQ (0x04) ! 1744: ! 1745: /* ! 1746: ** Status ! 1747: */ ! 1748: ! 1749: #define S_GOOD (0x00) ! 1750: #define S_CHECK_COND (0x02) ! 1751: #define S_COND_MET (0x04) ! 1752: #define S_BUSY (0x08) ! 1753: #define S_INT (0x10) ! 1754: #define S_INT_COND_MET (0x14) ! 1755: #define S_CONFLICT (0x18) ! 1756: #define S_TERMINATED (0x20) ! 1757: #define S_QUEUE_FULL (0x28) ! 1758: #define S_ILLEGAL (0xff) ! 1759: #define S_SENSE (0x80) ! 1760: ! 1761: /* ! 1762: * End of ncrreg from FreeBSD ! 1763: */ ! 1764: ! 1765: #endif /* !defined HOSTS_C */ ! 1766: ! 1767: #endif /* defined SYM53C8XX_DEFS_H */
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