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1.1 root 1: /***********************************************************************
2: ;* File Name : TMSCSIM.H *
3: ;* TEKRAM DC-390(T) PCI SCSI Bus Master Host Adapter *
4: ;* Device Driver *
5: ;***********************************************************************/
6:
7: #ifndef TMSCSIM_H
8: #define TMSCSIM_H
9:
10: #define IRQ_NONE 255
11:
12: typedef unsigned char UCHAR;
13: typedef unsigned short USHORT;
14: typedef unsigned long ULONG;
15: typedef unsigned int UINT;
16:
17: typedef UCHAR *PUCHAR;
18: typedef USHORT *PUSHORT;
19: typedef ULONG *PULONG;
20: typedef Scsi_Host_Template *PSHT;
21: typedef struct Scsi_Host *PSH;
22: typedef Scsi_Device *PSCSIDEV;
23: typedef Scsi_Cmnd *PSCSICMD;
24: typedef void *PVOID;
25: typedef struct scatterlist *PSGL, SGL;
26:
27:
28: /*;-----------------------------------------------------------------------*/
29: typedef struct _SyncMsg
30: {
31: UCHAR ExtendMsg;
32: UCHAR ExtMsgLen;
33: UCHAR SyncXferReq;
34: UCHAR Period;
35: UCHAR ReqOffset;
36: } SyncMsg;
37: /*;-----------------------------------------------------------------------*/
38: typedef struct _Capacity
39: {
40: ULONG BlockCount;
41: ULONG BlockLength;
42: } Capacity;
43: /*;-----------------------------------------------------------------------*/
44: typedef struct _SGentry
45: {
46: ULONG SGXferDataPtr;
47: ULONG SGXferDataLen;
48: } SGentry;
49:
50: typedef struct _SGentry1
51: {
52: ULONG SGXLen;
53: ULONG SGXPtr;
54: } SGentry1, *PSGE;
55:
56:
57: #define MAX_ADAPTER_NUM 4
58: #define MAX_DEVICES 10
59: #define MAX_SG_LIST_BUF 16
60: #define MAX_CMD_QUEUE 20
61: #define MAX_CMD_PER_LUN 8
62: #define MAX_SCSI_ID 8
63: #define MAX_SRB_CNT MAX_CMD_QUEUE+4
64: #define END_SCAN 2
65:
66: #define SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40 MHz) */
67:
68: /*
69: ;-----------------------------------------------------------------------
70: ; SCSI Request Block
71: ;-----------------------------------------------------------------------
72: */
73: struct _SRB
74: {
75: UCHAR CmdBlock[12];
76:
77: struct _SRB *pNextSRB;
78: struct _DCB *pSRBDCB;
79: PSCSICMD pcmd;
80: PSGL pSegmentList;
81:
82: ULONG PhysSRB;
83: ULONG TotalXferredLen;
84: ULONG SGPhysAddr; /*;a segment starting address */
85: ULONG SGToBeXferLen; /*; to be xfer length */
86:
87: SGL Segmentx; /* make a one entry of S/G list table */
88:
89: PUCHAR pMsgPtr;
90: USHORT SRBState;
91: USHORT Revxx2; /* ??? */
92:
93: UCHAR MsgInBuf[6];
94: UCHAR MsgOutBuf[6];
95:
96: UCHAR AdaptStatus;
97: UCHAR TargetStatus;
98: UCHAR MsgCnt;
99: UCHAR EndMessage;
100: UCHAR TagNumber;
101: UCHAR SGcount;
102: UCHAR SGIndex;
103: UCHAR IORBFlag; /*;81h-Reset, 2-retry */
104:
105: UCHAR SRBStatus;
106: UCHAR RetryCnt;
107: UCHAR SRBFlag; /*; b0-AutoReqSense,b6-Read,b7-write */
108: /*; b4-settimeout,b5-Residual valid */
109: UCHAR ScsiCmdLen;
110: UCHAR ScsiPhase;
111: UCHAR Reserved3[3]; /*;for dword alignment */
112: ULONG Segment0[2];
113: ULONG Segment1[2];
114: };
115:
116: typedef struct _SRB DC390_SRB, *PSRB;
117:
118: /*
119: ;-----------------------------------------------------------------------
120: ; Device Control Block
121: ;-----------------------------------------------------------------------
122: */
123: struct _DCB
124: {
125: struct _DCB *pNextDCB;
126: struct _ACB *pDCBACB;
127:
128: PSCSICMD pQIORBhead;
129: PSCSICMD pQIORBtail;
130: PSCSICMD AboIORBhead;
131: PSCSICMD AboIORBtail;
132: USHORT QIORBCnt;
133: USHORT AboIORBcnt;
134:
135: PSRB pWaitingSRB;
136: PSRB pWaitLast;
137: PSRB pGoingSRB;
138: PSRB pGoingLast;
139: PSRB pActiveSRB;
140: USHORT GoingSRBCnt;
141: USHORT WaitSRBCnt; /* ??? */
142:
143: ULONG TagMask;
144:
145: USHORT MaxCommand;
146: USHORT AdaptIndex; /*; UnitInfo struc start */
147: USHORT UnitIndex; /*; nth Unit on this card */
148: UCHAR UnitSCSIID; /*; SCSI Target ID (SCSI Only) */
149: UCHAR UnitSCSILUN; /*; SCSI Log. Unit (SCSI Only) */
150:
151: UCHAR IdentifyMsg;
152: UCHAR CtrlR1;
153: UCHAR CtrlR3;
154: UCHAR CtrlR4;
155:
156: UCHAR InqDataBuf[8];
157: UCHAR CapacityBuf[8];
158: UCHAR DevMode;
159: UCHAR AdpMode;
160: UCHAR SyncMode; /*; 0:async mode */
161: UCHAR NegoPeriod; /*;for nego. */
162: UCHAR SyncPeriod; /*;for reg. */
163: UCHAR SyncOffset; /*;for reg. and nego.(low nibble) */
164: UCHAR UnitCtrlFlag;
165: UCHAR DCBFlag;
166: UCHAR DevType;
167: UCHAR Reserved2[3]; /*;for dword alignment */
168: };
169:
170: typedef struct _DCB DC390_DCB, *PDCB;
171: /*
172: ;-----------------------------------------------------------------------
173: ; Adapter Control Block
174: ;-----------------------------------------------------------------------
175: */
176: struct _ACB
177: {
178: ULONG PhysACB;
179: PSH pScsiHost;
180: struct _ACB *pNextACB;
181: USHORT IOPortBase;
182: USHORT Revxx1; /* ??? */
183:
184: PDCB pLinkDCB;
185: PDCB pDCBRunRobin;
186: PDCB pActiveDCB;
187: PDCB pDCB_free;
188: PSRB pFreeSRB;
189: PSRB pTmpSRB;
190: USHORT SRBCount;
191: USHORT AdapterIndex; /*; nth Adapter this driver */
192: USHORT max_id;
193: USHORT max_lun;
194:
195: UCHAR msgin123[4];
196: UCHAR status;
197: UCHAR AdaptSCSIID; /*; Adapter SCSI Target ID */
198: UCHAR AdaptSCSILUN; /*; Adapter SCSI LUN */
199: UCHAR DeviceCnt;
200: UCHAR IRQLevel;
201: UCHAR TagMaxNum;
202: UCHAR ACBFlag;
203: UCHAR Gmode2;
204: UCHAR LUNchk;
205: UCHAR scan_devices;
206: UCHAR HostID_Bit;
207: UCHAR Reserved1[1]; /*;for dword alignment */
208: UCHAR DCBmap[MAX_SCSI_ID];
209: DC390_DCB DCB_array[MAX_DEVICES]; /* +74h, Len=3E8 */
210: DC390_SRB SRB_array[MAX_SRB_CNT]; /* +45Ch, Len= */
211: DC390_SRB TmpSRB;
212: };
213:
214: typedef struct _ACB DC390_ACB, *PACB;
215:
216: /*;-----------------------------------------------------------------------*/
217:
218:
219: #define BIT31 0x80000000
220: #define BIT30 0x40000000
221: #define BIT29 0x20000000
222: #define BIT28 0x10000000
223: #define BIT27 0x08000000
224: #define BIT26 0x04000000
225: #define BIT25 0x02000000
226: #define BIT24 0x01000000
227: #define BIT23 0x00800000
228: #define BIT22 0x00400000
229: #define BIT21 0x00200000
230: #define BIT20 0x00100000
231: #define BIT19 0x00080000
232: #define BIT18 0x00040000
233: #define BIT17 0x00020000
234: #define BIT16 0x00010000
235: #define BIT15 0x00008000
236: #define BIT14 0x00004000
237: #define BIT13 0x00002000
238: #define BIT12 0x00001000
239: #define BIT11 0x00000800
240: #define BIT10 0x00000400
241: #define BIT9 0x00000200
242: #define BIT8 0x00000100
243: #define BIT7 0x00000080
244: #define BIT6 0x00000040
245: #define BIT5 0x00000020
246: #define BIT4 0x00000010
247: #define BIT3 0x00000008
248: #define BIT2 0x00000004
249: #define BIT1 0x00000002
250: #define BIT0 0x00000001
251:
252: /*;---UnitCtrlFlag */
253: #define UNIT_ALLOCATED BIT0
254: #define UNIT_INFO_CHANGED BIT1
255: #define FORMATING_MEDIA BIT2
256: #define UNIT_RETRY BIT3
257:
258: /*;---UnitFlags */
259: #define DASD_SUPPORT BIT0
260: #define SCSI_SUPPORT BIT1
261: #define ASPI_SUPPORT BIT2
262:
263: /*;----SRBState machine definition */
264: #define SRB_FREE 0
265: #define SRB_WAIT BIT0
266: #define SRB_READY BIT1
267: #define SRB_MSGOUT BIT2 /*;arbitration+msg_out 1st byte*/
268: #define SRB_MSGIN BIT3
269: #define SRB_MSGIN_MULTI BIT4
270: #define SRB_COMMAND BIT5
271: #define SRB_START_ BIT6 /*;arbitration+msg_out+command_out*/
272: #define SRB_DISCONNECT BIT7
273: #define SRB_DATA_XFER BIT8
274: #define SRB_XFERPAD BIT9
275: #define SRB_STATUS BIT10
276: #define SRB_COMPLETED BIT11
277: #define SRB_ABORT_SENT BIT12
278: #define DO_SYNC_NEGO BIT13
279: #define SRB_UNEXPECT_RESEL BIT14
280:
281: /*;---ACBFlag */
282: #define RESET_DEV BIT0
283: #define RESET_DETECT BIT1
284: #define RESET_DONE BIT2
285:
286: /*;---DCBFlag */
287: #define ABORT_DEV_ BIT0
288:
289: /*;---SRBstatus */
290: #define SRB_OK BIT0
291: #define ABORTION BIT1
292: #define OVER_RUN BIT2
293: #define UNDER_RUN BIT3
294: #define PARITY_ERROR BIT4
295: #define SRB_ERROR BIT5
296:
297: /*;---SRBFlag */
298: #define DATAOUT BIT7
299: #define DATAIN BIT6
300: #define RESIDUAL_VALID BIT5
301: #define ENABLE_TIMER BIT4
302: #define RESET_DEV0 BIT2
303: #define ABORT_DEV BIT1
304: #define AUTO_REQSENSE BIT0
305:
306: /*;---Adapter status */
307: #define H_STATUS_GOOD 0
308: #define H_SEL_TIMEOUT 0x11
309: #define H_OVER_UNDER_RUN 0x12
310: #define H_UNEXP_BUS_FREE 0x13
311: #define H_TARGET_PHASE_F 0x14
312: #define H_INVALID_CCB_OP 0x16
313: #define H_LINK_CCB_BAD 0x17
314: #define H_BAD_TARGET_DIR 0x18
315: #define H_DUPLICATE_CCB 0x19
316: #define H_BAD_CCB_OR_SG 0x1A
317: #define H_ABORT 0x0FF
318:
319: /*; SCSI Status byte codes*/
320: #define SCSI_STAT_GOOD 0x0 /*; Good status */
321: #define SCSI_STAT_CHECKCOND 0x02 /*; SCSI Check Condition */
322: #define SCSI_STAT_CONDMET 0x04 /*; Condition Met */
323: #define SCSI_STAT_BUSY 0x08 /*; Target busy status */
324: #define SCSI_STAT_INTER 0x10 /*; Intermediate status */
325: #define SCSI_STAT_INTERCONDMET 0x14 /*; Intermediate condition met */
326: #define SCSI_STAT_RESCONFLICT 0x18 /*; Reservation conflict */
327: #define SCSI_STAT_CMDTERM 0x22 /*; Command Terminated */
328: #define SCSI_STAT_QUEUEFULL 0x28 /*; Queue Full */
329:
330: #define SCSI_STAT_UNEXP_BUS_F 0xFD /*; Unexpect Bus Free */
331: #define SCSI_STAT_BUS_RST_DETECT 0xFE /*; Scsi Bus Reset detected */
332: #define SCSI_STAT_SEL_TIMEOUT 0xFF /*; Selection Time out */
333:
334: /*;---Sync_Mode */
335: #define SYNC_DISABLE 0
336: #define SYNC_ENABLE BIT0
337: #define SYNC_NEGO_DONE BIT1
338: #define WIDE_ENABLE BIT2
339: #define WIDE_NEGO_DONE BIT3
340: #define EN_TAG_QUEUING BIT4
341: #define EN_ATN_STOP BIT5
342:
343: #define SYNC_NEGO_OFFSET 15
344:
345: /*;---SCSI bus phase*/
346: #define SCSI_DATA_OUT 0
347: #define SCSI_DATA_IN 1
348: #define SCSI_COMMAND 2
349: #define SCSI_STATUS_ 3
350: #define SCSI_NOP0 4
351: #define SCSI_NOP1 5
352: #define SCSI_MSG_OUT 6
353: #define SCSI_MSG_IN 7
354:
355: /*;----SCSI MSG BYTE*/
356: #define MSG_COMPLETE 0x00
357: #define MSG_EXTENDED 0x01
358: #define MSG_SAVE_PTR 0x02
359: #define MSG_RESTORE_PTR 0x03
360: #define MSG_DISCONNECT 0x04
361: #define MSG_INITIATOR_ERROR 0x05
362: #define MSG_ABORT 0x06
363: #define MSG_REJECT_ 0x07
364: #define MSG_NOP 0x08
365: #define MSG_PARITY_ERROR 0x09
366: #define MSG_LINK_CMD_COMPL 0x0A
367: #define MSG_LINK_CMD_COMPL_FLG 0x0B
368: #define MSG_BUS_RESET 0x0C
369: #define MSG_ABORT_TAG 0x0D
370: #define MSG_SIMPLE_QTAG 0x20
371: #define MSG_HEAD_QTAG 0x21
372: #define MSG_ORDER_QTAG 0x22
373: #define MSG_IDENTIFY 0x80
374: #define MSG_HOST_ID 0x0C0
375:
376: /*;----SCSI STATUS BYTE*/
377: #define STATUS_GOOD 0x00
378: #define CHECK_CONDITION_ 0x02
379: #define STATUS_BUSY 0x08
380: #define STATUS_INTERMEDIATE 0x10
381: #define RESERVE_CONFLICT 0x18
382:
383: /* cmd->result */
384: #define STATUS_MASK_ 0xFF
385: #define MSG_MASK 0xFF00
386: #define RETURN_MASK 0xFF0000
387:
388: /*
389: ** Inquiry Data format
390: */
391:
392: typedef struct _SCSIInqData { /* INQ */
393:
394: UCHAR DevType; /* Periph Qualifier & Periph Dev Type*/
395: UCHAR RMB_TypeMod; /* rem media bit & Dev Type Modifier */
396: UCHAR Vers; /* ISO, ECMA, & ANSI versions */
397: UCHAR RDF; /* AEN, TRMIOP, & response data format*/
398: UCHAR AddLen; /* length of additional data */
399: UCHAR Res1; /* reserved */
400: UCHAR Res2; /* reserved */
401: UCHAR Flags; /* RelADr,Wbus32,Wbus16,Sync,etc. */
402: UCHAR VendorID[8]; /* Vendor Identification */
403: UCHAR ProductID[16]; /* Product Identification */
404: UCHAR ProductRev[4]; /* Product Revision */
405:
406:
407: } SCSI_INQDATA, *PSCSI_INQDATA;
408:
409:
410: /* Inquiry byte 0 masks */
411:
412:
413: #define SCSI_DEVTYPE 0x1F /* Peripheral Device Type */
414: #define SCSI_PERIPHQUAL 0xE0 /* Peripheral Qualifier */
415:
416:
417: /* Inquiry byte 1 mask */
418:
419: #define SCSI_REMOVABLE_MEDIA 0x80 /* Removable Media bit (1=removable) */
420:
421:
422: /* Peripheral Device Type definitions */
423:
424: #define SCSI_DASD 0x00 /* Direct-access Device */
425: #define SCSI_SEQACESS 0x01 /* Sequential-access device */
426: #define SCSI_PRINTER 0x02 /* Printer device */
427: #define SCSI_PROCESSOR 0x03 /* Processor device */
428: #define SCSI_WRITEONCE 0x04 /* Write-once device */
429: #define SCSI_CDROM 0x05 /* CD-ROM device */
430: #define SCSI_SCANNER 0x06 /* Scanner device */
431: #define SCSI_OPTICAL 0x07 /* Optical memory device */
432: #define SCSI_MEDCHGR 0x08 /* Medium changer device */
433: #define SCSI_COMM 0x09 /* Communications device */
434: #define SCSI_NODEV 0x1F /* Unknown or no device type */
435:
436: /*
437: ** Inquiry flag definitions (Inq data byte 7)
438: */
439:
440: #define SCSI_INQ_RELADR 0x80 /* device supports relative addressing*/
441: #define SCSI_INQ_WBUS32 0x40 /* device supports 32 bit data xfers */
442: #define SCSI_INQ_WBUS16 0x20 /* device supports 16 bit data xfers */
443: #define SCSI_INQ_SYNC 0x10 /* device supports synchronous xfer */
444: #define SCSI_INQ_LINKED 0x08 /* device supports linked commands */
445: #define SCSI_INQ_CMDQUEUE 0x02 /* device supports command queueing */
446: #define SCSI_INQ_SFTRE 0x01 /* device supports soft resets */
447:
448:
449: /*
450: ;==========================================================
451: ; EEPROM byte offset
452: ;==========================================================
453: */
454: typedef struct _EEprom
455: {
456: UCHAR EE_MODE1;
457: UCHAR EE_SPEED;
458: UCHAR xx1;
459: UCHAR xx2;
460: } EEprom, *PEEprom;
461:
462: #define EE_ADAPT_SCSI_ID 64
463: #define EE_MODE2 65
464: #define EE_DELAY 66
465: #define EE_TAG_CMD_NUM 67
466:
467: /*; EE_MODE1 bits definition*/
468: #define PARITY_CHK_ BIT0
469: #define SYNC_NEGO_ BIT1
470: #define EN_DISCONNECT_ BIT2
471: #define SEND_START_ BIT3
472: #define TAG_QUEUING_ BIT4
473:
474: /*; EE_MODE2 bits definition*/
475: #define MORE2_DRV BIT0
476: #define GREATER_1G BIT1
477: #define RST_SCSI_BUS BIT2
478: #define ACTIVE_NEGATION BIT3
479: #define NO_SEEK BIT4
480: #define LUN_CHECK BIT5
481:
482: #define ENABLE_CE 1
483: #define DISABLE_CE 0
484: #define EEPROM_READ 0x80
485:
486: /*
487: ;==========================================================
488: ; AMD 53C974 Registers bit Definition
489: ;==========================================================
490: */
491: /*
492: ;====================
493: ; SCSI Register
494: ;====================
495: */
496:
497: /*; Command Reg.(+0CH) */
498: #define DMA_COMMAND BIT7
499: #define NOP_CMD 0
500: #define CLEAR_FIFO_CMD 1
501: #define RST_DEVICE_CMD 2
502: #define RST_SCSI_BUS_CMD 3
503: #define INFO_XFER_CMD 0x10
504: #define INITIATOR_CMD_CMPLTE 0x11
505: #define MSG_ACCEPTED_CMD 0x12
506: #define XFER_PAD_BYTE 0x18
507: #define SET_ATN_CMD 0x1A
508: #define RESET_ATN_CMD 0x1B
509: #define SELECT_W_ATN 0x42
510: #define SEL_W_ATN_STOP 0x43
511: #define EN_SEL_RESEL 0x44
512: #define SEL_W_ATN2 0x46
513: #define DATA_XFER_CMD INFO_XFER_CMD
514:
515:
516: /*; SCSI Status Reg.(+10H) */
517: #define INTERRUPT BIT7
518: #define ILLEGAL_OP_ERR BIT6
519: #define PARITY_ERR BIT5
520: #define COUNT_2_ZERO BIT4
521: #define GROUP_CODE_VALID BIT3
522: #define SCSI_PHASE_MASK (BIT2+BIT1+BIT0)
523:
524: /*; Interrupt Status Reg.(+14H) */
525: #define SCSI_RESET BIT7
526: #define INVALID_CMD BIT6
527: #define DISCONNECTED BIT5
528: #define SERVICE_REQUEST BIT4
529: #define SUCCESSFUL_OP BIT3
530: #define RESELECTED BIT2
531: #define SEL_ATTENTION BIT1
532: #define SELECTED BIT0
533:
534: /*; Internal State Reg.(+18H) */
535: #define SYNC_OFFSET_FLAG BIT3
536: #define INTRN_STATE_MASK (BIT2+BIT1+BIT0)
537:
538: /*; Clock Factor Reg.(+24H) */
539: #define CLK_FREQ_40MHZ 0
540: #define CLK_FREQ_35MHZ (BIT2+BIT1+BIT0)
541: #define CLK_FREQ_30MHZ (BIT2+BIT1)
542: #define CLK_FREQ_25MHZ (BIT2+BIT0)
543: #define CLK_FREQ_20MHZ BIT2
544: #define CLK_FREQ_15MHZ (BIT1+BIT0)
545: #define CLK_FREQ_10MHZ BIT1
546:
547: /*; Control Reg. 1(+20H) */
548: #define EXTENDED_TIMING BIT7
549: #define DIS_INT_ON_SCSI_RST BIT6
550: #define PARITY_ERR_REPO BIT4
551: #define SCSI_ID_ON_BUS (BIT2+BIT1+BIT0)
552:
553: /*; Control Reg. 2(+2CH) */
554: #define EN_FEATURE BIT6
555: #define EN_SCSI2_CMD BIT3
556:
557: /*; Control Reg. 3(+30H) */
558: #define ID_MSG_CHECK BIT7
559: #define EN_QTAG_MSG BIT6
560: #define EN_GRP2_CMD BIT5
561: #define FAST_SCSI BIT4 /* ;10MB/SEC */
562: #define FAST_CLK BIT3 /* ;25 - 40 MHZ */
563:
564: /*; Control Reg. 4(+34H) */
565: #define EATER_12NS 0
566: #define EATER_25NS BIT7
567: #define EATER_35NS BIT6
568: #define EATER_0NS (BIT7+BIT6)
569: #define NEGATE_REQACKDATA BIT2
570: #define NEGATE_REQACK BIT3
571: /*
572: ;====================
573: ; DMA Register
574: ;====================
575: */
576: /*; DMA Command Reg.(+40H) */
577: #define READ_DIRECTION BIT7
578: #define WRITE_DIRECTION 0
579: #define EN_DMA_INT BIT6
580: #define MAP_TO_MDL BIT5
581: #define DIAGNOSTIC BIT4
582: #define DMA_IDLE_CMD 0
583: #define DMA_BLAST_CMD BIT0
584: #define DMA_ABORT_CMD BIT1
585: #define DMA_START_CMD (BIT1+BIT0)
586:
587: /*; DMA Status Reg.(+54H) */
588: #define PCI_MS_ABORT BIT6
589: #define BLAST_COMPLETE BIT5
590: #define SCSI_INTERRUPT BIT4
591: #define DMA_XFER_DONE BIT3
592: #define DMA_XFER_ABORT BIT2
593: #define DMA_XFER_ERROR BIT1
594: #define POWER_DOWN BIT0
595:
596: /*
597: ; DMA SCSI Bus and Ctrl.(+70H)
598: ;EN_INT_ON_PCI_ABORT
599: */
600:
601: /*
602: ;==========================================================
603: ; SCSI Chip register address offset
604: ;==========================================================
605: */
606: #define CtcReg_Low 0x00
607: #define CtcReg_Mid 0x04
608: #define ScsiFifo 0x08
609: #define ScsiCmd 0x0C
610: #define Scsi_Status 0x10
611: #define INT_Status 0x14
612: #define Sync_Period 0x18
613: #define Sync_Offset 0x1C
614: #define CtrlReg1 0x20
615: #define Clk_Factor 0x24
616: #define CtrlReg2 0x2C
617: #define CtrlReg3 0x30
618: #define CtrlReg4 0x34
619: #define CtcReg_High 0x38
620: #define DMA_Cmd 0x40
621: #define DMA_XferCnt 0x44
622: #define DMA_XferAddr 0x48
623: #define DMA_Wk_ByteCntr 0x4C
624: #define DMA_Wk_AddrCntr 0x50
625: #define DMA_Status 0x54
626: #define DMA_MDL_Addr 0x58
627: #define DMA_Wk_MDL_Cntr 0x5C
628: #define DMA_ScsiBusCtrl 0x70
629:
630: #define StcReg_Low CtcReg_Low
631: #define StcReg_Mid CtcReg_Mid
632: #define Scsi_Dest_ID Scsi_Status
633: #define Scsi_TimeOut INT_Status
634: #define Intern_State Sync_Period
635: #define Current_Fifo Sync_Offset
636: #define StcReg_High CtcReg_High
637:
638: #define am_target Scsi_Status
639: #define am_timeout INT_Status
640: #define am_seq_step Sync_Period
641: #define am_fifo_count Sync_Offset
642:
643:
644: #define DC390_read8(address) \
645: inb(DC390_ioport + (address)))
646:
647: #define DC390_read16(address) \
648: inw(DC390_ioport + (address)))
649:
650: #define DC390_read32(address) \
651: inl(DC390_ioport + (address)))
652:
653: #define DC390_write8(address,value) \
654: outb((value), DC390_ioport + (address)))
655:
656: #define DC390_write16(address,value) \
657: outw((value), DC390_ioport + (address)))
658:
659: #define DC390_write32(address,value) \
660: outl((value), DC390_ioport + (address)))
661:
662:
663: /* Configuration method #1 */
664: #define PCI_CFG1_ADDRESS_REG 0xcf8
665: #define PCI_CFG1_DATA_REG 0xcfc
666: #define PCI_CFG1_ENABLE 0x80000000
667: #define PCI_CFG1_TUPPLE(bus, device, function, register) \
668: (PCI_CFG1_ENABLE | (((bus) << 16) & 0xff0000) | \
669: (((device) << 11) & 0xf800) | (((function) << 8) & 0x700)| \
670: (((register) << 2) & 0xfc))
671:
672: /* Configuration method #2 */
673: #define PCI_CFG2_ENABLE_REG 0xcf8
674: #define PCI_CFG2_FORWARD_REG 0xcfa
675: #define PCI_CFG2_ENABLE 0x0f0
676: #define PCI_CFG2_TUPPLE(function) \
677: (PCI_CFG2_ENABLE | (((function) << 1) & 0xe))
678:
679:
680: #endif /* TMSCSIM_H */
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