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1.1 ! root 1: /*********************************************************************** ! 2: ;* File Name : TMSCSIW.H * ! 3: ;* TEKRAM DC-390 PCI Wide SCSI Bus Master Host Adapter* ! 4: ;* Device Driver * ! 5: ;***********************************************************************/ ! 6: ! 7: #ifndef TMSCSIW_H ! 8: #define TMSCSIW_H ! 9: ! 10: #define IRQ_NONE 255 ! 11: ! 12: typedef unsigned char UCHAR; ! 13: typedef unsigned short USHORT; ! 14: typedef unsigned long ULONG; ! 15: typedef unsigned int UINT; ! 16: ! 17: typedef UCHAR *PUCHAR; ! 18: typedef USHORT *PUSHORT; ! 19: typedef ULONG *PULONG; ! 20: typedef Scsi_Host_Template *PSHT; ! 21: typedef struct Scsi_Host *PSH; ! 22: typedef Scsi_Device *PSCSIDEV; ! 23: typedef Scsi_Cmnd *PSCSICMD; ! 24: typedef void *PVOID; ! 25: typedef struct scatterlist *PSGL, SGL; ! 26: ! 27: ! 28: typedef struct _AddWkSpace ! 29: { ! 30: USHORT WKIOCtrlFlag; /* ;b7-Done, b6-wrtVerify, b0-in process */ ! 31: USHORT XferredBlkCnt; ! 32: USHORT WKToXferBlkCnt; ! 33: USHORT WKcSGListDone; ! 34: USHORT WKMaxSGIndex; ! 35: ULONG WKToXferLen; ! 36: USHORT NxtSGoffset; ! 37: } AddWkSpace; ! 38: ! 39: /*;-----------------------------------------------------------------------*/ ! 40: typedef struct _SyncMsg ! 41: { ! 42: UCHAR ExtendMsg; ! 43: UCHAR ExtMsgLen; ! 44: UCHAR SyncXferReq; ! 45: UCHAR Period; ! 46: UCHAR ReqOffset; ! 47: } SyncMsg; ! 48: /*;-----------------------------------------------------------------------*/ ! 49: typedef struct _Capacity ! 50: { ! 51: ULONG BlockCount; ! 52: ULONG BlockLength; ! 53: } Capacity; ! 54: /*;-----------------------------------------------------------------------*/ ! 55: typedef struct _SGentry ! 56: { ! 57: ULONG SGXferDataPtr; ! 58: ULONG SGXferDataLen; ! 59: } SGentry; ! 60: ! 61: typedef struct _SGentry1 ! 62: { ! 63: ULONG SGXLen; ! 64: ULONG SGXPtr; ! 65: } SGentry1, *PSGE; ! 66: ! 67: ! 68: #define MAX_ADAPTER_NUM 4 ! 69: #define MAX_DEVICES 10 ! 70: #define MAX_SG_LIST_BUF 32 ! 71: #define MAX_CMD_QUEUE 20 ! 72: #define MAX_CMD_PER_LUN 8 ! 73: #define MAX_SCSI_ID 16 ! 74: #define MAX_SRB_CNT MAX_CMD_QUEUE+4 ! 75: #define END_SCAN 2 ! 76: ! 77: /* ! 78: ;----------------------------------------------------------------------- ! 79: ; SCSI Request Block ! 80: ;----------------------------------------------------------------------- ! 81: */ ! 82: struct _SRB ! 83: { ! 84: UCHAR CmdBlock[12]; ! 85: ULONG Segment0[MAX_SG_LIST_BUF+1][2]; ! 86: ULONG SegmentPad[2]; ! 87: ! 88: ULONG __select; ! 89: ULONG __command[2]; /* ;len,ptr */ ! 90: ULONG __msgout0[2]; /* ;len,ptr */ ! 91: ! 92: ULONG PhysSRB; ! 93: ULONG ReturnAddr; ! 94: ULONG RemainSegPtr; ! 95: PSCSICMD pcmd; ! 96: struct _SRB *pNextSRB; ! 97: struct _DCB *pSRBDCB; ! 98: PSGL pSegmentList; ! 99: ULONG XferredLen; ! 100: ! 101: ULONG SGPhysAddr; /*;a segment starting address */ ! 102: ULONG XferredLen1; ! 103: ! 104: SGL Segmentx; /* make a one entry of S/G list table */ ! 105: ! 106: PUCHAR pMsgPtr; ! 107: USHORT SRBState; ! 108: USHORT Revxx2; /* ??? */ ! 109: ! 110: UCHAR MsgInBuf[6]; ! 111: UCHAR MsgOutBuf[6]; ! 112: UCHAR SenseDataBuf[0x12]; ! 113: UCHAR AdaptStatus; ! 114: UCHAR TargetStatus; ! 115: ! 116: UCHAR MsgCnt; ! 117: UCHAR EndMessage; ! 118: UCHAR TagNumber; ! 119: UCHAR InternalReq; /*; 1-ADD internal request, 0-DMD request */ ! 120: ! 121: UCHAR SGcount; ! 122: UCHAR SGIndex; ! 123: UCHAR IORBFlag; /*;81h-Reset, 2-retry */ ! 124: UCHAR SRBStatus; ! 125: ! 126: UCHAR RetryCnt; ! 127: UCHAR SRBFlag; /*; b0-AutoReqSense,b6-Read,b7-write */ ! 128: /*; b4-settimeout,b5-Residual valid */ ! 129: UCHAR ScratchABuf; ! 130: UCHAR Reserved3[1]; /*;for dword alignment */ ! 131: }; ! 132: ! 133: typedef struct _SRB DC390W_SRB, *PSRB; ! 134: ! 135: /* ! 136: ;----------------------------------------------------------------------- ! 137: ; Device Control Block ! 138: ;----------------------------------------------------------------------- ! 139: */ ! 140: struct _DCB ! 141: { ! 142: UCHAR DCBselect; ! 143: UCHAR DCBsxfer; ! 144: UCHAR DCBsdid; ! 145: UCHAR DCBscntl3; ! 146: ! 147: UCHAR DCBscntl0; ! 148: UCHAR IdentifyMsg; ! 149: UCHAR DevMode; ! 150: UCHAR AdpMode; ! 151: ! 152: struct _DCB *pNextDCB; ! 153: struct _ACB *pDCBACB; ! 154: ! 155: PSCSICMD pQIORBhead; ! 156: PSCSICMD pQIORBtail; ! 157: PSCSICMD AboIORBhead; ! 158: PSCSICMD AboIORBtail; ! 159: USHORT QIORBCnt; ! 160: USHORT AboIORBcnt; ! 161: ! 162: PSRB pWaitingSRB; ! 163: PSRB pWaitLast; ! 164: PSRB pGoingSRB; ! 165: PSRB pGoingLast; ! 166: PSRB pActiveSRB; ! 167: USHORT GoingSRBCnt; ! 168: USHORT WaitSRBCnt; /* ??? */ ! 169: ! 170: ULONG TagMask; ! 171: ! 172: USHORT MaxCommand; ! 173: USHORT AdaptIndex; /*; UnitInfo struc start */ ! 174: USHORT UnitIndex; /*; nth Unit on this card */ ! 175: UCHAR UnitSCSIID; /*; SCSI Target ID (SCSI Only) */ ! 176: UCHAR UnitSCSILUN; /*; SCSI Log. Unit (SCSI Only) */ ! 177: ! 178: UCHAR InqDataBuf[8]; ! 179: UCHAR CapacityBuf[8]; ! 180: UCHAR SyncMode; /*; 0:async mode */ ! 181: UCHAR NegoPeriod; /*;for nego. */ ! 182: UCHAR SyncPeriod; /*;for reg. */ ! 183: UCHAR SyncOffset; /*;for reg. and nego.(low nibble) */ ! 184: UCHAR UnitCtrlFlag; ! 185: UCHAR DCBFlag; ! 186: UCHAR DevType; ! 187: UCHAR Reserved2[1]; /*;for dword alignment */ ! 188: }; ! 189: ! 190: typedef struct _DCB DC390W_DCB, *PDCB; ! 191: /* ! 192: ;----------------------------------------------------------------------- ! 193: ; Adapter Control Block ! 194: ;----------------------------------------------------------------------- ! 195: */ ! 196: struct _ACB ! 197: { ! 198: ULONG PhysACB; ! 199: ULONG DevVendorID; ! 200: PSH pScsiHost; ! 201: struct _ACB *pNextACB; ! 202: USHORT IOPortBase; ! 203: USHORT Revxx1; /* ??? */ ! 204: ! 205: PDCB pLinkDCB; ! 206: PDCB pDCBRunRobin; ! 207: PDCB pActiveDCB; ! 208: PDCB pDCB_free; ! 209: PSRB pFreeSRB; ! 210: USHORT SRBCount; ! 211: USHORT AdapterIndex; /*; nth Adapter this driver */ ! 212: USHORT max_id; ! 213: USHORT max_lun; ! 214: ! 215: ULONG jmp_reselect; ! 216: ULONG jmp_select; ! 217: ULONG jmp_table8; ! 218: ULONG jmp_set_atn; ! 219: ULONG jmp_clear_ack; ! 220: ULONG jmp_next; ! 221: ULONG jmp_din8; ! 222: ULONG jmp_dout8; ! 223: ULONG jmp_clear_atn; ! 224: ULONG jmp_reselecttag; ! 225: ! 226: UCHAR msgin123[4]; ! 227: UCHAR status; ! 228: UCHAR AdaptSCSIID; /*; Adapter SCSI Target ID */ ! 229: UCHAR AdaptSCSILUN; /*; Adapter SCSI LUN */ ! 230: UCHAR DeviceCnt; ! 231: UCHAR IRQLevel; ! 232: UCHAR AdaptType; /*;1:390W, 2:390U, 3:390F */ ! 233: UCHAR TagMaxNum; ! 234: UCHAR ACBFlag; ! 235: UCHAR Gmode2; ! 236: UCHAR LUNchk; ! 237: UCHAR scan_devices; ! 238: UCHAR Reserved1[1]; /*;for dword alignment */ ! 239: UCHAR DCBmap[MAX_SCSI_ID]; ! 240: DC390W_DCB DCB_array[MAX_DEVICES]; /* +74h, Len=3E8 */ ! 241: DC390W_SRB SRB_array[MAX_SRB_CNT]; /* +45Ch, Len= */ ! 242: }; ! 243: ! 244: typedef struct _ACB DC390W_ACB, *PACB; ! 245: ! 246: /*;-----------------------------------------------------------------------*/ ! 247: ! 248: #define PCI_DEVICE_ID_NCR53C825A 0x0003 ! 249: #define PCI_DEVICE_ID_NCR53C875 0x000f ! 250: ! 251: #define CHIP810_ID 0x00011000 ! 252: #define CHIP820_ID 0x00021000 ! 253: #define CHIP825_ID 0x00031000 ! 254: #define CHIP815_ID 0x00041000 ! 255: #define CHIP875_ID 0x000f1000 ! 256: ! 257: #define DC390W 1 /*;825A - 16 BIT*/ ! 258: #define DC390U 2 /*;875 - 8 BIT*/ ! 259: #define DC390F 3 /*;875 - 16 BIT*/ ! 260: ! 261: #define BIT31 0x80000000 ! 262: #define BIT30 0x40000000 ! 263: #define BIT29 0x20000000 ! 264: #define BIT28 0x10000000 ! 265: #define BIT27 0x08000000 ! 266: #define BIT26 0x04000000 ! 267: #define BIT25 0x02000000 ! 268: #define BIT24 0x01000000 ! 269: #define BIT23 0x00800000 ! 270: #define BIT22 0x00400000 ! 271: #define BIT21 0x00200000 ! 272: #define BIT20 0x00100000 ! 273: #define BIT19 0x00080000 ! 274: #define BIT18 0x00040000 ! 275: #define BIT17 0x00020000 ! 276: #define BIT16 0x00010000 ! 277: #define BIT15 0x00008000 ! 278: #define BIT14 0x00004000 ! 279: #define BIT13 0x00002000 ! 280: #define BIT12 0x00001000 ! 281: #define BIT11 0x00000800 ! 282: #define BIT10 0x00000400 ! 283: #define BIT9 0x00000200 ! 284: #define BIT8 0x00000100 ! 285: #define BIT7 0x00000080 ! 286: #define BIT6 0x00000040 ! 287: #define BIT5 0x00000020 ! 288: #define BIT4 0x00000010 ! 289: #define BIT3 0x00000008 ! 290: #define BIT2 0x00000004 ! 291: #define BIT1 0x00000002 ! 292: #define BIT0 0x00000001 ! 293: ! 294: /*;---WKIOCtrlFlag */ ! 295: #define IN_PROCESSING BIT0 ! 296: #define BAD_WRITE_V_CMD BIT1 ! 297: #define VERIFY_CMD BIT2 ! 298: #define RESIDUAL_SG BIT3 ! 299: ! 300: /*;---UnitCtrlFlag */ ! 301: #define UNIT_ALLOCATED BIT0 ! 302: #define UNIT_INFO_CHANGED BIT1 ! 303: #define FORMATING_MEDIA BIT2 ! 304: #define UNIT_RETRY BIT3 ! 305: ! 306: /*;---UnitFlags */ ! 307: #define DASD_SUPPORT BIT0 ! 308: #define SCSI_SUPPORT BIT1 ! 309: #define ASPI_SUPPORT BIT2 ! 310: ! 311: /*;----SRBState machine definition */ ! 312: #define SRB_FREE 0 ! 313: #define SRB_WAIT BIT0 ! 314: #define SRB_READY BIT1 ! 315: #define SRB_MSGOUT BIT2 /*;arbitration+msg_out 1st byte*/ ! 316: #define SRB_MSGIN BIT3 ! 317: #define SRB_MSGIN_MULTI BIT4 ! 318: #define SRB_COMMAND BIT5 ! 319: #define SRB_START_ BIT6 /*;arbitration+msg_out+command_out*/ ! 320: #define SRB_DISCONNECT BIT7 ! 321: #define SRB_DATA_XFER BIT8 ! 322: #define SRB_XFERPAD BIT9 ! 323: #define SRB_STATUS BIT10 ! 324: #define SRB_COMPLETED BIT11 ! 325: ! 326: #define DO_WIDE_NEGO BIT12 ! 327: #define DO_SYNC_NEGO BIT13 ! 328: #define SRB_UNEXPECT_RESEL BIT14 ! 329: ! 330: /*;---ACBFlag */ ! 331: #define RESET_DEV BIT0 ! 332: #define RESET_DETECT BIT1 ! 333: #define RESET_DONE BIT2 ! 334: ! 335: /*;---DCBFlag */ ! 336: #define ABORT_DEV_ BIT0 ! 337: ! 338: /*;---SRBstatus */ ! 339: #define SRB_OK BIT0 ! 340: #define ABORTION BIT1 ! 341: #define OVER_RUN BIT2 ! 342: #define UNDER_RUN BIT3 ! 343: #define SRB_ERROR BIT4 ! 344: ! 345: /*;---SRBFlag */ ! 346: #define DATAOUT BIT7 ! 347: #define DATAIN BIT6 ! 348: #define RESIDUAL_VALID BIT5 ! 349: #define ENABLE_TIMER BIT4 ! 350: #define RESET_DEV0 BIT2 ! 351: #define ABORT_DEV BIT1 ! 352: #define AUTO_REQSENSE BIT0 ! 353: ! 354: /*;---Adapter status */ ! 355: #define H_STATUS_GOOD 0 ! 356: #define H_SEL_TIMEOUT 0x11 ! 357: #define H_OVER_UNDER_RUN 0x12 ! 358: #define H_UNEXP_BUS_FREE 0x13 ! 359: #define H_TARGET_PHASE_F 0x14 ! 360: #define H_INVALID_CCB_OP 0x16 ! 361: #define H_LINK_CCB_BAD 0x17 ! 362: #define H_BAD_TARGET_DIR 0x18 ! 363: #define H_DUPLICATE_CCB 0x19 ! 364: #define H_BAD_CCB_OR_SG 0x1A ! 365: #define H_ABORT 0x0FF ! 366: ! 367: /*; SCSI Status byte codes*/ ! 368: #define SCSI_STAT_GOOD 0x0 /*; Good status */ ! 369: #define SCSI_STAT_CHECKCOND 0x02 /*; SCSI Check Condition */ ! 370: #define SCSI_STAT_CONDMET 0x04 /*; Condition Met */ ! 371: #define SCSI_STAT_BUSY 0x08 /*; Target busy status */ ! 372: #define SCSI_STAT_INTER 0x10 /*; Intermediate status */ ! 373: #define SCSI_STAT_INTERCONDMET 0x14 /*; Intermediate condition met */ ! 374: #define SCSI_STAT_RESCONFLICT 0x18 /*; Reservation conflict */ ! 375: #define SCSI_STAT_CMDTERM 0x22 /*; Command Terminated */ ! 376: #define SCSI_STAT_QUEUEFULL 0x28 /*; Queue Full */ ! 377: ! 378: #define SCSI_STAT_UNEXP_BUS_F 0xFD /*; Unexpect Bus Free */ ! 379: #define SCSI_STAT_BUS_RST_DETECT 0xFE /*; Scsi Bus Reset detected */ ! 380: #define SCSI_STAT_SEL_TIMEOUT 0xFF /*; Selection Time out */ ! 381: ! 382: /*;---Sync_Mode */ ! 383: #define SYNC_DISABLE 0 ! 384: #define SYNC_ENABLE BIT0 ! 385: #define SYNC_NEGO_DONE BIT1 ! 386: #define WIDE_ENABLE BIT2 ! 387: #define WIDE_NEGO_DONE BIT3 ! 388: #define EN_TAG_QUEUING BIT4 ! 389: ! 390: #define SYNC_NEGO_OFFSET 16 ! 391: ! 392: /*;---SCSI bus phase*/ ! 393: #define SCSI_DATA_OUT 0 ! 394: #define SCSI_DATA_IN 1 ! 395: #define SCSI_COMMAND 2 ! 396: #define SCSI_STATUS_ 3 ! 397: #define SCSI_NOP0 4 ! 398: #define SCSI_NOP1 5 ! 399: #define SCSI_MSG_OUT 6 ! 400: #define SCSI_MSG_IN 7 ! 401: ! 402: /*;----SCSI MSG BYTE*/ ! 403: #define MSG_COMPLETE 0x00 ! 404: #define MSG_EXTENDED 0x01 ! 405: #define MSG_SAVE_PTR 0x02 ! 406: #define MSG_RESTORE_PTR 0x03 ! 407: #define MSG_DISCONNECT 0x04 ! 408: #define MSG_INITIATOR_ERROR 0x05 ! 409: #define MSG_ABORT 0x06 ! 410: #define MSG_REJECT_ 0x07 ! 411: #define MSG_NOP 0x08 ! 412: #define MSG_PARITY_ERROR 0x09 ! 413: #define MSG_LINK_CMD_COMPL 0x0A ! 414: #define MSG_LINK_CMD_COMPL_FLG 0x0B ! 415: #define MSG_BUS_RESET 0x0C ! 416: #define MSG_ABORT_TAG 0x0D ! 417: #define MSG_SIMPLE_QTAG 0x20 ! 418: #define MSG_HEAD_QTAG 0x21 ! 419: #define MSG_ORDER_QTAG 0x22 ! 420: #define MSG_IDENTIFY 0x80 ! 421: #define MSG_HOST_ID 0x0C0 ! 422: ! 423: /*;----SCSI STATUS BYTE*/ ! 424: #define STATUS_GOOD 0x00 ! 425: #define CHECK_CONDITION_ 0x02 ! 426: #define STATUS_BUSY 0x08 ! 427: #define STATUS_INTERMEDIATE 0x10 ! 428: #define RESERVE_CONFLICT 0x18 ! 429: ! 430: /* cmd->result */ ! 431: #define STATUS_MASK_ 0xFF ! 432: #define MSG_MASK 0xFF00 ! 433: #define RETURN_MASK 0xFF0000 ! 434: ! 435: /* ! 436: ** Inquiry Data format ! 437: */ ! 438: ! 439: typedef struct _SCSIInqData { /* INQ */ ! 440: ! 441: UCHAR DevType; /* Periph Qualifier & Periph Dev Type*/ ! 442: UCHAR RMB_TypeMod; /* rem media bit & Dev Type Modifier */ ! 443: UCHAR Vers; /* ISO, ECMA, & ANSI versions */ ! 444: UCHAR RDF; /* AEN, TRMIOP, & response data format*/ ! 445: UCHAR AddLen; /* length of additional data */ ! 446: UCHAR Res1; /* reserved */ ! 447: UCHAR Res2; /* reserved */ ! 448: UCHAR Flags; /* RelADr,Wbus32,Wbus16,Sync,etc. */ ! 449: UCHAR VendorID[8]; /* Vendor Identification */ ! 450: UCHAR ProductID[16]; /* Product Identification */ ! 451: UCHAR ProductRev[4]; /* Product Revision */ ! 452: ! 453: ! 454: } SCSI_INQDATA, *PSCSI_INQDATA; ! 455: ! 456: ! 457: /* Inquiry byte 0 masks */ ! 458: ! 459: ! 460: #define SCSI_DEVTYPE 0x1F /* Peripheral Device Type */ ! 461: #define SCSI_PERIPHQUAL 0xE0 /* Peripheral Qualifier */ ! 462: ! 463: ! 464: /* Inquiry byte 1 mask */ ! 465: ! 466: #define SCSI_REMOVABLE_MEDIA 0x80 /* Removable Media bit (1=removable) */ ! 467: ! 468: ! 469: /* Peripheral Device Type definitions */ ! 470: ! 471: #define SCSI_DASD 0x00 /* Direct-access Device */ ! 472: #define SCSI_SEQACESS 0x01 /* Sequential-access device */ ! 473: #define SCSI_PRINTER 0x02 /* Printer device */ ! 474: #define SCSI_PROCESSOR 0x03 /* Processor device */ ! 475: #define SCSI_WRITEONCE 0x04 /* Write-once device */ ! 476: #define SCSI_CDROM 0x05 /* CD-ROM device */ ! 477: #define SCSI_SCANNER 0x06 /* Scanner device */ ! 478: #define SCSI_OPTICAL 0x07 /* Optical memory device */ ! 479: #define SCSI_MEDCHGR 0x08 /* Medium changer device */ ! 480: #define SCSI_COMM 0x09 /* Communications device */ ! 481: #define SCSI_NODEV 0x1F /* Unknown or no device type */ ! 482: ! 483: /* ! 484: ** Inquiry flag definitions (Inq data byte 7) ! 485: */ ! 486: ! 487: #define SCSI_INQ_RELADR 0x80 /* device supports relative addressing*/ ! 488: #define SCSI_INQ_WBUS32 0x40 /* device supports 32 bit data xfers */ ! 489: #define SCSI_INQ_WBUS16 0x20 /* device supports 16 bit data xfers */ ! 490: #define SCSI_INQ_SYNC 0x10 /* device supports synchronous xfer */ ! 491: #define SCSI_INQ_LINKED 0x08 /* device supports linked commands */ ! 492: #define SCSI_INQ_CMDQUEUE 0x02 /* device supports command queueing */ ! 493: #define SCSI_INQ_SFTRE 0x01 /* device supports soft resets */ ! 494: ! 495: ! 496: /* ! 497: ;========================================================== ! 498: ; EEPROM byte offset ! 499: ;========================================================== ! 500: */ ! 501: typedef struct _EEprom ! 502: { ! 503: UCHAR EE_MODE1; ! 504: UCHAR EE_SPEED; ! 505: UCHAR xx1; ! 506: UCHAR xx2; ! 507: } EEprom, *PEEprom; ! 508: ! 509: #define EE_ADAPT_SCSI_ID 64 ! 510: #define EE_MODE2 65 ! 511: #define EE_DELAY 66 ! 512: #define EE_TAG_CMD_NUM 67 ! 513: ! 514: /*; EE_MODE1 bits definition*/ ! 515: #define PARITY_CHK_ BIT0 ! 516: #define SYNC_NEGO_ BIT1 ! 517: #define EN_DISCONNECT_ BIT2 ! 518: #define SEND_START_ BIT3 ! 519: #define TAG_QUEUING_ BIT4 ! 520: #define WIDE_NEGO_ BIT5 ! 521: ! 522: /*; EE_MODE2 bits definition*/ ! 523: #define MORE2_DRV BIT0 ! 524: #define GREATER_1G BIT1 ! 525: #define RST_SCSI_BUS BIT2 ! 526: #define ACTIVE_NEGATION BIT3 ! 527: #define NO_SEEK BIT4 ! 528: #define LUN_CHECK BIT5 ! 529: ! 530: #define ENABLE_CE 1 ! 531: #define DISABLE_CE 0 ! 532: #define EEPROM_READ 0x80 ! 533: ! 534: /* ! 535: ;========================================================== ! 536: ; NCR 53C825 Registers Structure ! 537: ;========================================================== ! 538: */ ! 539: typedef struct _OperatingReg ! 540: { ! 541: UCHAR SCSICtrl0; /*; (+00)*/ ! 542: UCHAR SCSICtrl1; /*; (+01)*/ ! 543: UCHAR SCSICtrl2; /*; (+02)*/ ! 544: UCHAR SCSICtrl3; /*; (+03)*/ ! 545: UCHAR SCSIChipID; /*; (+04)*/ ! 546: UCHAR SCSIXfer; /*; (+05)*/ ! 547: UCHAR SCSIDestID; /*; (+06)*/ ! 548: UCHAR GeneralPReg; /*; (+07)*/ ! 549: UCHAR SCSI1stByteR; /*; (+08)*/ ! 550: UCHAR SCSIOPCtrlL; /*; (+09)*/ ! 551: UCHAR SCSISelID; /*; (+0A)*/ ! 552: UCHAR SCSIBusCtrlLin; /*; (+0B)*/ ! 553: UCHAR DMAStatus; /*; (+0C)*/ ! 554: UCHAR SCSIStatus0; /*; (+0D)*/ ! 555: UCHAR SCSIStatus1; /*; (+0E)*/ ! 556: UCHAR SCSIStatus2; /*; (+0F)*/ ! 557: ULONG DataStrucAddr; /*; (+10)*/ ! 558: UCHAR InterruptStatus;/*; (+14)*/ ! 559: UCHAR Reser1; /*; (+15)*/ ! 560: UCHAR Reser2; /*; (+16)*/ ! 561: UCHAR Reser3; /*; (+17)*/ ! 562: UCHAR ChipTest0; /*; (+18)*/ ! 563: UCHAR ChipTest1; /*; (+19)*/ ! 564: UCHAR ChipTest2; /*; (+1A)*/ ! 565: UCHAR ChipTest3; /*; (+1B)*/ ! 566: ULONG TempStack; /*; (+1C)*/ ! 567: UCHAR DMAFIFO; /*; (+20)*/ ! 568: UCHAR ChipTest4; /*; (+21)*/ ! 569: UCHAR ChipTest5; /*; (+22)*/ ! 570: UCHAR ChipTest6; /*; (+23)*/ ! 571: UCHAR DMAByteCnt[3]; /*; (+24)*/ ! 572: UCHAR DMACommand; /*; (+27)*/ ! 573: ULONG DMANextAddr; /*; (+28)*/ ! 574: ULONG DMAScriptsPtr; /*; (+2C)*/ ! 575: ULONG DMAScriptPtrSav;/*; (+30)*/ ! 576: ULONG ScratchA; /*; (+34)*/ ! 577: UCHAR DMAMode; /*; (+38)*/ ! 578: UCHAR DMAIntEnable; /*; (+39)*/ ! 579: UCHAR DMAWatchDog; /*; (+3A)*/ ! 580: UCHAR DMACtrl; /*; (+3B)*/ ! 581: ULONG ADDer; /*; (+3C)*/ ! 582: UCHAR SCSIIntEnable0; /*; (+40)*/ ! 583: UCHAR SCSIIntEnable1; /*; (+41)*/ ! 584: UCHAR SCSIIntStatus0; /*; (+42)*/ ! 585: UCHAR SCSIIntStatus1; /*; (+43)*/ ! 586: UCHAR SCSILongParity; /*; (+44)*/ ! 587: UCHAR WideResiData; /*; (+45)*/ ! 588: UCHAR MemAccessCtrl; /*; (+46)*/ ! 589: UCHAR GeneralPCtrl; /*; (+47)*/ ! 590: UCHAR SCSITimer0; /*; (+48)*/ ! 591: UCHAR SCSITimer1; /*; (+49)*/ ! 592: UCHAR ResponseID0; /*; (+4A)*/ ! 593: UCHAR ResponseID1; /*; (+4B)*/ ! 594: UCHAR SCSITest0; /*; (+4C)*/ ! 595: UCHAR SCSITest1; /*; (+4D)*/ ! 596: UCHAR SCSITest2; /*; (+4E)*/ ! 597: UCHAR SCSITest3; /*; (+4F)*/ ! 598: USHORT SCSIIPDataL; /*; (+50)*/ ! 599: USHORT Reser4; /*; (+52)*/ ! 600: USHORT SCSIOPDataL; /*; (+54)*/ ! 601: USHORT Reser5; /*; (+56)*/ ! 602: USHORT SCSIBusDataLin; /*; (+58)*/ ! 603: USHORT Reser6; /*; (+5A)*/ ! 604: ULONG ScratchB; /*; (+5C)*/ ! 605: ULONG ScratchC; /*; (+60)*/ ! 606: ULONG ScratchD; /*; (+64)*/ ! 607: ULONG ScratchE; /*; (+68)*/ ! 608: ULONG ScratchF; /*; (+6C)*/ ! 609: ULONG ScratchG; /*; (+70)*/ ! 610: ULONG ScratchH; /*; (+74)*/ ! 611: ULONG ScratchI; /*; (+78)*/ ! 612: ULONG ScratchJ; /*; (+7C)*/ ! 613: } OperatingReg; ! 614: /* ! 615: ;========================================================== ! 616: ; NCR 53C825 Registers bit Definition ! 617: ;========================================================== ! 618: */ ! 619: /*; SCSICtrl0 (+00)*/ ! 620: #define FULL_ARBITRATION (BIT7+BIT6) ! 621: #define START_ARBIT BIT5 ! 622: #define SEL_W_SATN BIT4 ! 623: #define EN_PARITY_CHK BIT3 ! 624: #define SATN_IF_PARITY_ERR BIT1 ! 625: #define TARGET_MODE BIT0 ! 626: ! 627: /*; SCSICtrl1 (+01)*/ ! 628: #define ASSERT_RST BIT3 ! 629: #define ASSERT_EVEN_P BIT2 ! 630: #define START_SCSI_XFER BIT0 ! 631: ! 632: /*; SCSICtrl2 (+02)*/ ! 633: #define DISC_UNEXPECTED BIT7 ! 634: #define CHAIN_MODE BIT6 ! 635: #define WIDE_SCSI_SEND BIT3 ! 636: #define WIDE_SCSI_RECV BIT0 ! 637: ! 638: /*; SCSICtrl3 (+03)*/ ! 639: #define EN_FAST_20 BIT7 ! 640: #define SYNC_CLK_F4 (BIT6+BIT4) ! 641: #define SYNC_CLK_F3 BIT6 ! 642: #define SYNC_CLK_F2 (BIT5+BIT4) ! 643: #define SYNC_CLK_F1_5 BIT5 ! 644: #define SYNC_CLK_F1 BIT4 ! 645: #define EN_WIDE_SCSI BIT3 ! 646: #define ASYNC_CLK_F4 (BIT2+BIT0) ! 647: #define ASYNC_CLK_F3 BIT2 ! 648: #define ASYNC_CLK_F2 (BIT1+BIT0) ! 649: #define ASYNC_CLK_F1_5 BIT1 ! 650: #define ASYNC_CLK_F1 BIT0 ! 651: ! 652: /*; SCSIChipID (+04)*/ ! 653: #define ENABLE_RESEL BIT6 ! 654: #define ENABLE_SEL BIT5 ! 655: #define CHIP_ID_MASK 0FH ! 656: ! 657: /*; SCSIXfer (+05)*/ ! 658: #define PERIOD_MASK (BIT7+BIT6+BIT5) ! 659: #define SYNC_PERIOD_F11 (BIT7+BIT6+BIT5) ! 660: #define SYNC_PERIOD_F10 (BIT7+BIT6) ! 661: #define SYNC_PERIOD_F9 (BIT7+BIT5) ! 662: #define SYNC_PERIOD_F8 BIT7 ! 663: #define SYNC_PERIOD_F7 (BIT6+BIT5) ! 664: #define SYNC_PERIOD_F6 BIT6 ! 665: #define SYNC_PERIOD_F5 BIT5 ! 666: #define SYNC_PERIOD_F4 0 ! 667: #define OFFSET_MASK (BIT4+BIT3+BIT2+BIT1+BIT0) ! 668: #define SYNC_OFFSET_16 BIT4 ! 669: #define SYNC_OFFSET_8 BIT3 ! 670: #define SYNC_OFFSET_7 (BIT2+BIT1+BIT0) ! 671: #define SYNC_OFFSET_6 (BIT2+BIT1) ! 672: #define SYNC_OFFSET_5 (BIT2+BIT0) ! 673: #define SYNC_OFFSET_4 BIT2 ! 674: #define SYNC_OFFSET_3 (BIT1+BIT0) ! 675: #define SYNC_OFFSET_2 BIT1 ! 676: #define SYNC_OFFSET_1 BIT0 ! 677: #define SYNC_OFFSET_0 0 ! 678: #define ASYNCHRONOUS SYNC_OFFSET_0 ! 679: /* ! 680: ; SCSIDestID (+06) ! 681: ! 682: ; GeneralPReg (+07) ! 683: ! 684: ; SCSI1stByteR (+08) ! 685: */ ! 686: /*; SCSIOPCtrlL (+09)*/ ! 687: #define ASSERT_REQ BIT7 ! 688: #define ASSERT_ACK BIT6 ! 689: #define ASSERT_BSY BIT5 ! 690: #define ASSERT_SEL BIT4 ! 691: #define ASSERT_ATN BIT3 ! 692: #define ASSERT_MSG BIT2 ! 693: #define ASSERT_C_D BIT1 ! 694: #define ASSERT_I_O BIT0 ! 695: ! 696: /*; SCSISelID (+0A) Read*/ ! 697: #define SCSI_ID_VALID BIT7 ! 698: ! 699: /*; SCSIBusCtrlLin (+0B) Read*/ ! 700: #define REQ_SIGNAL BIT7 ! 701: #define ACK_SIGNAL BIT6 ! 702: #define BSY_SIGNAL BIT5 ! 703: #define SEL_SIGNAL BIT4 ! 704: #define ATN_SIGNAL BIT3 ! 705: #define MSG_SIGNAL BIT2 ! 706: #define C_D_SIGNAL BIT1 ! 707: #define I_O_SIGNAL BIT0 ! 708: ! 709: /*; DMAStatus (+0C) Read*/ ! 710: #define DMA_FIFO_EMPTY BIT7 ! 711: #define MASTER_PARITY_ERR BIT6 ! 712: #define BUS_FAULT BIT5 ! 713: #define ABORT_ BIT4 ! 714: #define SINGLE_STEP_INT BIT3 ! 715: #define SCRIPTS_INT BIT2 ! 716: #define ILLEGAL_INSTRUC BIT0 ! 717: ! 718: /*; SCSIStatus0 (+0D) Read*/ ! 719: #define SIDL_LSB_FULL BIT7 ! 720: #define SODR_LSB_FULL BIT6 ! 721: #define SODL_LSB_FULL BIT5 ! 722: #define IN_ARBITRATION BIT4 ! 723: #define LOST_ARBITRATION BIT3 ! 724: #define WIN_ARBITRATION BIT2 ! 725: #define RST_SIGNAL BIT1 ! 726: #define PARITY_SIGNAL BIT0 ! 727: ! 728: /*; SCSIStatus1 (+0E) Read*/ ! 729: #define SCSI_FIFO_MASK (BIT7+BIT6+BIT5+BIT4) ! 730: ! 731: /*; SCSIStatus2 (+0F) Read*/ ! 732: #define SIDL_MSB_FULL BIT7 ! 733: #define SODR_MSB_FULL BIT6 ! 734: #define SODL_MSB_FULL BIT5 ! 735: #define SCSI_FIFO_MSB BIT4 ! 736: ! 737: /*; DataStrucAddr (+10)*/ ! 738: ! 739: /*; InterruptStatus (+14)*/ ! 740: #define ABORT_OP BIT7 ! 741: #define SOFTWARE_RST BIT6 ! 742: #define SIGNAL_PROC BIT5 ! 743: #define SEMAPHORE BIT4 ! 744: #define CONNECTED BIT3 ! 745: #define INT_ON_FLY BIT2 ! 746: #define SCSI_INT_PENDING BIT1 ! 747: #define DMA_INT_PENDING BIT0 ! 748: ! 749: /*; ChipTest0 (+18)*/ ! 750: /*; ChipTest1 (+19)*/ ! 751: #define FIFO_BYTE_EMPTY (BIT7+BIT6+BIT5+BIT4) ! 752: #define FIFO_BYTE_FULL (BIT3+BIT2+BIT1+BIT0) ! 753: ! 754: /*; ChipTest2 (+1A)*/ ! 755: #define READ_DIR BIT7 ! 756: #define WRITE_DIR 0 ! 757: #define SIGNAL_PROC_ BIT6 ! 758: #define CFG_AS_IO_MAP BIT5 ! 759: #define CFG_AS_MEM_MAP BIT4 ! 760: #define SCRATCHAB_AS_BASE BIT3 ! 761: #define TRUE_EOP BIT2 ! 762: #define INTERNAL_DREQ BIT1 ! 763: #define INTERNAL_DACK BIT0 ! 764: ! 765: /*; ChipTest3 (+1B)*/ ! 766: #define CHIP_REV_MASK (BIT7+BIT6+BIT5+BIT4) ! 767: #define FLUSH_DMA_FIFO BIT3 ! 768: #define CLR_DMA_FIFO BIT2 ! 769: #define FETCH_PIN_MODE BIT1 ! 770: #define WRT_EN_INVALIDATE BIT0 ! 771: ! 772: /*; TempStack (+1C)*/ ! 773: ! 774: /*; DMAFIFO (+20)*/ ! 775: /*; 2 upper bits in ChipTest5*/ ! 776: ! 777: /*; ChipTest4 (+21)*/ ! 778: #define BURST_DISABLE BIT7 ! 779: ! 780: /*; ChipTest5 (+22) */ ! 781: #define EN_DMA_FIFO_536 BIT5 ! 782: #define BURST_LEN_MSB BIT2 ! 783: #define DMAFIFO_MS2B (BIT1+BIT0) ! 784: /* ! 785: ; ChipTest6 (+23) ! 786: ; DMAByteCnt (+24) ! 787: ; DMACommand (+27) ! 788: ; DMANextAddr (+28) ! 789: ; DMAScriptsPtr (+2C) ! 790: ; DMAScriptPtrSav (+30) ! 791: */ ! 792: /*; ScratchA (+34)*/ ! 793: #define COMPLETED_OK_ BIT0 ! 794: #define RE_SELECTED_ BIT1 ! 795: #define OVER_RUN_ BIT2 ! 796: ! 797: /*; DMAMode (+38)*/ ! 798: #define BURST_LEN16 (BIT7+BIT6) ! 799: #define BURST_LEN8 BIT7 ! 800: #define BURST_LEN4 BIT6 ! 801: #define BURST_LEN2 0 ! 802: #define SRC_IO_MAP BIT5 ! 803: #define SRC_MEM_MAP 0 ! 804: #define DEST_IO_MAP BIT4 ! 805: #define DEST_MEM_MAP 0 ! 806: #define EN_READ_LINE BIT3 ! 807: #define EN_READ_MULTIPLE BIT2 ! 808: #define BURST_OPCODE_FETCH BIT1 ! 809: #define MANUAL_START BIT0 ! 810: #define AUTO_START 0 ! 811: ! 812: /*; DMAIntEnable (+39)*/ ! 813: #define EN_MDPE BIT6 ! 814: #define EN_BUS_FAULT BIT5 ! 815: #define EN_ABORTED BIT4 ! 816: #define EN_SINGLE_STEP BIT3 ! 817: #define EN_SCRIPT_INT BIT2 ! 818: #define EN_ILLEGAL_INST BIT0 ! 819: ! 820: ! 821: /*; DMAWatchDog (+3A)*/ ! 822: ! 823: /*; DMACtrl (+3B)*/ ! 824: #define EN_CACHE_LINE_SIZE BIT7 ! 825: #define PRE_FETCH_FLUSH BIT6 ! 826: #define EN_PRE_FETCH BIT5 ! 827: #define SINGLE_STEP_MIDE BIT4 ! 828: #define TOTEM_POLE_IRQ BIT3 ! 829: #define OPEN_DRAIN_IRQ 0 ! 830: #define START_DMA BIT2 ! 831: #define IRQ_DISABLE BIT1 ! 832: #define COMPATIBLE_700 BIT0 ! 833: ! 834: /*; ADDer (+3C)*/ ! 835: ! 836: /*; SCSIIntEnable0 (+40)*/ ! 837: #define EN_PHASE_MISMATCH BIT7 ! 838: #define EN_ARB_SEL_DONE BIT6 ! 839: #define EN_BE_SELECTED BIT5 ! 840: #define EN_BE_RESELECTED BIT4 ! 841: #define EN_SCSI_GERROR BIT3 ! 842: #define EN_UNEXPECT_DISC BIT2 ! 843: #define EN_SCSI_RESET BIT1 ! 844: #define EN_PARITY_ERROR BIT0 ! 845: ! 846: /*; SCSIIntEnable1 (+41)*/ ! 847: #define EN_SEL_TIMEOUT BIT2 ! 848: #define EN_GENERAL_TIMEOUT BIT1 ! 849: #define EN_HANDSHAKE_TIMEOUT BIT0 ! 850: ! 851: /*; SCSIIntStatus0 (+42)*/ ! 852: #define PHASE_MISMATCH BIT7 ! 853: #define ARB_SEL_DONE BIT6 ! 854: #define BE_SELECTED BIT5 ! 855: #define BE_RESELECTED BIT4 ! 856: #define SCSI_GERROR BIT3 ! 857: #define UNEXPECT_DISC BIT2 ! 858: #define SCSI_RESET BIT1 ! 859: #define PARITY_ERROR BIT0 ! 860: ! 861: /*; SCSIIntStatus1 (+43)*/ ! 862: #define SEL_TIMEOUT BIT2 ! 863: #define GENERAL_TIMEOUT BIT1 ! 864: #define HANDSHAKE_TIMEOUT BIT0 ! 865: /* ! 866: ; SCSILongParity (+44) ! 867: ; WideResiData (+45) ! 868: ; MemAccessCtrl (+46) ! 869: ; GeneralPCtrl (+47) ! 870: */ ! 871: /*; SCSITimer0 (+48)*/ ! 872: #define HTH_TO_DISABLE 0 ! 873: #define SEL_TO_204ms (BIT3+BIT2) ! 874: /* ! 875: ; SCSITimer1 (+49) ! 876: ; ResponseID0 (+4A) ! 877: ; ResponseID1 (+4B) ! 878: ; SCSITest0 (+4C) ! 879: ; SCSITest1 (+4D) ! 880: ; SCSITest2 (+4E) ! 881: */ ! 882: /*; SCSITest3 (+4F)*/ ! 883: #define ACTIVE_NEGATION_ BIT7 ! 884: #define FIFO_TEST_READ BIT6 ! 885: #define HALT_SCSI_CLK BIT5 ! 886: #define DIS_SINGLE_INIT BIT4 ! 887: #define TIMER_TEST_MODE BIT2 ! 888: #define CLR_SCSI_FIFO BIT1 ! 889: #define FIFO_TEST_WRITE BIT0 ! 890: /* ! 891: ; SCSIIPDataL (+50) ! 892: ; SCSIOPDataL (+54) ! 893: ; SCSIBusDataLin (+58) ! 894: ; ScratchB (+5C) ! 895: ; ScratchC (+60) ! 896: ; ScratchD (+64) ! 897: ; ScratchE (+68) ! 898: ; ScratchF (+6C) ! 899: ; ScratchG (+70) ! 900: ; ScratchH (+74) ! 901: ; ScratchI (+78) ! 902: ; ScratchJ (+7C) ! 903: */ ! 904: ! 905: /*********************************************************************** ! 906: * NCR53C825 I/O Address Map ! 907: * base address is stored at offset 0x10 in the PCI configuration space ! 908: *----------------------------------------------------------------------- ! 909: * SCSI Core Registers Offset ! 910: ***********************************************************************/ ! 911: #define SCNTL0 0x00 /* Scsi Control 0 R/W */ ! 912: #define SCNTL1 0x01 /* Scsi Control 1 R/W */ ! 913: #define SCNTL2 0x02 /* Scsi Control 2 R/W */ ! 914: #define SCNTL3 0x03 /* Scsi Control 3 R/W */ ! 915: #define SCID 0x04 /* Scsi Chip ID R/W */ ! 916: #define SXFER 0x05 /* Scsi Transfer R/W */ ! 917: #define SDID 0x06 /* Scsi Destination ID R/W */ ! 918: #define GPREG 0x07 /* General Purpose Bits R/W */ ! 919: #define SFBR 0x08 /* Scsi First Byte Received R/W */ ! 920: #define SOCL 0x09 /* Scsi Output Control Latch R/W */ ! 921: #define SSID 0x0A /* Scsi Selector ID R */ ! 922: #define SBCL 0x0B /* Scsi Bus Control Lines R/W */ ! 923: #define DSTAT 0x0C /* DMA Status R */ ! 924: #define SSTAT0 0x0D /* Scsi Status 0 R */ ! 925: #define SSTAT1 0x0E /* Scsi Status 1 R */ ! 926: #define SSTAT2 0x0F /* Scsi Status 2 R */ ! 927: #define DSA 0x10 /* Data Structure Address R/W */ ! 928: #define ISTAT 0x14 /* Interrupt Status R/W */ ! 929: #define RES15 0x15 /* Reserved */ ! 930: #define CTEST0 0x18 /* Reserved */ ! 931: #define CTEST1 0x19 /* Chip Test 1 R/W */ ! 932: #define CTEST2 0x1A /* Chip Test 2 R */ ! 933: #define CTEST3 0x1B /* Chip Test 3 R */ ! 934: #define TEMP 0x1C /* Temperary Stack R/W */ ! 935: #define DFIFO 0x20 /* DMA FIFO R/W */ ! 936: #define CTEST4 0x21 /* Chip Test 4 R/W */ ! 937: #define CTEST5 0x22 /* Chip Test 5 R/W */ ! 938: #define CTEST6 0x23 /* Chip Test 6 R/W */ ! 939: #define DBC 0x24 /* DMA Byte Counter R/W */ ! 940: #define DCMD 0x27 /* DMA Command R/W */ ! 941: #define DNAD 0x28 /* DMA Next Address For Data R/W */ ! 942: #define DSP 0x2C /* DMA SCIPTS Pointer R/W */ ! 943: #define DSPS 0x30 /* DMA SCIPTS Pointer Saves R/W */ ! 944: #define SCRATCHA 0x34 /* General Purpose Scratch Pad A R/W */ ! 945: #define DMODE 0x38 /* DMA Mode R/W */ ! 946: #define DIEN 0x39 /* DMA Interrupt Enable R/W */ ! 947: #define DWT 0x3A /* DMA Watchdog Timer R/W */ ! 948: #define DCNTL 0x3B /* DMA Control R/W */ ! 949: #define ADDER 0x3C /* Sum output of Internal adder R */ ! 950: #define SIEN0 0x40 /* Scsi Interrupt Enable 0 R/W */ ! 951: #define SIEN1 0x41 /* Scsi Interrupt Enable 1 R/W */ ! 952: #define SIST0 0x42 /* Scsi Interrupt Status 0 R */ ! 953: #define SIST1 0x43 /* Scsi Interrupt Status 1 R */ ! 954: #define SLPAR 0x44 /* Scsi Longitudinal Parity R/W */ ! 955: #define SWIDE 0x45 /* Reserved */ ! 956: #define MACNTL 0x46 /* Memory Access Control R/W */ ! 957: #define GPCNTL 0x47 /* General Purpose Control R/W */ ! 958: #define STIME0 0x48 /* Scsi Timer 0 R/W */ ! 959: #define STIME1 0x49 /* Scsi Timer 1 R/W */ ! 960: #define RESPID0 0x4A /* Response ID 0 R/W */ ! 961: #define RESPID1 0x4B /* Response ID 1 R/W */ ! 962: #define STEST0 0x4C /* Scsi Test 0 R */ ! 963: #define STEST1 0x4D /* Scsi Test 1 R */ ! 964: #define STEST2 0x4E /* Scsi Test 2 R/W */ ! 965: #define STEST3 0x4F /* Scsi Test 3 R/W */ ! 966: #define SIDL 0x50 /* Scsi Input Data Latch R */ ! 967: #define RES51 0x51 /* Reserved */ ! 968: #define SODL 0x54 /* Scsi Output Data Latch R/W */ ! 969: #define RES55 0x55 /* Reserved */ ! 970: #define SBDL 0x58 /* Scsi Bus Data Lines R */ ! 971: #define RES59 0x59 /* Reserved */ ! 972: #define SCRATCHB 0x5C /* General Purpose Scratch Pad B R/W */ ! 973: ! 974: ! 975: /* ! 976: ;========================================================== ! 977: ; structure for 53C825A register ( I/O ) ! 978: ;========================================================== ! 979: */ ! 980: #define __scntl0 0 ! 981: #define __scntl1 1 ! 982: #define __scntl2 2 ! 983: #define __scntl3 3 ! 984: #define __scid 4 ! 985: #define __sxfer 5 ! 986: #define __sdid 6 ! 987: #define __gpreg 7 ! 988: #define __sfbr 8 ! 989: #define __socl 9 ! 990: #define __ssid 0x0A ! 991: #define __sbcl 0x0B ! 992: #define __dstat 0x0C ! 993: #define __sstat0 0x0D ! 994: #define __sstat1 0x0E ! 995: #define __sstat2 0x0F ! 996: #define __dsa 0x10 ! 997: #define __istat 0x14 ! 998: /*#define 0x15*/ ! 999: #define __ctest0 0x18 ! 1000: #define __ctest1 0x19 ! 1001: #define __ctest2 0x1A ! 1002: #define __ctest3 0x1B ! 1003: #define __temp 0x1C ! 1004: #define __dfifo 0x20 ! 1005: #define __ctest4 0x21 ! 1006: #define __ctest5 0x22 ! 1007: #define __ctest6 0x23 ! 1008: #define __dbc 0x24 ! 1009: #define __dcmd 0x27 ! 1010: #define __dnad 0x28 ! 1011: #define __dsp 0x2C ! 1012: #define __dsps 0x30 ! 1013: #define __scratcha 0x34 ! 1014: #define __dmode 0x38 ! 1015: #define __dien 0x39 ! 1016: #define __dwt 0x3A ! 1017: #define __dcntl 0x3B ! 1018: #define __adder 0x3C ! 1019: #define __sien0 0x40 ! 1020: #define __sien1 0x41 ! 1021: #define __sist0 0x42 ! 1022: #define __sist1 0x43 ! 1023: #define __slpar 0x44 ! 1024: #define __swide 0x45 ! 1025: #define __mactrl 0x46 ! 1026: #define __gpctrl 0x47 ! 1027: #define __stime0 0x48 ! 1028: #define __stime1 0x49 ! 1029: #define __respid0 0x4A ! 1030: #define __respid1 0x4B ! 1031: #define __stest0 0x4C ! 1032: #define __stest1 0x4D ! 1033: #define __stest2 0x4E ! 1034: #define __stest3 0x4F ! 1035: #define __sidl 0x50 /*; For wide SCSI, this register*/ ! 1036: /*#define 0x51 ; contains 2 bytes*/ ! 1037: #define __sodl 0x54 ! 1038: /*#define 0x55*/ ! 1039: #define __sbdl 0x58 ! 1040: /*#define 0x59*/ ! 1041: #define __scratchb 0x5C ! 1042: /* ! 1043: ;========================================================== ! 1044: ; Script interrupt code(Vector) ! 1045: ;========================================================== ! 1046: */ ! 1047: #define __COMPLETE 0 /*; command complete*/ ! 1048: #define __RESELECTED 1 /*; reselected, without MESSAGE*/ ! 1049: #define __RESELECTED1 2 /*; reselected with idenntify bytes*/ ! 1050: #define __RESELECTEDT 3 /*; reselected with TAGS*/ ! 1051: #define __DISCONNECTED 4 /*; disconnected*/ ! 1052: #define __MSGEXTEND 5 /*; Extended msgin*/ ! 1053: #define __SIGNAL 6 /*; signaled, need to clear SIG*/ ! 1054: #define __MSGUNKNOWN 7 /*; Unknown message*/ ! 1055: #define __MSGOUT 8 /*; Message out phase detected*/ ! 1056: #define __FATALERROR 9 /*; Fatal error*/ ! 1057: #define __MSGSYNC 10 /*; Sync nego input*/ ! 1058: #define __MSGWIDE 11 /*; Wide nego input*/ ! 1059: #define __RESTOREPTR 12 /*; restore pointer received*/ ! 1060: #define __MSGREJECT 13 /*; Reject message received*/ ! 1061: #define __DEBUG 14 /*; For debug*/ ! 1062: ! 1063: ! 1064: #define DC390W_read8(address) \ ! 1065: inb(DC390W_ioport + (address))) ! 1066: ! 1067: #define DC390W_read16(address) \ ! 1068: inw(DC390W_ioport + (address))) ! 1069: ! 1070: #define DC390W_read32(address) \ ! 1071: inl(DC390W_ioport + (address))) ! 1072: ! 1073: #define DC390W_write8(address,value) \ ! 1074: outb((value), DC390W_ioport + (address))) ! 1075: ! 1076: #define DC390W_write16(address,value) \ ! 1077: outw((value), DC390W_ioport + (address))) ! 1078: ! 1079: #define DC390W_write32(address,value) \ ! 1080: outl((value), DC390W_ioport + (address))) ! 1081: ! 1082: #endif /* TMSCSIW_H */
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