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Annotation of Gnu-Mach/linux/src/include/asm-i386/dma.h, revision 1.1

1.1     ! root        1: /* $Id: dma.h,v 1.1 1999/04/26 05:55:43 tb Exp $
        !             2:  * linux/include/asm/dma.h: Defines for using and allocating dma channels.
        !             3:  * Written by Hennus Bergman, 1992.
        !             4:  * High DMA channel support & info by Hannu Savolainen
        !             5:  * and John Boyd, Nov. 1992.
        !             6:  */
        !             7: 
        !             8: #ifndef _ASM_DMA_H
        !             9: #define _ASM_DMA_H
        !            10: 
        !            11: #include <asm/io.h>            /* need byte IO */
        !            12: 
        !            13: 
        !            14: #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
        !            15: #define dma_outb       outb_p
        !            16: #else
        !            17: #define dma_outb       outb
        !            18: #endif
        !            19: 
        !            20: #define dma_inb                inb
        !            21: 
        !            22: /*
        !            23:  * NOTES about DMA transfers:
        !            24:  *
        !            25:  *  controller 1: channels 0-3, byte operations, ports 00-1F
        !            26:  *  controller 2: channels 4-7, word operations, ports C0-DF
        !            27:  *
        !            28:  *  - ALL registers are 8 bits only, regardless of transfer size
        !            29:  *  - channel 4 is not used - cascades 1 into 2.
        !            30:  *  - channels 0-3 are byte - addresses/counts are for physical bytes
        !            31:  *  - channels 5-7 are word - addresses/counts are for physical words
        !            32:  *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
        !            33:  *  - transfer count loaded to registers is 1 less than actual count
        !            34:  *  - controller 2 offsets are all even (2x offsets for controller 1)
        !            35:  *  - page registers for 5-7 don't use data bit 0, represent 128K pages
        !            36:  *  - page registers for 0-3 use bit 0, represent 64K pages
        !            37:  *
        !            38:  * DMA transfers are limited to the lower 16MB of _physical_ memory.  
        !            39:  * Note that addresses loaded into registers must be _physical_ addresses,
        !            40:  * not logical addresses (which may differ if paging is active).
        !            41:  *
        !            42:  *  Address mapping for channels 0-3:
        !            43:  *
        !            44:  *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
        !            45:  *    |  ...  |   |  ... |   |  ... |
        !            46:  *    |  ...  |   |  ... |   |  ... |
        !            47:  *    |  ...  |   |  ... |   |  ... |
        !            48:  *   P7  ...  P0  A7 ... A0  A7 ... A0   
        !            49:  * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
        !            50:  *
        !            51:  *  Address mapping for channels 5-7:
        !            52:  *
        !            53:  *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
        !            54:  *    |  ...  |   \   \   ... \  \  \  ... \  \
        !            55:  *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
        !            56:  *    |  ...  |     \   \   ... \  \  \  ... \
        !            57:  *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0   
        !            58:  * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
        !            59:  *
        !            60:  * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
        !            61:  * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
        !            62:  * the hardware level, so odd-byte transfers aren't possible).
        !            63:  *
        !            64:  * Transfer count (_not # bytes_) is limited to 64K, represented as actual
        !            65:  * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
        !            66:  * and up to 128K bytes may be transferred on channels 5-7 in one operation. 
        !            67:  *
        !            68:  */
        !            69: 
        !            70: #define MAX_DMA_CHANNELS       8
        !            71: 
        !            72: /* The maximum address that we can perform a DMA transfer to on this platform */
        !            73: #define MAX_DMA_ADDRESS      0x1000000
        !            74: 
        !            75: /* 8237 DMA controllers */
        !            76: #define IO_DMA1_BASE   0x00    /* 8 bit slave DMA, channels 0..3 */
        !            77: #define IO_DMA2_BASE   0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
        !            78: 
        !            79: /* DMA controller registers */
        !            80: #define DMA1_CMD_REG           0x08    /* command register (w) */
        !            81: #define DMA1_STAT_REG          0x08    /* status register (r) */
        !            82: #define DMA1_REQ_REG            0x09    /* request register (w) */
        !            83: #define DMA1_MASK_REG          0x0A    /* single-channel mask (w) */
        !            84: #define DMA1_MODE_REG          0x0B    /* mode register (w) */
        !            85: #define DMA1_CLEAR_FF_REG      0x0C    /* clear pointer flip-flop (w) */
        !            86: #define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
        !            87: #define DMA1_RESET_REG         0x0D    /* Master Clear (w) */
        !            88: #define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
        !            89: #define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
        !            90: 
        !            91: #define DMA2_CMD_REG           0xD0    /* command register (w) */
        !            92: #define DMA2_STAT_REG          0xD0    /* status register (r) */
        !            93: #define DMA2_REQ_REG            0xD2    /* request register (w) */
        !            94: #define DMA2_MASK_REG          0xD4    /* single-channel mask (w) */
        !            95: #define DMA2_MODE_REG          0xD6    /* mode register (w) */
        !            96: #define DMA2_CLEAR_FF_REG      0xD8    /* clear pointer flip-flop (w) */
        !            97: #define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
        !            98: #define DMA2_RESET_REG         0xDA    /* Master Clear (w) */
        !            99: #define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
        !           100: #define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
        !           101: 
        !           102: #define DMA_ADDR_0              0x00    /* DMA address registers */
        !           103: #define DMA_ADDR_1              0x02
        !           104: #define DMA_ADDR_2              0x04
        !           105: #define DMA_ADDR_3              0x06
        !           106: #define DMA_ADDR_4              0xC0
        !           107: #define DMA_ADDR_5              0xC4
        !           108: #define DMA_ADDR_6              0xC8
        !           109: #define DMA_ADDR_7              0xCC
        !           110: 
        !           111: #define DMA_CNT_0               0x01    /* DMA count registers */
        !           112: #define DMA_CNT_1               0x03
        !           113: #define DMA_CNT_2               0x05
        !           114: #define DMA_CNT_3               0x07
        !           115: #define DMA_CNT_4               0xC2
        !           116: #define DMA_CNT_5               0xC6
        !           117: #define DMA_CNT_6               0xCA
        !           118: #define DMA_CNT_7               0xCE
        !           119: 
        !           120: #define DMA_PAGE_0              0x87    /* DMA page registers */
        !           121: #define DMA_PAGE_1              0x83
        !           122: #define DMA_PAGE_2              0x81
        !           123: #define DMA_PAGE_3              0x82
        !           124: #define DMA_PAGE_5              0x8B
        !           125: #define DMA_PAGE_6              0x89
        !           126: #define DMA_PAGE_7              0x8A
        !           127: 
        !           128: #define DMA_MODE_READ  0x44    /* I/O to memory, no autoinit, increment, single mode */
        !           129: #define DMA_MODE_WRITE 0x48    /* memory to I/O, no autoinit, increment, single mode */
        !           130: #define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
        !           131: 
        !           132: /* enable/disable a specific DMA channel */
        !           133: static __inline__ void enable_dma(unsigned int dmanr)
        !           134: {
        !           135:        if (dmanr<=3)
        !           136:                dma_outb(dmanr,  DMA1_MASK_REG);
        !           137:        else
        !           138:                dma_outb(dmanr & 3,  DMA2_MASK_REG);
        !           139: }
        !           140: 
        !           141: static __inline__ void disable_dma(unsigned int dmanr)
        !           142: {
        !           143:        if (dmanr<=3)
        !           144:                dma_outb(dmanr | 4,  DMA1_MASK_REG);
        !           145:        else
        !           146:                dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
        !           147: }
        !           148: 
        !           149: /* Clear the 'DMA Pointer Flip Flop'.
        !           150:  * Write 0 for LSB/MSB, 1 for MSB/LSB access.
        !           151:  * Use this once to initialize the FF to a known state.
        !           152:  * After that, keep track of it. :-)
        !           153:  * --- In order to do that, the DMA routines below should ---
        !           154:  * --- only be used while interrupts are disabled! ---
        !           155:  */
        !           156: static __inline__ void clear_dma_ff(unsigned int dmanr)
        !           157: {
        !           158:        if (dmanr<=3)
        !           159:                dma_outb(0,  DMA1_CLEAR_FF_REG);
        !           160:        else
        !           161:                dma_outb(0,  DMA2_CLEAR_FF_REG);
        !           162: }
        !           163: 
        !           164: /* set mode (above) for a specific DMA channel */
        !           165: static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
        !           166: {
        !           167:        if (dmanr<=3)
        !           168:                dma_outb(mode | dmanr,  DMA1_MODE_REG);
        !           169:        else
        !           170:                dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
        !           171: }
        !           172: 
        !           173: /* Set only the page register bits of the transfer address.
        !           174:  * This is used for successive transfers when we know the contents of
        !           175:  * the lower 16 bits of the DMA current address register, but a 64k boundary
        !           176:  * may have been crossed.
        !           177:  */
        !           178: static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
        !           179: {
        !           180:        switch(dmanr) {
        !           181:                case 0:
        !           182:                        dma_outb(pagenr, DMA_PAGE_0);
        !           183:                        break;
        !           184:                case 1:
        !           185:                        dma_outb(pagenr, DMA_PAGE_1);
        !           186:                        break;
        !           187:                case 2:
        !           188:                        dma_outb(pagenr, DMA_PAGE_2);
        !           189:                        break;
        !           190:                case 3:
        !           191:                        dma_outb(pagenr, DMA_PAGE_3);
        !           192:                        break;
        !           193:                case 5:
        !           194:                        dma_outb(pagenr & 0xfe, DMA_PAGE_5);
        !           195:                        break;
        !           196:                case 6:
        !           197:                        dma_outb(pagenr & 0xfe, DMA_PAGE_6);
        !           198:                        break;
        !           199:                case 7:
        !           200:                        dma_outb(pagenr & 0xfe, DMA_PAGE_7);
        !           201:                        break;
        !           202:        }
        !           203: }
        !           204: 
        !           205: 
        !           206: /* Set transfer address & page bits for specific DMA channel.
        !           207:  * Assumes dma flipflop is clear.
        !           208:  */
        !           209: static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
        !           210: {
        !           211:        set_dma_page(dmanr, a>>16);
        !           212:        if (dmanr <= 3)  {
        !           213:            dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
        !           214:             dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
        !           215:        }  else  {
        !           216:            dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
        !           217:            dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
        !           218:        }
        !           219: }
        !           220: 
        !           221: 
        !           222: /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
        !           223:  * a specific DMA channel.
        !           224:  * You must ensure the parameters are valid.
        !           225:  * NOTE: from a manual: "the number of transfers is one more
        !           226:  * than the initial word count"! This is taken into account.
        !           227:  * Assumes dma flip-flop is clear.
        !           228:  * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
        !           229:  */
        !           230: static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
        !           231: {
        !           232:         count--;
        !           233:        if (dmanr <= 3)  {
        !           234:            dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
        !           235:            dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
        !           236:         } else {
        !           237:            dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
        !           238:            dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
        !           239:         }
        !           240: }
        !           241: 
        !           242: 
        !           243: /* Get DMA residue count. After a DMA transfer, this
        !           244:  * should return zero. Reading this while a DMA transfer is
        !           245:  * still in progress will return unpredictable results.
        !           246:  * If called before the channel has been used, it may return 1.
        !           247:  * Otherwise, it returns the number of _bytes_ left to transfer.
        !           248:  *
        !           249:  * Assumes DMA flip-flop is clear.
        !           250:  */
        !           251: static __inline__ int get_dma_residue(unsigned int dmanr)
        !           252: {
        !           253:        unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
        !           254:                                         : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
        !           255: 
        !           256:        /* using short to get 16-bit wrap around */
        !           257:        unsigned short count;
        !           258: 
        !           259:        count = 1 + dma_inb(io_port);
        !           260:        count += dma_inb(io_port) << 8;
        !           261:        
        !           262:        return (dmanr<=3)? count : (count<<1);
        !           263: }
        !           264: 
        !           265: 
        !           266: /* These are in kernel/dma.c: */
        !           267: extern int request_dma(unsigned int dmanr, const char * device_id);    /* reserve a DMA channel */
        !           268: extern void free_dma(unsigned int dmanr);      /* release it again */
        !           269: 
        !           270: 
        !           271: #endif /* _ASM_DMA_H */

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