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Annotation of Net2/arch/amiga/dev/dmareg.h, revision 1.1

1.1     ! root        1: /*
        !             2:  * Copyright (c) 1982, 1990 The Regents of the University of California.
        !             3:  * All rights reserved.
        !             4:  *
        !             5:  * Redistribution and use in source and binary forms, with or without
        !             6:  * modification, are permitted provided that the following conditions
        !             7:  * are met:
        !             8:  * 1. Redistributions of source code must retain the above copyright
        !             9:  *    notice, this list of conditions and the following disclaimer.
        !            10:  * 2. Redistributions in binary form must reproduce the above copyright
        !            11:  *    notice, this list of conditions and the following disclaimer in the
        !            12:  *    documentation and/or other materials provided with the distribution.
        !            13:  * 3. All advertising materials mentioning features or use of this software
        !            14:  *    must display the following acknowledgement:
        !            15:  *     This product includes software developed by the University of
        !            16:  *     California, Berkeley and its contributors.
        !            17:  * 4. Neither the name of the University nor the names of its contributors
        !            18:  *    may be used to endorse or promote products derived from this software
        !            19:  *    without specific prior written permission.
        !            20:  *
        !            21:  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
        !            22:  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
        !            23:  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
        !            24:  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
        !            25:  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
        !            26:  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
        !            27:  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
        !            28:  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
        !            29:  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
        !            30:  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
        !            31:  * SUCH DAMAGE.
        !            32:  *
        !            33:  *     @(#)dmareg.h
        !            34:  */
        !            35: 
        !            36: /* Hardware layout of the A3000/A2091 SDMAC. This also contains the
        !            37:    registers for the sbic chip, but in favor of separating DMA and
        !            38:    scsi, the scsi-driver doesn't make use of this dependency */
        !            39: 
        !            40: #define v_char         volatile char
        !            41: #define        v_int           volatile int
        !            42: #define vu_char                volatile u_char
        !            43: #define vu_short       volatile u_short
        !            44: #define vu_int         volatile u_int
        !            45: 
        !            46: struct sdmac {
        !            47:        short           ________________pad0;
        !            48:        vu_short        DAWR;           /* DACK Width Register          WO */
        !            49: 
        !            50:        vu_int          WTC;            /* Word Transfer Count Register RW */
        !            51: 
        !            52:        short           ________________pad1;
        !            53:        vu_short        CNTR;           /* Control Register             RW */
        !            54: 
        !            55:        vu_int          ACR;            /* Address Count Register       RW */
        !            56: 
        !            57:        short           ________________pad2;
        !            58:        vu_short        ST_DMA;         /* Start DMA Transfers          RW-Strobe */
        !            59: 
        !            60:        short           ________________pad3;
        !            61:        vu_short        FLUSH;          /* Flush FIFO                   RW-Strobe */
        !            62: 
        !            63:        short           ________________pad4;
        !            64:        vu_short        CINT;           /* Clear Interrupts             RW-Strobe */
        !            65: 
        !            66:        short           ________________pad5;
        !            67:        vu_short        ISTR;           /* Interrupt Status Register    RO */
        !            68: 
        !            69:        int             ________________pad6[7];
        !            70: 
        !            71:        short           ________________pad7;
        !            72:        vu_short        SP_DMA;         /* Stop DMA Transfers           RW-Strobe */
        !            73: 
        !            74:        char            ________________pad8;
        !            75:        vu_char         SASR;           /* sbic asr */
        !            76: 
        !            77:        char            ________________pad9;
        !            78:        vu_char         SCMD;           /* sbic data */
        !            79: };
        !            80:        
        !            81: 
        !            82: 
        !            83: /* value to go into DAWR */
        !            84: #define DAWR_A3000     3       /* according to A3000T service-manual */
        !            85: 
        !            86: /* bits defined for CNTR */
        !            87: #define CNTR_TCEN      (1<<5)  /* Terminal Count Enable */
        !            88: #define CNTR_PREST     (1<<4)  /* Peripheral Reset (not implemented :-((( ) */
        !            89: #define CNTR_PDMD      (1<<3)  /* Peripheral Device Mode Select (1=SCSI,0=XT/AT) */
        !            90: #define CNTR_INTEN     (1<<2)  /* Interrupt Enable */
        !            91: #define CNTR_DDIR      (1<<1)  /* Device Direction. 1==read from host, write to periph */
        !            92: #define CNTR_IO_DX     (1<<0)  /* IORDY & CSX1 Polarity Select */
        !            93: 
        !            94: /* bits defined for ISTR */
        !            95: #define ISTR_INTX      (1<<8)  /* XT/AT Interrupt pending */
        !            96: #define ISTR_INT_F     (1<<7)  /* Interrupt Follow */
        !            97: #define ISTR_INTS      (1<<6)  /* SCSI Peripheral Interrupt */
        !            98: #define ISTR_E_INT     (1<<5)  /* End-Of-Process Interrupt */
        !            99: #define ISTR_INT_P     (1<<4)  /* Interrupt Pending */
        !           100: #define ISTR_UE_INT    (1<<3)  /* Under-Run FIFO Error Interrupt */
        !           101: #define ISTR_OE_INT    (1<<2)  /* Over-Run FIFO Error Interrupt */
        !           102: #define ISTR_FF_FLG    (1<<1)  /* FIFO-Full Flag */
        !           103: #define ISTR_FE_FLG    (1<<0)  /* FIFO-Empty Flag */
        !           104: 
        !           105: 
        !           106: #define        NDMA            1
        !           107: 

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