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1.1 root 1: /*
2: * Copyright (c) 1988 University of Utah.
3: * Copyright (c) 1982, 1990 The Regents of the University of California.
4: * All rights reserved.
5: *
6: * This code is derived from software contributed to Berkeley by
7: * the Systems Programming Group of the University of Utah Computer
8: * Science Department.
9: *
10: * Redistribution and use in source and binary forms, with or without
11: * modification, are permitted provided that the following conditions
12: * are met:
13: * 1. Redistributions of source code must retain the above copyright
14: * notice, this list of conditions and the following disclaimer.
15: * 2. Redistributions in binary form must reproduce the above copyright
16: * notice, this list of conditions and the following disclaimer in the
17: * documentation and/or other materials provided with the distribution.
18: * 3. All advertising materials mentioning features or use of this software
19: * must display the following acknowledgement:
20: * This product includes software developed by the University of
21: * California, Berkeley and its contributors.
22: * 4. Neither the name of the University nor the names of its contributors
23: * may be used to endorse or promote products derived from this software
24: * without specific prior written permission.
25: *
26: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36: * SUCH DAMAGE.
37: *
38: * from: Utah $Hdr: cpu.h 1.16 91/03/25$
39: *
40: * @(#)cpu.h 7.7 (Berkeley) 6/27/91
41: */
42:
43: /*
44: * Exported definitions unique to amiga/68k cpu support.
45: */
46:
47: /*
48: * definitions of cpu-dependent requirements
49: * referenced in generic code
50: */
51: #define COPY_SIGCODE /* copy sigcode above user stack in exec */
52:
53: /*
54: * function vs. inline configuration;
55: * these are defined to get generic functions
56: * rather than inline or machine-dependent implementations
57: */
58: #define NEED_MINMAX /* need {,i,l,ul}{min,max} functions */
59: #undef NEED_FFS /* don't need ffs function */
60: #undef NEED_BCMP /* don't need bcmp function */
61: #undef NEED_STRLEN /* don't need strlen function */
62:
63: #define cpu_exec(p) /* nothing */
64: #define cpu_wait(p) /* nothing */
65:
66: /*
67: * Arguments to hardclock, softclock and gatherstats
68: * encapsulate the previous machine state in an opaque
69: * clockframe; for hp300, use just what the hardware
70: * leaves on the stack.
71: */
72: typedef struct intrframe {
73: int pc;
74: int ps;
75: } clockframe;
76:
77: #define CLKF_USERMODE(framep) (((framep)->ps & PSL_S) == 0)
78: #define CLKF_BASEPRI(framep) (((framep)->ps & PSL_IPL7) == 0)
79: #define CLKF_PC(framep) ((framep)->pc)
80:
81:
82: /*
83: * Preempt the current process if in interrupt from user mode,
84: * or after the current trap/syscall if in system mode.
85: */
86: #define need_resched() { want_resched++; aston(); }
87:
88: /*
89: * Give a profiling tick to the current process from the softclock
90: * interrupt. On hp300, request an ast to send us through trap(),
91: * marking the proc as needing a profiling tick.
92: */
93: #define profile_tick(p, framep) { (p)->p_flag |= SOWEUPC; aston(); }
94:
95: /*
96: * Notify the current process (p) that it has a signal pending,
97: * process as soon as possible.
98: */
99: #define signotify(p) aston()
100:
101: #define aston() (astpending++)
102:
103: int astpending; /* need to trap before returning to user mode */
104: int want_resched; /* resched() was called */
105:
106:
107: /*
108: * simulated software interrupt register
109: */
110: extern unsigned char ssir;
111:
112: #define SIR_NET 0x1
113: #define SIR_CLOCK 0x2
114:
115: #define siroff(x) ssir &= ~(x)
116: #define setsoftnet() ssir |= SIR_NET
117: #define setsoftclock() ssir |= SIR_CLOCK
118:
119:
120: /*
121: * The rest of this should probably be moved to ../amiga/amigacpu.h,
122: * although some of it could probably be put into generic 68k headers.
123: */
124:
125: /* values for machineid (happen to be AFF_* settings of AttnFlags)
126: * NOTE: '40 support does NOT YET exist! */
127: #define AMIGA_68020 (1L<<1)
128: #define AMIGA_68030 (1L<<2)
129: #define AMIGA_68040 (1L<<3)
130: #define AMIGA_68881 (1L<<4)
131: #define AMIGA_68882 (1L<<5)
132: #define AMIGA_FPU40 (1L<<6)
133:
134:
135: /* values for mmutype (assigned for quick testing) */
136: #define MMU_68030 -1 /* 68030 on-chip subset of 68851 */
137: #define MMU_68851 1 /* Motorola 68851 */
138:
139: /* values for cpuspeed (not really related to clock speed due to caches) */
140: #define MHZ_8 1
141: #define MHZ_16 2
142: #define MHZ_25 3
143: #define MHZ_33 4
144: #define MHZ_50 6
145:
146: #ifdef KERNEL
147: extern int machineid, mmutype;
148: extern char *chipmembase, *chipmemlimit;
149: extern char *customchipbase, *customchiplimit;
150:
151: /* what is this supposed to do? i.e. how is it different than startrtclock?
152: #define enablertclock()
153:
154: Answer (MW): startrtclock is supposed to start the clock chip (to get an
155: accurate uptime, enablertclock is called later (after *vital* stuff
156: has been setup) to enable clock interrupts. Enabling clock interrupts
157: at startrtclock-time can get you into big troubles... */
158:
159: #endif
160:
161: /* physical memory sections */
162: #define CHIPMEMBASE (0x00000000)
163: /* maximum for mapping, not the whole range is needed in physical equivalence */
164: #define CHIPMEMTOP (0x00200000)
165: #define CHIPMEMSIZE btoc(CHIPMEMTOP-CHIPMEMBASE)
166: /* CIA-A and CIA-B */
167: #define CIABASE (0x00BFC000)
168: #define CIATOP (0x00C00000)
169: #define CIASIZE btoc(CIATOP-CIABASE)
170: #define CUSTOMBASE (0x00DFE000)
171: #define CUSTOMTOP (0x00E00000)
172: #define CUSTOMSIZE btoc(CUSTOMTOP-CUSTOMBASE)
173: #ifdef A3000
174: #define SCSIBASE (0x00DD0000)
175: #define SCSITOP (0x00DD0000+AMIGA_PAGE_SIZE)
176: #define SCSISIZE btoc(SCSITOP-SCSIBASE)
177: #endif
178:
179: /* XXX only correct for A3000 memory map!
180: * corresponds to address of last physical memory page, for A3000
181: * this is always 0x08000000 - pagesize (== NBPS)
182: */
183: #define MAXADDR (0x08000000 - UPAGES)
184:
185:
186: /* Amiga specific mappings:
187: *
188: * phys-start map-start phys-end map-end name
189: *
190: * 0x00000000 chipmembase - 0x00200000 chipmemlimit CHIP MEM
191: * 0x00be0000 ciabase - 0x00c00000 cialimit CIA-B/CIA-A
192: * 0x00d80000 customchipbase - 0x00f00000 customchiplimit CUSTOM/ZORRO2
193: */
194: #define ISCHIPMEM(va) \
195: ((char *)(va) >= chipmembase && (char *)(va) < chipmemlimit)
196: #define CHIPMEMV(pa) ((int)(pa)-CHIPMEMBASE+(int)chipmembase)
197: #define CHIPMEMP(va) ((int)(va)-(int)chipmembase+CHIPMEMBASE)
198: #define CHIPMEMPOFF(pa) ((int)(pa)-CHIPMEMBASE)
199: #define CHIPMEMMAPSIZE btoc(CHIPMEMTOP-CHIPMEMBASE) /* 2mb */
200:
201: #define ISCIA(va) \
202: ((char *)(va) >= ciabase && (char *)(va) < cialimit)
203: #define CIAV(pa) ((int)(pa)-CIABASE+(int)ciabase)
204: #define CIAP(va) ((int)(va)-(int)ciabase+CIABASE)
205: #define CIAPOFF(pa) ((int)(pa)-CIABASE)
206: #define CIAMAPSIZE btoc(CIATOP-CIABASE) /* 8k */
207:
208: #define ISCUSTOMCHIP(va) \
209: ((char *)(va) >= customchipbase && (char *)(va) < customchiplimit)
210: #define CUSTOMCHIPV(pa) ((int)(pa)-CUSTOMCHIPBASE+(int)customchipbase)
211: #define CUSTOMCHIPP(va) ((int)(va)-(int)customchipbase+CUSTOMCHIPBASE)
212: #define CUSTOMCHIPPOFF(pa) ((int)(pa)-CUSTOMCHIPBASE)
213: #define CUSTOMCHIPMAPSIZE btoc(CUSTOMCHIPTOP-CUSTOMCHIPBASE) /* 1.5mb */
214:
215:
216: /*
217: * 68851 and 68030 MMU
218: */
219: #define PMMU_LVLMASK 0x0007
220: #define PMMU_INV 0x0400
221: #define PMMU_WP 0x0800
222: #define PMMU_ALV 0x1000
223: #define PMMU_SO 0x2000
224: #define PMMU_LV 0x4000
225: #define PMMU_BE 0x8000
226: #define PMMU_FAULT (PMMU_WP|PMMU_INV)
227:
228: /* 680X0 function codes */
229: #define FC_USERD 1 /* user data space */
230: #define FC_USERP 2 /* user program space */
231: #define FC_SUPERD 5 /* supervisor data space */
232: #define FC_SUPERP 6 /* supervisor program space */
233: #define FC_CPU 7 /* CPU space */
234:
235: /* fields in the 68020 cache control register */
236: #define IC_ENABLE 0x0001 /* enable instruction cache */
237: #define IC_FREEZE 0x0002 /* freeze instruction cache */
238: #define IC_CE 0x0004 /* clear instruction cache entry */
239: #define IC_CLR 0x0008 /* clear entire instruction cache */
240:
241: /* additional fields in the 68030 cache control register */
242: #define IC_BE 0x0010 /* instruction burst enable */
243: #define DC_ENABLE 0x0100 /* data cache enable */
244: #define DC_FREEZE 0x0200 /* data cache freeze */
245: #define DC_CE 0x0400 /* clear data cache entry */
246: #define DC_CLR 0x0800 /* clear entire data cache */
247: #define DC_BE 0x1000 /* data burst enable */
248: #define DC_WA 0x2000 /* write allocate */
249:
250: #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
251: #define CACHE_OFF (DC_CLR|IC_CLR)
252: #define CACHE_CLR (CACHE_ON)
253: #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
254: #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)
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