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1.1 root 1: /*
2: * Copyright (c) 1982, 1986, 1990 Regents of the University of California.
3: * All rights reserved.
4: *
5: * Redistribution and use in source and binary forms, with or without
6: * modification, are permitted provided that the following conditions
7: * are met:
8: * 1. Redistributions of source code must retain the above copyright
9: * notice, this list of conditions and the following disclaimer.
10: * 2. Redistributions in binary form must reproduce the above copyright
11: * notice, this list of conditions and the following disclaimer in the
12: * documentation and/or other materials provided with the distribution.
13: * 3. All advertising materials mentioning features or use of this software
14: * must display the following acknowledgement:
15: * This product includes software developed by the University of
16: * California, Berkeley and its contributors.
17: * 4. Neither the name of the University nor the names of its contributors
18: * may be used to endorse or promote products derived from this software
19: * without specific prior written permission.
20: *
21: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31: * SUCH DAMAGE.
32: *
33: * @(#)dcareg.h 7.3 (Berkeley) 5/7/91
34: */
35:
36: struct dcadevice {
37: u_char dca_pad0;
38: volatile u_char dca_irid;
39: volatile short dca_ic;
40: volatile short dca_ocbrc;
41: volatile short dca_lcsm;
42: short dca_pad1[4];
43: u_char dca_pad2;
44: volatile u_char dca_data;
45: volatile short dca_ier;
46: u_char dca_pad4;
47: volatile u_char dca_iir; /* read-only */
48: #define dca_fifo dca_iir /* write-only */
49: volatile short dca_cfcr;
50: volatile short dca_mcr;
51: volatile short dca_lsr;
52: u_char dca_pad3;
53: volatile u_char dca_msr;
54: };
55:
56: /* interface reset/id */
57: #define DCAID0 0x02
58: #define DCAREMID0 0x82
59: #define DCAID1 0x42
60: #define DCAREMID1 0xC2
61:
62: /* interrupt control */
63: #define DCAIPL(x) ((((x) >> 4) & 3) + 3)
64: #define IC_IR 0x40
65: #define IC_IE 0x80
66:
67: /* 16 bit baud rate divisor (lower byte in dca_data, upper in dca_ier) */
68: #define DCABRD(x) (153600 / (x))
69:
70: /* interrupt enable register */
71: #define IER_ERXRDY 0x1
72: #define IER_ETXRDY 0x2
73: #define IER_ERLS 0x4
74: #define IER_EMSC 0x8
75:
76: /* interrupt identification register */
77: #define IIR_IMASK 0xf
78: #define IIR_RXTOUT 0xc
79: #define IIR_RLS 0x6
80: #define IIR_RXRDY 0x4
81: #define IIR_TXRDY 0x2
82: #define IIR_NOPEND 0x1
83: #define IIR_MLSC 0x0
84: #define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
85:
86: /* fifo control register */
87: #define FIFO_ENABLE 0x01
88: #define FIFO_RCV_RST 0x02
89: #define FIFO_XMT_RST 0x04
90: #define FIFO_DMA_MODE 0x08
91: #define FIFO_TRIGGER_1 0x00
92: #define FIFO_TRIGGER_4 0x40
93: #define FIFO_TRIGGER_8 0x80
94: #define FIFO_TRIGGER_14 0xc0
95:
96: /* character format control register */
97: #define CFCR_DLAB 0x80
98: #define CFCR_SBREAK 0x40
99: #define CFCR_PZERO 0x30
100: #define CFCR_PONE 0x20
101: #define CFCR_PEVEN 0x10
102: #define CFCR_PODD 0x00
103: #define CFCR_PENAB 0x08
104: #define CFCR_STOPB 0x04
105: #define CFCR_8BITS 0x03
106: #define CFCR_7BITS 0x02
107: #define CFCR_6BITS 0x01
108: #define CFCR_5BITS 0x00
109:
110: /* modem control register */
111: #define MCR_LOOPBACK 0x10
112: #define MCR_SRTS 0x08
113: #define MCR_DRS 0x04
114: #define MCR_RTS 0x02
115: #define MCR_DTR 0x01
116:
117: /* line status register */
118: #define LSR_RCV_FIFO 0x80
119: #define LSR_TSRE 0x40
120: #define LSR_TXRDY 0x20
121: #define LSR_BI 0x10
122: #define LSR_FE 0x08
123: #define LSR_PE 0x04
124: #define LSR_OE 0x02
125: #define LSR_RXRDY 0x01
126: #define LSR_RCV_MASK 0x1f
127:
128: /* modem status register */
129: #define MSR_DCD 0x80
130: #define MSR_RI 0x40
131: #define MSR_DSR 0x20
132: #define MSR_CTS 0x10
133: #define MSR_DDCD 0x08
134: #define MSR_TERI 0x04
135: #define MSR_DDSR 0x02
136: #define MSR_DCTS 0x01
137:
138: /*
139: * WARNING: Serial console is assumed to be at SC9
140: * and CONUNIT must be 0.
141: */
142: #define CONSCODE (9)
143: #define CONUNIT (0)
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