![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to scsi.c CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Net/2] / Net2 / arch / hp300 / dev|
Return to scsi.c CVS log | Up to [Net/2] / Net2 / arch / hp300 / dev |
1.1 root 1: /*
2: * Copyright (c) 1990 The Regents of the University of California.
3: * All rights reserved.
4: *
5: * This code is derived from software contributed to Berkeley by
6: * Van Jacobson of Lawrence Berkeley Laboratory.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: * 3. All advertising materials mentioning features or use of this software
17: * must display the following acknowledgement:
18: * This product includes software developed by the University of
19: * California, Berkeley and its contributors.
20: * 4. Neither the name of the University nor the names of its contributors
21: * may be used to endorse or promote products derived from this software
22: * without specific prior written permission.
23: *
24: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34: * SUCH DAMAGE.
35: *
1.1.1.2 ! root 36: * from: @(#)scsi.c 7.5 (Berkeley) 5/4/91
! 37: * scsi.c,v 1.2 1993/05/22 07:56:48 cgd Exp
1.1 root 38: */
39:
40: /*
41: * HP9000/3xx 98658 SCSI host adaptor driver.
42: */
43: #include "scsi.h"
44: #if NSCSI > 0
45:
46: #include "sys/param.h"
47: #include "sys/systm.h"
48: #include "sys/buf.h"
49: #include "device.h"
50:
51: #include "scsivar.h"
52: #include "scsireg.h"
53: #include "dmavar.h"
54:
55: #include "../include/cpu.h"
56: #include "../hp300/isr.h"
57:
58: /*
59: * SCSI delays
60: * In u-seconds, primarily for state changes on the SPC.
61: */
62: #define SCSI_CMD_WAIT 1000 /* wait per step of 'immediate' cmds */
63: #define SCSI_DATA_WAIT 1000 /* wait per data in/out step */
64: #define SCSI_INIT_WAIT 50000 /* wait per step (both) during init */
65:
66: extern void isrlink();
67: extern void _insque();
68: extern void _remque();
69:
70: int scsiinit(), scsigo(), scsiintr(), scsixfer();
71: void scsistart(), scsidone(), scsifree(), scsireset();
72: struct driver scsidriver = {
73: scsiinit, "scsi", (int (*)())scsistart, scsigo, scsiintr,
74: (int (*)())scsidone,
75: };
76:
77: struct scsi_softc scsi_softc[NSCSI];
78: struct isr scsi_isr[NSCSI];
79:
80: int scsi_cmd_wait = SCSI_CMD_WAIT;
81: int scsi_data_wait = SCSI_DATA_WAIT;
82: int scsi_init_wait = SCSI_INIT_WAIT;
83:
84: int scsi_nosync = 1; /* inhibit sync xfers if 1 */
85: int scsi_pridma = 0; /* use "priority" dma */
86:
87: #ifdef DEBUG
88: int scsi_debug = 0;
89: #define WAITHIST
90: #endif
91:
92: #ifdef WAITHIST
93: #define MAXWAIT 1022
94: u_int ixstart_wait[MAXWAIT+2];
95: u_int ixin_wait[MAXWAIT+2];
96: u_int ixout_wait[MAXWAIT+2];
97: u_int mxin_wait[MAXWAIT+2];
98: u_int mxin2_wait[MAXWAIT+2];
99: u_int cxin_wait[MAXWAIT+2];
100: u_int fxfr_wait[MAXWAIT+2];
101: u_int sgo_wait[MAXWAIT+2];
102: #define HIST(h,w) (++h[((w)>MAXWAIT? MAXWAIT : ((w) < 0 ? -1 : (w))) + 1]);
103: #else
104: #define HIST(h,w)
105: #endif
106:
107: #define b_cylin b_resid
108:
109: static void
110: scsiabort(hs, hd, where)
111: register struct scsi_softc *hs;
112: volatile register struct scsidevice *hd;
113: char *where;
114: {
115: int len;
116: u_char junk;
117:
118: printf("scsi%d: abort from %s: phase=0x%x, ssts=0x%x, ints=0x%x\n",
119: hs->sc_hc->hp_unit, where, hd->scsi_psns, hd->scsi_ssts,
120: hd->scsi_ints);
121:
122: hd->scsi_ints = hd->scsi_ints;
123: hd->scsi_csr = 0;
124: if (hd->scsi_psns == 0 || (hd->scsi_ssts & SSTS_INITIATOR) == 0)
125: /* no longer connected to scsi target */
126: return;
127:
128: /* get the number of bytes remaining in current xfer + fudge */
129: len = (hd->scsi_tch << 16) | (hd->scsi_tcm << 8) | hd->scsi_tcl;
130:
131: /* for that many bus cycles, try to send an abort msg */
132: for (len += 1024; (hd->scsi_ssts & SSTS_INITIATOR) && --len >= 0; ) {
133: hd->scsi_scmd = SCMD_SET_ATN;
134: while ((hd->scsi_psns & PSNS_REQ) == 0) {
135: if (! (hd->scsi_ssts & SSTS_INITIATOR))
136: goto out;
137: DELAY(1);
138: }
139: if ((hd->scsi_psns & PHASE) == MESG_OUT_PHASE)
140: hd->scsi_scmd = SCMD_RST_ATN;
141: hd->scsi_pctl = hd->scsi_psns & PHASE;
142: if (hd->scsi_psns & PHASE_IO) {
143: /* one of the input phases - read & discard a byte */
144: hd->scsi_scmd = SCMD_SET_ACK;
145: if (hd->scsi_tmod == 0)
146: while (hd->scsi_psns & PSNS_REQ)
147: DELAY(1);
148: junk = hd->scsi_temp;
149: } else {
150: /* one of the output phases - send an abort msg */
151: hd->scsi_temp = MSG_ABORT;
152: hd->scsi_scmd = SCMD_SET_ACK;
153: if (hd->scsi_tmod == 0)
154: while (hd->scsi_psns & PSNS_REQ)
155: DELAY(1);
156: }
157: hd->scsi_scmd = SCMD_RST_ACK;
158: }
159: out:
160: /*
161: * Either the abort was successful & the bus is disconnected or
162: * the device didn't listen. If the latter, announce the problem.
163: * Either way, reset the card & the SPC.
164: */
165: if (len < 0 && hs)
166: printf("scsi%d: abort failed. phase=0x%x, ssts=0x%x\n",
167: hs->sc_hc->hp_unit, hd->scsi_psns, hd->scsi_ssts);
168:
169: if (! ((junk = hd->scsi_ints) & INTS_RESEL)) {
170: hd->scsi_sctl |= SCTL_CTRLRST;
171: DELAY(1);
172: hd->scsi_sctl &=~ SCTL_CTRLRST;
173: hd->scsi_hconf = 0;
174: hd->scsi_ints = hd->scsi_ints;
175: }
176: }
177:
178: /*
179: * XXX Set/reset long delays.
180: *
181: * if delay == 0, reset default delays
182: * if delay < 0, set both delays to default long initialization values
183: * if delay > 0, set both delays to this value
184: *
185: * Used when a devices is expected to respond slowly (e.g. during
186: * initialization).
187: */
188: void
189: scsi_delay(delay)
190: int delay;
191: {
192: static int saved_cmd_wait, saved_data_wait;
193:
194: if (delay) {
195: saved_cmd_wait = scsi_cmd_wait;
196: saved_data_wait = scsi_data_wait;
197: if (delay > 0)
198: scsi_cmd_wait = scsi_data_wait = delay;
199: else
200: scsi_cmd_wait = scsi_data_wait = scsi_init_wait;
201: } else {
202: scsi_cmd_wait = saved_cmd_wait;
203: scsi_data_wait = saved_data_wait;
204: }
205: }
206:
207: int
208: scsiinit(hc)
209: register struct hp_ctlr *hc;
210: {
211: register struct scsi_softc *hs = &scsi_softc[hc->hp_unit];
212: register struct scsidevice *hd = (struct scsidevice *)hc->hp_addr;
213:
214: if ((hd->scsi_id & ID_MASK) != SCSI_ID)
215: return(0);
216: hc->hp_ipl = SCSI_IPL(hd->scsi_csr);
217: hs->sc_hc = hc;
218: hs->sc_dq.dq_unit = hc->hp_unit;
219: hs->sc_dq.dq_driver = &scsidriver;
220: hs->sc_sq.dq_forw = hs->sc_sq.dq_back = &hs->sc_sq;
221: scsi_isr[hc->hp_unit].isr_intr = scsiintr;
222: scsi_isr[hc->hp_unit].isr_ipl = hc->hp_ipl;
223: scsi_isr[hc->hp_unit].isr_arg = hc->hp_unit;
224: isrlink(&scsi_isr[hc->hp_unit]);
225: scsireset(hc->hp_unit);
226: return(1);
227: }
228:
229: void
230: scsireset(unit)
231: register int unit;
232: {
233: register struct scsi_softc *hs = &scsi_softc[unit];
234: volatile register struct scsidevice *hd =
235: (struct scsidevice *)hs->sc_hc->hp_addr;
236: u_int i;
237:
238: if (hs->sc_flags & SCSI_ALIVE)
239: scsiabort(hs, hd, "reset");
240:
241: printf("scsi%d: ", unit);
242:
243: hd->scsi_id = 0xFF;
244: DELAY(100);
245: /*
246: * Disable interrupts then reset the FUJI chip.
247: */
248: hd->scsi_csr = 0;
249: hd->scsi_sctl = SCTL_DISABLE | SCTL_CTRLRST;
250: hd->scsi_scmd = 0;
251: hd->scsi_tmod = 0;
252: hd->scsi_pctl = 0;
253: hd->scsi_temp = 0;
254: hd->scsi_tch = 0;
255: hd->scsi_tcm = 0;
256: hd->scsi_tcl = 0;
257: hd->scsi_ints = 0;
258:
259: if ((hd->scsi_id & ID_WORD_DMA) == 0) {
260: hs->sc_flags |= SCSI_DMA32;
261: printf("32 bit dma, ");
262: }
263:
264: /* Determine Max Synchronous Transfer Rate */
265: if (scsi_nosync)
266: i = 3;
267: else
268: i = SCSI_SYNC_XFER(hd->scsi_hconf);
269: switch (i) {
270: case 0:
271: hs->sc_sync = TMOD_SYNC | 0x3e; /* 250 nsecs */
272: printf("250ns sync");
273: break;
274: case 1:
275: hs->sc_sync = TMOD_SYNC | 0x5e; /* 375 nsecs */
276: printf("375ns sync");
277: break;
278: case 2:
279: hs->sc_sync = TMOD_SYNC | 0x7d; /* 500 nsecs */
280: printf("500ns sync");
281: break;
282: case 3:
283: hs->sc_sync = 0;
284: printf("async");
285: break;
286: }
287:
288: /*
289: * Configure the FUJI chip with its SCSI address, all
290: * interrupts enabled & appropriate parity.
291: */
292: i = (~hd->scsi_hconf) & 0x7;
293: hs->sc_scsi_addr = 1 << i;
294: hd->scsi_bdid = i;
295: if (hd->scsi_hconf & HCONF_PARITY)
296: hd->scsi_sctl = SCTL_DISABLE | SCTL_ABRT_ENAB |
297: SCTL_SEL_ENAB | SCTL_RESEL_ENAB |
298: SCTL_INTR_ENAB | SCTL_PARITY_ENAB;
299: else {
300: hd->scsi_sctl = SCTL_DISABLE | SCTL_ABRT_ENAB |
301: SCTL_SEL_ENAB | SCTL_RESEL_ENAB |
302: SCTL_INTR_ENAB;
303: printf(", no parity");
304: }
305: hd->scsi_sctl &=~ SCTL_DISABLE;
306:
307: printf(", scsi id %d\n", i);
308: hs->sc_flags |= SCSI_ALIVE;
309: }
310:
311: static void
312: scsierror(hs, hd, ints)
313: register struct scsi_softc *hs;
314: volatile register struct scsidevice *hd;
315: u_char ints;
316: {
317: int unit = hs->sc_hc->hp_unit;
318: char *sep = "";
319:
320: printf("scsi%d: ", unit);
321: if (ints & INTS_RST) {
322: DELAY(100);
323: if (hd->scsi_hconf & HCONF_SD)
324: printf("spurious RST interrupt");
325: else
326: printf("hardware error - check fuse");
327: sep = ", ";
328: }
329: if ((ints & INTS_HARD_ERR) || hd->scsi_serr) {
330: if (hd->scsi_serr & SERR_SCSI_PAR) {
331: printf("%sparity err", sep);
332: sep = ", ";
333: }
334: if (hd->scsi_serr & SERR_SPC_PAR) {
335: printf("%sSPC parity err", sep);
336: sep = ", ";
337: }
338: if (hd->scsi_serr & SERR_TC_PAR) {
339: printf("%sTC parity err", sep);
340: sep = ", ";
341: }
342: if (hd->scsi_serr & SERR_PHASE_ERR) {
343: printf("%sphase err", sep);
344: sep = ", ";
345: }
346: if (hd->scsi_serr & SERR_SHORT_XFR) {
347: printf("%ssync short transfer err", sep);
348: sep = ", ";
349: }
350: if (hd->scsi_serr & SERR_OFFSET) {
351: printf("%ssync offset error", sep);
352: sep = ", ";
353: }
354: }
355: if (ints & INTS_TIMEOUT)
356: printf("%sSPC select timeout error", sep);
357: if (ints & INTS_SRV_REQ)
358: printf("%sspurious SRV_REQ interrupt", sep);
359: if (ints & INTS_CMD_DONE)
360: printf("%sspurious CMD_DONE interrupt", sep);
361: if (ints & INTS_DISCON)
362: printf("%sspurious disconnect interrupt", sep);
363: if (ints & INTS_RESEL)
364: printf("%sspurious reselect interrupt", sep);
365: if (ints & INTS_SEL)
366: printf("%sspurious select interrupt", sep);
367: printf("\n");
368: }
369:
370: static int
371: issue_select(hd, target, our_addr)
372: volatile register struct scsidevice *hd;
373: u_char target, our_addr;
374: {
375: if (hd->scsi_ssts & (SSTS_INITIATOR|SSTS_TARGET|SSTS_BUSY))
376: return (1);
377:
378: if (hd->scsi_ints & INTS_DISCON)
379: hd->scsi_ints = INTS_DISCON;
380:
381: hd->scsi_pctl = 0;
382: hd->scsi_temp = (1 << target) | our_addr;
383: /* select timeout is hardcoded to 2ms */
384: hd->scsi_tch = 0;
385: hd->scsi_tcm = 32;
386: hd->scsi_tcl = 4;
387:
388: hd->scsi_scmd = SCMD_SELECT;
389: return (0);
390: }
391:
392: static int
393: wait_for_select(hd)
394: volatile register struct scsidevice *hd;
395: {
396: u_char ints;
397:
398: while ((ints = hd->scsi_ints) == 0)
399: DELAY(1);
400: hd->scsi_ints = ints;
401: return (!(hd->scsi_ssts & SSTS_INITIATOR));
402: }
403:
404: static int
405: ixfer_start(hd, len, phase, wait)
406: volatile register struct scsidevice *hd;
407: int len;
408: u_char phase;
409: register int wait;
410: {
411:
412: hd->scsi_tch = len >> 16;
413: hd->scsi_tcm = len >> 8;
414: hd->scsi_tcl = len;
415: hd->scsi_pctl = phase;
416: hd->scsi_tmod = 0; /*XXX*/
417: hd->scsi_scmd = SCMD_XFR | SCMD_PROG_XFR;
418:
419: /* wait for xfer to start or svc_req interrupt */
420: while ((hd->scsi_ssts & SSTS_BUSY) == 0) {
421: if (hd->scsi_ints || --wait < 0) {
422: #ifdef DEBUG
423: if (scsi_debug)
424: printf("ixfer_start fail: i%x, w%d\n",
425: hd->scsi_ints, wait);
426: #endif
427: HIST(ixstart_wait, wait)
428: return (0);
429: }
430: DELAY(1);
431: }
432: HIST(ixstart_wait, wait)
433: return (1);
434: }
435:
436: static int
437: ixfer_out(hd, len, buf)
438: volatile register struct scsidevice *hd;
439: int len;
440: register u_char *buf;
441: {
442: register int wait = scsi_data_wait;
443:
444: for (; len > 0; --len) {
445: while (hd->scsi_ssts & SSTS_DREG_FULL) {
446: if (hd->scsi_ints || --wait < 0) {
447: #ifdef DEBUG
448: if (scsi_debug)
449: printf("ixfer_out fail: l%d i%x w%d\n",
450: len, hd->scsi_ints, wait);
451: #endif
452: HIST(ixout_wait, wait)
453: return (len);
454: }
455: DELAY(1);
456: }
457: hd->scsi_dreg = *buf++;
458: }
459: HIST(ixout_wait, wait)
460: return (0);
461: }
462:
463: static void
464: ixfer_in(hd, len, buf)
465: volatile register struct scsidevice *hd;
466: int len;
467: register u_char *buf;
468: {
469: register int wait = scsi_data_wait;
470:
471: for (; len > 0; --len) {
472: while (hd->scsi_ssts & SSTS_DREG_EMPTY) {
473: if (hd->scsi_ints || --wait < 0) {
474: while (! (hd->scsi_ssts & SSTS_DREG_EMPTY)) {
475: *buf++ = hd->scsi_dreg;
476: --len;
477: }
478: #ifdef DEBUG
479: if (scsi_debug)
480: printf("ixfer_in fail: l%d i%x w%d\n",
481: len, hd->scsi_ints, wait);
482: #endif
483: HIST(ixin_wait, wait)
484: return;
485: }
486: DELAY(1);
487: }
488: *buf++ = hd->scsi_dreg;
489: }
490: HIST(ixin_wait, wait)
491: }
492:
493: static int
494: mxfer_in(hd, len, buf, phase)
495: volatile register struct scsidevice *hd;
496: register int len;
497: register u_char *buf;
498: register u_char phase;
499: {
500: register int wait = scsi_cmd_wait;
501: register int i;
502:
503: hd->scsi_tmod = 0;
504: for (i = 0; i < len; ++i) {
505: /*
506: * manual sez: reset ATN before ACK is sent.
507: */
508: if (hd->scsi_psns & PSNS_ATN)
509: hd->scsi_scmd = SCMD_RST_ATN;
510: /*
511: * wait for the request line (which says the target
512: * wants to give us data). If the phase changes while
513: * we're waiting, we're done.
514: */
515: while ((hd->scsi_psns & PSNS_REQ) == 0) {
516: if (--wait < 0) {
517: HIST(mxin_wait, wait)
518: return (-1);
519: }
520: if ((hd->scsi_psns & PHASE) != phase ||
521: (hd->scsi_ssts & SSTS_INITIATOR) == 0)
522: goto out;
523:
524: DELAY(1);
525: }
526: /*
527: * set ack (which says we're ready for the data, wait for
528: * req to go away (target says data is available), grab the
529: * data, then reset ack (say we've got the data).
530: */
531: hd->scsi_pctl = phase;
532: hd->scsi_scmd = SCMD_SET_ACK;
533: while (hd->scsi_psns & PSNS_REQ) {
534: if (--wait < 0) {
535: HIST(mxin_wait, wait)
536: return (-2);
537: }
538: DELAY(1);
539: }
540: *buf++ = hd->scsi_temp;
541: hd->scsi_scmd = SCMD_RST_ACK;
542: }
543: out:
544: HIST(mxin_wait, wait)
545: /*
546: * Wait for manual transfer to finish.
547: * Avoids occasional "unexpected phase" errors in finishxfer
548: * formerly addressed by per-slave delays.
549: */
550: wait = scsi_cmd_wait;
551: while ((hd->scsi_ssts & SSTS_ACTIVE) == SSTS_INITIATOR) {
552: if (--wait < 0)
553: break;
554: DELAY(1);
555: }
556: HIST(mxin2_wait, wait)
557: return (i);
558: }
559:
560: /*
561: * SCSI 'immediate' command: issue a command to some SCSI device
562: * and get back an 'immediate' response (i.e., do programmed xfer
563: * to get the response data). 'cbuf' is a buffer containing a scsi
564: * command of length clen bytes. 'buf' is a buffer of length 'len'
565: * bytes for data. The transfer direction is determined by the device
566: * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the
567: * command must supply no data. 'xferphase' is the bus phase the
568: * caller expects to happen after the command is issued. It should
569: * be one of DATA_IN_PHASE, DATA_OUT_PHASE or STATUS_PHASE.
570: */
571: static int
572: scsiicmd(hs, target, cbuf, clen, buf, len, xferphase)
573: struct scsi_softc *hs;
574: int target;
575: u_char *cbuf;
576: int clen;
577: u_char *buf;
578: int len;
579: u_char xferphase;
580: {
581: volatile register struct scsidevice *hd =
582: (struct scsidevice *)hs->sc_hc->hp_addr;
583: u_char phase, ints;
584: register int wait;
585:
586: /* select the SCSI bus (it's an error if bus isn't free) */
587: if (issue_select(hd, target, hs->sc_scsi_addr))
588: return (-1);
589: if (wait_for_select(hd))
590: return (-1);
591: /*
592: * Wait for a phase change (or error) then let the device
593: * sequence us through the various SCSI phases.
594: */
595: hs->sc_stat[0] = 0xff;
596: hs->sc_msg[0] = 0xff;
597: phase = CMD_PHASE;
598: while (1) {
599: wait = scsi_cmd_wait;
600: switch (phase) {
601:
602: case CMD_PHASE:
603: if (ixfer_start(hd, clen, phase, wait))
604: if (ixfer_out(hd, clen, cbuf))
605: goto abort;
606: phase = xferphase;
607: break;
608:
609: case DATA_IN_PHASE:
610: if (len <= 0)
611: goto abort;
612: wait = scsi_data_wait;
613: if (ixfer_start(hd, len, phase, wait) ||
614: !(hd->scsi_ssts & SSTS_DREG_EMPTY))
615: ixfer_in(hd, len, buf);
616: phase = STATUS_PHASE;
617: break;
618:
619: case DATA_OUT_PHASE:
620: if (len <= 0)
621: goto abort;
622: wait = scsi_data_wait;
623: if (ixfer_start(hd, len, phase, wait)) {
624: if (ixfer_out(hd, len, buf))
625: goto abort;
626: }
627: phase = STATUS_PHASE;
628: break;
629:
630: case STATUS_PHASE:
631: wait = scsi_data_wait;
632: if (ixfer_start(hd, sizeof(hs->sc_stat), phase, wait) ||
633: !(hd->scsi_ssts & SSTS_DREG_EMPTY))
634: ixfer_in(hd, sizeof(hs->sc_stat), hs->sc_stat);
635: phase = MESG_IN_PHASE;
636: break;
637:
638: case MESG_IN_PHASE:
639: if (ixfer_start(hd, sizeof(hs->sc_msg), phase, wait) ||
640: !(hd->scsi_ssts & SSTS_DREG_EMPTY)) {
641: ixfer_in(hd, sizeof(hs->sc_msg), hs->sc_msg);
642: hd->scsi_scmd = SCMD_RST_ACK;
643: }
644: phase = BUS_FREE_PHASE;
645: break;
646:
647: case BUS_FREE_PHASE:
648: goto out;
649:
650: default:
651: printf("scsi%d: unexpected phase %d in icmd from %d\n",
652: hs->sc_hc->hp_unit, phase, target);
653: goto abort;
654: }
655: /* wait for last command to complete */
656: while ((ints = hd->scsi_ints) == 0) {
657: if (--wait < 0) {
658: HIST(cxin_wait, wait)
659: goto abort;
660: }
661: DELAY(1);
662: }
663: HIST(cxin_wait, wait)
664: hd->scsi_ints = ints;
665: if (ints & INTS_SRV_REQ)
666: phase = hd->scsi_psns & PHASE;
667: else if (ints & INTS_DISCON)
668: goto out;
669: else if ((ints & INTS_CMD_DONE) == 0) {
670: scsierror(hs, hd, ints);
671: goto abort;
672: }
673: }
674: abort:
675: scsiabort(hs, hd, "icmd");
676: out:
677: return (hs->sc_stat[0]);
678: }
679:
680: /*
681: * Finish SCSI xfer command: After the completion interrupt from
682: * a read/write operation, sequence through the final phases in
683: * programmed i/o. This routine is a lot like scsiicmd except we
684: * skip (and don't allow) the select, cmd out and data in/out phases.
685: */
686: static void
687: finishxfer(hs, hd, target)
688: struct scsi_softc *hs;
689: volatile register struct scsidevice *hd;
690: int target;
691: {
692: u_char phase, ints;
693:
694: /*
695: * We specified padding xfer so we ended with either a phase
696: * change interrupt (normal case) or an error interrupt (handled
697: * elsewhere). Reset the board dma logic then try to get the
698: * completion status & command done msg. The reset confuses
699: * the SPC REQ/ACK logic so we have to do any status/msg input
700: * operations via 'manual xfer'.
701: */
702: if (hd->scsi_ssts & SSTS_BUSY) {
703: int wait = scsi_cmd_wait;
704:
705: /* wait for dma operation to finish */
706: while (hd->scsi_ssts & SSTS_BUSY) {
707: if (--wait < 0) {
708: #ifdef DEBUG
709: if (scsi_debug)
710: printf("finishxfer fail: ssts %x\n",
711: hd->scsi_ssts);
712: #endif
713: HIST(fxfr_wait, wait)
714: goto abort;
715: }
716: }
717: HIST(fxfr_wait, wait)
718: }
719: hd->scsi_scmd |= SCMD_PROG_XFR;
720: hd->scsi_sctl |= SCTL_CTRLRST;
721: DELAY(1);
722: hd->scsi_sctl &=~ SCTL_CTRLRST;
723: hd->scsi_hconf = 0;
724: hs->sc_stat[0] = 0xff;
725: hs->sc_msg[0] = 0xff;
726: hd->scsi_csr = 0;
727: hd->scsi_ints = ints = hd->scsi_ints;
728: while (1) {
729: phase = hd->scsi_psns & PHASE;
730: switch (phase) {
731:
732: case STATUS_PHASE:
733: if (mxfer_in(hd, sizeof(hs->sc_stat), hs->sc_stat,
734: phase) <= 0)
735: goto abort;
736: break;
737:
738: case MESG_IN_PHASE:
739: if (mxfer_in(hd, sizeof(hs->sc_msg), hs->sc_msg,
740: phase) < 0)
741: goto abort;
742: break;
743:
744: case BUS_FREE_PHASE:
745: return;
746:
747: default:
748: printf("scsi%d: unexpected phase %d in finishxfer from %d\n",
749: hs->sc_hc->hp_unit, phase, target);
750: goto abort;
751: }
752: if (ints = hd->scsi_ints) {
753: hd->scsi_ints = ints;
754: if (ints & INTS_DISCON)
755: return;
756: else if (ints & ~(INTS_SRV_REQ|INTS_CMD_DONE)) {
757: scsierror(hs, hd, ints);
758: break;
759: }
760: }
761: if ((hd->scsi_ssts & SSTS_INITIATOR) == 0)
762: return;
763: }
764: abort:
765: scsiabort(hs, hd, "finishxfer");
766: hs->sc_stat[0] = 0xfe;
767: }
768:
769: int
770: scsi_test_unit_rdy(ctlr, slave, unit)
771: int ctlr, slave, unit;
772: {
773: register struct scsi_softc *hs = &scsi_softc[ctlr];
774: static struct scsi_cdb6 cdb = { CMD_TEST_UNIT_READY };
775:
776: cdb.lun = unit;
777: return (scsiicmd(hs, slave, &cdb, sizeof(cdb), (u_char *)0, 0,
778: STATUS_PHASE));
779: }
780:
781: int
782: scsi_request_sense(ctlr, slave, unit, buf, len)
783: int ctlr, slave, unit;
784: u_char *buf;
785: unsigned len;
786: {
787: register struct scsi_softc *hs = &scsi_softc[ctlr];
788: static struct scsi_cdb6 cdb = { CMD_REQUEST_SENSE };
789:
790: cdb.lun = unit;
791: cdb.len = len;
792: return (scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_IN_PHASE));
793: }
794:
795: int
796: scsi_immed_command(ctlr, slave, unit, cdb, buf, len, rd)
797: int ctlr, slave, unit;
798: struct scsi_fmt_cdb *cdb;
799: u_char *buf;
800: unsigned len;
801: {
802: register struct scsi_softc *hs = &scsi_softc[ctlr];
803:
804: cdb->cdb[1] |= unit << 5;
805: return (scsiicmd(hs, slave, cdb->cdb, cdb->len, buf, len,
806: rd != 0? DATA_IN_PHASE : DATA_OUT_PHASE));
807: }
808:
809: /*
810: * The following routines are test-and-transfer i/o versions of read/write
811: * for things like reading disk labels and writing core dumps. The
812: * routine scsigo should be used for normal data transfers, NOT these
813: * routines.
814: */
815: int
816: scsi_tt_read(ctlr, slave, unit, buf, len, blk, bshift)
817: int ctlr, slave, unit;
818: u_char *buf;
819: u_int len;
820: daddr_t blk;
821: int bshift;
822: {
823: register struct scsi_softc *hs = &scsi_softc[ctlr];
824: struct scsi_cdb10 cdb;
825: int stat;
826: int old_wait = scsi_data_wait;
827:
828: scsi_data_wait = 300000;
829: bzero(&cdb, sizeof(cdb));
830: cdb.cmd = CMD_READ_EXT;
831: cdb.lun = unit;
832: blk >>= bshift;
833: cdb.lbah = blk >> 24;
834: cdb.lbahm = blk >> 16;
835: cdb.lbalm = blk >> 8;
836: cdb.lbal = blk;
837: cdb.lenh = len >> (8 + DEV_BSHIFT + bshift);
838: cdb.lenl = len >> (DEV_BSHIFT + bshift);
839: stat = scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_IN_PHASE);
840: scsi_data_wait = old_wait;
841: return (stat);
842: }
843:
844: int
845: scsi_tt_write(ctlr, slave, unit, buf, len, blk, bshift)
846: int ctlr, slave, unit;
847: u_char *buf;
848: u_int len;
849: daddr_t blk;
850: int bshift;
851: {
852: register struct scsi_softc *hs = &scsi_softc[ctlr];
853: struct scsi_cdb10 cdb;
854: int stat;
855: int old_wait = scsi_data_wait;
856:
857: scsi_data_wait = 300000;
858:
859: bzero(&cdb, sizeof(cdb));
860: cdb.cmd = CMD_WRITE_EXT;
861: cdb.lun = unit;
862: blk >>= bshift;
863: cdb.lbah = blk >> 24;
864: cdb.lbahm = blk >> 16;
865: cdb.lbalm = blk >> 8;
866: cdb.lbal = blk;
867: cdb.lenh = len >> (8 + DEV_BSHIFT + bshift);
868: cdb.lenl = len >> (DEV_BSHIFT + bshift);
869: stat = scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_OUT_PHASE);
870: scsi_data_wait = old_wait;
871: return (stat);
872: }
873:
874: int
875: scsireq(dq)
876: register struct devqueue *dq;
877: {
878: register struct devqueue *hq;
879:
880: hq = &scsi_softc[dq->dq_ctlr].sc_sq;
881: insque(dq, hq->dq_back);
882: if (dq->dq_back == hq)
883: return(1);
884: return(0);
885: }
886:
887: int
888: scsiustart(unit)
889: int unit;
890: {
891: register struct scsi_softc *hs = &scsi_softc[unit];
892:
893: hs->sc_dq.dq_ctlr = DMA0 | DMA1;
894: if (dmareq(&hs->sc_dq))
895: return(1);
896: return(0);
897: }
898:
899: void
900: scsistart(unit)
901: int unit;
902: {
903: register struct devqueue *dq;
904:
905: dq = scsi_softc[unit].sc_sq.dq_forw;
906: (dq->dq_driver->d_go)(dq->dq_unit);
907: }
908:
909: int
910: scsigo(ctlr, slave, unit, bp, cdb, pad)
911: int ctlr, slave, unit;
912: struct buf *bp;
913: struct scsi_fmt_cdb *cdb;
914: int pad;
915: {
916: register struct scsi_softc *hs = &scsi_softc[ctlr];
917: volatile register struct scsidevice *hd =
918: (struct scsidevice *)hs->sc_hc->hp_addr;
919: int i, dmaflags;
920: u_char phase, ints, cmd;
921:
922: cdb->cdb[1] |= unit << 5;
923:
924: /* select the SCSI bus (it's an error if bus isn't free) */
925: if (issue_select(hd, slave, hs->sc_scsi_addr) || wait_for_select(hd)) {
926: dmafree(&hs->sc_dq);
927: return (1);
928: }
929: /*
930: * Wait for a phase change (or error) then let the device
931: * sequence us through command phase (we may have to take
932: * a msg in/out before doing the command). If the disk has
933: * to do a seek, it may be a long time until we get a change
934: * to data phase so, in the absense of an explicit phase
935: * change, we assume data phase will be coming up and tell
936: * the SPC to start a transfer whenever it does. We'll get
937: * a service required interrupt later if this assumption is
938: * wrong. Otherwise we'll get a service required int when
939: * the transfer changes to status phase.
940: */
941: phase = CMD_PHASE;
942: while (1) {
943: register int wait = scsi_cmd_wait;
944:
945: switch (phase) {
946:
947: case CMD_PHASE:
948: if (ixfer_start(hd, cdb->len, phase, wait))
949: if (ixfer_out(hd, cdb->len, cdb->cdb))
950: goto abort;
951: break;
952:
953: case MESG_IN_PHASE:
954: if (ixfer_start(hd, sizeof(hs->sc_msg), phase, wait)||
955: !(hd->scsi_ssts & SSTS_DREG_EMPTY)) {
956: ixfer_in(hd, sizeof(hs->sc_msg), hs->sc_msg);
957: hd->scsi_scmd = SCMD_RST_ACK;
958: }
959: phase = BUS_FREE_PHASE;
960: break;
961:
962: case DATA_IN_PHASE:
963: case DATA_OUT_PHASE:
964: goto out;
965:
966: default:
967: printf("scsi%d: unexpected phase %d in go from %d\n",
968: hs->sc_hc->hp_unit, phase, slave);
969: goto abort;
970: }
971: while ((ints = hd->scsi_ints) == 0) {
972: if (--wait < 0) {
973: HIST(sgo_wait, wait)
974: goto abort;
975: }
976: DELAY(1);
977: }
978: HIST(sgo_wait, wait)
979: hd->scsi_ints = ints;
980: if (ints & INTS_SRV_REQ)
981: phase = hd->scsi_psns & PHASE;
982: else if (ints & INTS_CMD_DONE)
983: goto out;
984: else {
985: scsierror(hs, hd, ints);
986: goto abort;
987: }
988: }
989: out:
990: /*
991: * Reset the card dma logic, setup the dma channel then
992: * get the dio part of the card set for a dma xfer.
993: */
994: hd->scsi_hconf = 0;
995: cmd = CSR_IE;
996: dmaflags = DMAGO_NOINT;
997: if (scsi_pridma)
998: dmaflags |= DMAGO_PRI;
999: if (bp->b_flags & B_READ)
1000: dmaflags |= DMAGO_READ;
1001: if ((hs->sc_flags & SCSI_DMA32) &&
1002: ((int)bp->b_un.b_addr & 3) == 0 && (bp->b_bcount & 3) == 0) {
1003: cmd |= CSR_DMA32;
1004: dmaflags |= DMAGO_LWORD;
1005: } else
1006: dmaflags |= DMAGO_WORD;
1007: dmago(hs->sc_dq.dq_ctlr, bp->b_un.b_addr, bp->b_bcount, dmaflags);
1008:
1009: if (bp->b_flags & B_READ) {
1010: cmd |= CSR_DMAIN;
1011: phase = DATA_IN_PHASE;
1012: } else
1013: phase = DATA_OUT_PHASE;
1014: /*
1015: * DMA enable bits must be set after size and direction bits.
1016: */
1017: hd->scsi_csr = cmd;
1018: hd->scsi_csr |= (CSR_DE0 << hs->sc_dq.dq_ctlr);
1019: /*
1020: * Setup the SPC for the transfer. We don't want to take
1021: * first a command complete then a service required interrupt
1022: * at the end of the transfer so we try to disable the cmd
1023: * complete by setting the transfer counter to more bytes
1024: * than we expect. (XXX - This strategy may have to be
1025: * modified to deal with devices that return variable length
1026: * blocks, e.g., some tape drives.)
1027: */
1028: cmd = SCMD_XFR;
1029: i = (unsigned)bp->b_bcount;
1030: if (pad) {
1031: cmd |= SCMD_PAD;
1032: /*
1033: * XXX - If we don't do this, the last 2 or 4 bytes
1034: * (depending on word/lword DMA) of a read get trashed.
1035: * It looks like it is necessary for the DMA to complete
1036: * before the SPC goes into "pad mode"??? Note: if we
1037: * also do this on a write, the request never completes.
1038: */
1039: if (bp->b_flags & B_READ)
1040: i += 2;
1041: #ifdef DEBUG
1042: hs->sc_flags |= SCSI_PAD;
1043: if (i & 1)
1044: printf("scsi%d: odd byte count: %d bytes @ %d\n",
1045: ctlr, i, bp->b_cylin);
1046: #endif
1047: } else
1048: i += 4;
1049: hd->scsi_tch = i >> 16;
1050: hd->scsi_tcm = i >> 8;
1051: hd->scsi_tcl = i;
1052: hd->scsi_pctl = phase;
1053: hd->scsi_tmod = 0;
1054: hd->scsi_scmd = cmd;
1055: hs->sc_flags |= SCSI_IO;
1056: return (0);
1057: abort:
1058: scsiabort(hs, hd, "go");
1059: dmafree(&hs->sc_dq);
1060: return (1);
1061: }
1062:
1063: void
1064: scsidone(unit)
1065: register int unit;
1066: {
1067: volatile register struct scsidevice *hd =
1068: (struct scsidevice *)scsi_softc[unit].sc_hc->hp_addr;
1069:
1070: #ifdef DEBUG
1071: if (scsi_debug)
1072: printf("scsi%d: done called!\n");
1073: #endif
1074: /* dma operation is done -- turn off card dma */
1075: hd->scsi_csr &=~ (CSR_DE1|CSR_DE0);
1076: }
1077:
1078: int
1079: scsiintr(unit)
1080: register int unit;
1081: {
1082: register struct scsi_softc *hs = &scsi_softc[unit];
1083: volatile register struct scsidevice *hd =
1084: (struct scsidevice *)hs->sc_hc->hp_addr;
1085: register u_char ints;
1086: register struct devqueue *dq;
1087:
1088: if ((hd->scsi_csr & (CSR_IE|CSR_IR)) != (CSR_IE|CSR_IR))
1089: return (0);
1090:
1091: ints = hd->scsi_ints;
1092: if ((ints & INTS_SRV_REQ) && (hs->sc_flags & SCSI_IO)) {
1093: /*
1094: * this should be the normal i/o completion case.
1095: * get the status & cmd complete msg then let the
1096: * device driver look at what happened.
1097: */
1098: #ifdef DEBUG
1099: int len = (hd->scsi_tch << 16) | (hd->scsi_tcm << 8) |
1100: hd->scsi_tcl;
1101: if (!(hs->sc_flags & SCSI_PAD))
1102: len -= 4;
1103: hs->sc_flags &=~ SCSI_PAD;
1104: #endif
1105: dq = hs->sc_sq.dq_forw;
1106: finishxfer(hs, hd, dq->dq_slave);
1107: hs->sc_flags &=~ SCSI_IO;
1108: dmafree(&hs->sc_dq);
1109: (dq->dq_driver->d_intr)(dq->dq_unit, hs->sc_stat[0]);
1110: } else {
1111: /* Something unexpected happened -- deal with it. */
1112: hd->scsi_ints = ints;
1113: hd->scsi_csr = 0;
1114: scsierror(hs, hd, ints);
1115: scsiabort(hs, hd, "intr");
1116: if (hs->sc_flags & SCSI_IO) {
1117: hs->sc_flags &=~ SCSI_IO;
1118: dmafree(&hs->sc_dq);
1119: dq = hs->sc_sq.dq_forw;
1120: (dq->dq_driver->d_intr)(dq->dq_unit, -1);
1121: }
1122: }
1123: return(1);
1124: }
1125:
1126: void
1127: scsifree(dq)
1128: register struct devqueue *dq;
1129: {
1130: register struct devqueue *hq;
1131:
1132: hq = &scsi_softc[dq->dq_ctlr].sc_sq;
1133: remque(dq);
1134: if ((dq = hq->dq_forw) != hq)
1135: (dq->dq_driver->d_start)(dq->dq_unit);
1136: }
1137:
1138: /*
1139: * (XXX) The following routine is needed for the SCSI tape driver
1140: * to read odd-size records.
1141: */
1142:
1143: #include "st.h"
1144: #if NST > 0
1145: int
1146: scsi_tt_oddio(ctlr, slave, unit, buf, len, b_flags, freedma)
1147: int ctlr, slave, unit, b_flags;
1148: u_char *buf;
1149: u_int len;
1150: {
1151: register struct scsi_softc *hs = &scsi_softc[ctlr];
1152: struct scsi_cdb6 cdb;
1153: u_char iphase;
1154: int stat;
1155:
1156: /*
1157: * First free any DMA channel that was allocated.
1158: * We can't use DMA to do this transfer.
1159: */
1160: if (freedma)
1161: dmafree(hs->sc_dq);
1162: /*
1163: * Initialize command block
1164: */
1165: bzero(&cdb, sizeof(cdb));
1166: cdb.lun = unit;
1167: cdb.lbam = (len >> 16) & 0xff;
1168: cdb.lbal = (len >> 8) & 0xff;
1169: cdb.len = len & 0xff;
1170: if (buf == 0) {
1171: cdb.cmd = CMD_SPACE;
1172: cdb.lun |= 0x00;
1173: len = 0;
1174: iphase = MESG_IN_PHASE;
1175: } else if (b_flags & B_READ) {
1176: cdb.cmd = CMD_READ;
1177: iphase = DATA_IN_PHASE;
1178: } else {
1179: cdb.cmd = CMD_WRITE;
1180: iphase = DATA_OUT_PHASE;
1181: }
1182: /*
1183: * Perform command (with very long delays)
1184: */
1185: scsi_delay(30000000);
1186: stat = scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, iphase);
1187: scsi_delay(0);
1188: return (stat);
1189: }
1190: #endif
1191: #endif
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.