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1.1 ! root 1: /* ! 2: * Copyright (c) 1988 University of Utah. ! 3: * Copyright (c) 1982, 1990 The Regents of the University of California. ! 4: * All rights reserved. ! 5: * ! 6: * This code is derived from software contributed to Berkeley by ! 7: * the Systems Programming Group of the University of Utah Computer ! 8: * Science Department. ! 9: * ! 10: * Redistribution and use in source and binary forms, with or without ! 11: * modification, are permitted provided that the following conditions ! 12: * are met: ! 13: * 1. Redistributions of source code must retain the above copyright ! 14: * notice, this list of conditions and the following disclaimer. ! 15: * 2. Redistributions in binary form must reproduce the above copyright ! 16: * notice, this list of conditions and the following disclaimer in the ! 17: * documentation and/or other materials provided with the distribution. ! 18: * 3. All advertising materials mentioning features or use of this software ! 19: * must display the following acknowledgement: ! 20: * This product includes software developed by the University of ! 21: * California, Berkeley and its contributors. ! 22: * 4. Neither the name of the University nor the names of its contributors ! 23: * may be used to endorse or promote products derived from this software ! 24: * without specific prior written permission. ! 25: * ! 26: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ! 27: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ! 28: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ! 29: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE ! 30: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ! 31: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ! 32: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ! 33: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ! 34: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ! 35: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ! 36: * SUCH DAMAGE. ! 37: * ! 38: * from: Utah $Hdr: cpu.h 1.16 91/03/25$ ! 39: * ! 40: * @(#)cpu.h 7.7 (Berkeley) 6/27/91 ! 41: */ ! 42: ! 43: /* ! 44: * Exported definitions unique to hp300/68k cpu support. ! 45: */ ! 46: ! 47: /* ! 48: * definitions of cpu-dependent requirements ! 49: * referenced in generic code ! 50: */ ! 51: #define COPY_SIGCODE /* copy sigcode above user stack in exec */ ! 52: ! 53: /* ! 54: * function vs. inline configuration; ! 55: * these are defined to get generic functions ! 56: * rather than inline or machine-dependent implementations ! 57: */ ! 58: #define NEED_MINMAX /* need {,i,l,ul}{min,max} functions */ ! 59: #undef NEED_FFS /* don't need ffs function */ ! 60: #undef NEED_BCMP /* don't need bcmp function */ ! 61: #undef NEED_STRLEN /* don't need strlen function */ ! 62: ! 63: #define cpu_exec(p) /* nothing */ ! 64: #define cpu_wait(p) /* nothing */ ! 65: ! 66: /* ! 67: * Arguments to hardclock, softclock and gatherstats ! 68: * encapsulate the previous machine state in an opaque ! 69: * clockframe; for hp300, use just what the hardware ! 70: * leaves on the stack. ! 71: */ ! 72: typedef struct intrframe { ! 73: int pc; ! 74: int ps; ! 75: } clockframe; ! 76: ! 77: #define CLKF_USERMODE(framep) (((framep)->ps & PSL_S) == 0) ! 78: #define CLKF_BASEPRI(framep) (((framep)->ps & PSL_IPL7) == 0) ! 79: #define CLKF_PC(framep) ((framep)->pc) ! 80: ! 81: ! 82: /* ! 83: * Preempt the current process if in interrupt from user mode, ! 84: * or after the current trap/syscall if in system mode. ! 85: */ ! 86: #define need_resched() { want_resched++; aston(); } ! 87: ! 88: /* ! 89: * Give a profiling tick to the current process from the softclock ! 90: * interrupt. On hp300, request an ast to send us through trap(), ! 91: * marking the proc as needing a profiling tick. ! 92: */ ! 93: #define profile_tick(p, framep) { (p)->p_flag |= SOWEUPC; aston(); } ! 94: ! 95: /* ! 96: * Notify the current process (p) that it has a signal pending, ! 97: * process as soon as possible. ! 98: */ ! 99: #define signotify(p) aston() ! 100: ! 101: #define aston() (astpending++) ! 102: ! 103: int astpending; /* need to trap before returning to user mode */ ! 104: int want_resched; /* resched() was called */ ! 105: ! 106: ! 107: /* ! 108: * simulated software interrupt register ! 109: */ ! 110: extern unsigned char ssir; ! 111: ! 112: #define SIR_NET 0x1 ! 113: #define SIR_CLOCK 0x2 ! 114: ! 115: #define siroff(x) ssir &= ~(x) ! 116: #define setsoftnet() ssir |= SIR_NET ! 117: #define setsoftclock() ssir |= SIR_CLOCK ! 118: ! 119: ! 120: ! 121: /* ! 122: * The rest of this should probably be moved to ../hp300/hp300cpu.h, ! 123: * although some of it could probably be put into generic 68k headers. ! 124: */ ! 125: ! 126: /* values for machineid */ ! 127: #define HP_320 0 /* 16Mhz 68020+HP MMU+16K external cache */ ! 128: #define HP_330 1 /* 16Mhz 68020+68851 MMU */ ! 129: #define HP_350 2 /* 25Mhz 68020+HP MMU+32K external cache */ ! 130: #define HP_360 3 /* 25Mhz 68030 */ ! 131: #define HP_370 4 /* 33Mhz 68030+64K external cache */ ! 132: #define HP_340 5 /* 16Mhz 68030 */ ! 133: #define HP_375 6 /* 50Mhz 68030+32K external cache */ ! 134: ! 135: /* values for mmutype (assigned for quick testing) */ ! 136: #define MMU_68030 -1 /* 68030 on-chip subset of 68851 */ ! 137: #define MMU_HP 0 /* HP proprietary */ ! 138: #define MMU_68851 1 /* Motorola 68851 */ ! 139: ! 140: /* values for ectype */ ! 141: #define EC_PHYS -1 /* external physical address cache */ ! 142: #define EC_NONE 0 /* no external cache */ ! 143: #define EC_VIRT 1 /* external virtual address cache */ ! 144: ! 145: /* values for cpuspeed (not really related to clock speed due to caches) */ ! 146: #define MHZ_8 1 ! 147: #define MHZ_16 2 ! 148: #define MHZ_25 3 ! 149: #define MHZ_33 4 ! 150: #define MHZ_50 6 ! 151: ! 152: #ifdef KERNEL ! 153: extern int machineid, mmutype, ectype; ! 154: extern char *intiobase, *intiolimit; ! 155: ! 156: /* what is this supposed to do? i.e. how is it different than startrtclock? */ ! 157: #define enablertclock() ! 158: ! 159: #endif ! 160: ! 161: /* physical memory sections */ ! 162: #define ROMBASE (0x00000000) ! 163: #define INTIOBASE (0x00400000) ! 164: #define INTIOTOP (0x00600000) ! 165: #define EXTIOBASE (0x00600000) ! 166: #define EXTIOTOP (0x20000000) ! 167: #define MAXADDR (0xFFFFF000) ! 168: ! 169: /* ! 170: * Internal IO space: ! 171: * ! 172: * Ranges from 0x400000 to 0x600000 (IIOMAPSIZE). ! 173: * ! 174: * Internal IO space is mapped in the kernel from ``intiobase'' to ! 175: * ``intiolimit'' (defined in locore.s). Since it is always mapped, ! 176: * conversion between physical and kernel virtual addresses is easy. ! 177: */ ! 178: #define ISIIOVA(va) \ ! 179: ((char *)(va) >= intiobase && (char *)(va) < intiolimit) ! 180: #define IIOV(pa) ((int)(pa)-INTIOBASE+(int)intiobase) ! 181: #define IIOP(va) ((int)(va)-(int)intiobase+INTIOBASE) ! 182: #define IIOPOFF(pa) ((int)(pa)-INTIOBASE) ! 183: #define IIOMAPSIZE btoc(INTIOTOP-INTIOBASE) /* 2mb */ ! 184: ! 185: /* ! 186: * External IO space: ! 187: * ! 188: * DIO ranges from select codes 0-63 at physical addresses given by: ! 189: * 0x600000 + (sc - 32) * 0x10000 ! 190: * DIO cards are addressed in the range 0-31 [0x600000-0x800000) for ! 191: * their control space and the remaining areas, [0x200000-0x400000) and ! 192: * [0x800000-0x1000000), are for additional space required by a card; ! 193: * e.g. a display framebuffer. ! 194: * ! 195: * DIO-II ranges from select codes 132-255 at physical addresses given by: ! 196: * 0x1000000 + (sc - 132) * 0x400000 ! 197: * The address range of DIO-II space is thus [0x1000000-0x20000000). ! 198: * ! 199: * DIO/DIO-II space is too large to map in its entirety, instead devices ! 200: * are mapped into kernel virtual address space allocated from a range ! 201: * of EIOMAPSIZE pages (vmparam.h) starting at ``extiobase''. ! 202: */ ! 203: #define DIOBASE (0x600000) ! 204: #define DIOTOP (0x1000000) ! 205: #define DIOCSIZE (0x10000) ! 206: #define DIOIIBASE (0x01000000) ! 207: #define DIOIITOP (0x20000000) ! 208: #define DIOIICSIZE (0x00400000) ! 209: ! 210: /* ! 211: * HP MMU ! 212: */ ! 213: #define MMUBASE IIOPOFF(0x5F4000) ! 214: #define MMUSSTP 0x0 ! 215: #define MMUUSTP 0x4 ! 216: #define MMUTBINVAL 0x8 ! 217: #define MMUSTAT 0xC ! 218: #define MMUCMD MMUSTAT ! 219: ! 220: #define MMU_UMEN 0x0001 /* enable user mapping */ ! 221: #define MMU_SMEN 0x0002 /* enable supervisor mapping */ ! 222: #define MMU_CEN 0x0004 /* enable data cache */ ! 223: #define MMU_BERR 0x0008 /* bus error */ ! 224: #define MMU_IEN 0x0020 /* enable instruction cache */ ! 225: #define MMU_FPE 0x0040 /* enable 68881 FP coprocessor */ ! 226: #define MMU_WPF 0x2000 /* write protect fault */ ! 227: #define MMU_PF 0x4000 /* page fault */ ! 228: #define MMU_PTF 0x8000 /* page table fault */ ! 229: ! 230: #define MMU_FAULT (MMU_PTF|MMU_PF|MMU_WPF|MMU_BERR) ! 231: #define MMU_ENAB (MMU_UMEN|MMU_SMEN|MMU_IEN|MMU_FPE) ! 232: ! 233: /* ! 234: * 68851 and 68030 MMU ! 235: */ ! 236: #define PMMU_LVLMASK 0x0007 ! 237: #define PMMU_INV 0x0400 ! 238: #define PMMU_WP 0x0800 ! 239: #define PMMU_ALV 0x1000 ! 240: #define PMMU_SO 0x2000 ! 241: #define PMMU_LV 0x4000 ! 242: #define PMMU_BE 0x8000 ! 243: #define PMMU_FAULT (PMMU_WP|PMMU_INV) ! 244: ! 245: /* 680X0 function codes */ ! 246: #define FC_USERD 1 /* user data space */ ! 247: #define FC_USERP 2 /* user program space */ ! 248: #define FC_PURGE 3 /* HPMMU: clear TLB entries */ ! 249: #define FC_SUPERD 5 /* supervisor data space */ ! 250: #define FC_SUPERP 6 /* supervisor program space */ ! 251: #define FC_CPU 7 /* CPU space */ ! 252: ! 253: /* fields in the 68020 cache control register */ ! 254: #define IC_ENABLE 0x0001 /* enable instruction cache */ ! 255: #define IC_FREEZE 0x0002 /* freeze instruction cache */ ! 256: #define IC_CE 0x0004 /* clear instruction cache entry */ ! 257: #define IC_CLR 0x0008 /* clear entire instruction cache */ ! 258: ! 259: /* additional fields in the 68030 cache control register */ ! 260: #define IC_BE 0x0010 /* instruction burst enable */ ! 261: #define DC_ENABLE 0x0100 /* data cache enable */ ! 262: #define DC_FREEZE 0x0200 /* data cache freeze */ ! 263: #define DC_CE 0x0400 /* clear data cache entry */ ! 264: #define DC_CLR 0x0800 /* clear entire data cache */ ! 265: #define DC_BE 0x1000 /* data burst enable */ ! 266: #define DC_WA 0x2000 /* write allocate */ ! 267: ! 268: #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) ! 269: #define CACHE_OFF (DC_CLR|IC_CLR) ! 270: #define CACHE_CLR (CACHE_ON) ! 271: #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) ! 272: #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)
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