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1.1 root 1: /*
2: * Copyright (c) 1988 University of Utah.
3: * Copyright (c) 1982, 1990 The Regents of the University of California.
4: * All rights reserved.
5: *
6: * This code is derived from software contributed to Berkeley by
7: * the Systems Programming Group of the University of Utah Computer
8: * Science Department.
9: *
10: * Redistribution and use in source and binary forms, with or without
11: * modification, are permitted provided that the following conditions
12: * are met:
13: * 1. Redistributions of source code must retain the above copyright
14: * notice, this list of conditions and the following disclaimer.
15: * 2. Redistributions in binary form must reproduce the above copyright
16: * notice, this list of conditions and the following disclaimer in the
17: * documentation and/or other materials provided with the distribution.
18: * 3. All advertising materials mentioning features or use of this software
19: * must display the following acknowledgement:
20: * This product includes software developed by the University of
21: * California, Berkeley and its contributors.
22: * 4. Neither the name of the University nor the names of its contributors
23: * may be used to endorse or promote products derived from this software
24: * without specific prior written permission.
25: *
26: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36: * SUCH DAMAGE.
37: *
38: * from: Utah $Hdr: cpu.h 1.16 91/03/25$
39: *
1.1.1.2 ! root 40: * from: @(#)cpu.h 7.7 (Berkeley) 6/27/91
! 41: * cpu.h,v 1.2 1993/05/22 07:58:17 cgd Exp
1.1 root 42: */
43:
44: /*
45: * Exported definitions unique to hp300/68k cpu support.
46: */
47:
48: /*
49: * definitions of cpu-dependent requirements
50: * referenced in generic code
51: */
52: #define COPY_SIGCODE /* copy sigcode above user stack in exec */
53:
54: /*
55: * function vs. inline configuration;
56: * these are defined to get generic functions
57: * rather than inline or machine-dependent implementations
58: */
59: #define NEED_MINMAX /* need {,i,l,ul}{min,max} functions */
60: #undef NEED_FFS /* don't need ffs function */
61: #undef NEED_BCMP /* don't need bcmp function */
62: #undef NEED_STRLEN /* don't need strlen function */
63:
64: #define cpu_exec(p) /* nothing */
65: #define cpu_wait(p) /* nothing */
66:
67: /*
68: * Arguments to hardclock, softclock and gatherstats
69: * encapsulate the previous machine state in an opaque
70: * clockframe; for hp300, use just what the hardware
71: * leaves on the stack.
72: */
73: typedef struct intrframe {
74: int pc;
75: int ps;
76: } clockframe;
77:
78: #define CLKF_USERMODE(framep) (((framep)->ps & PSL_S) == 0)
79: #define CLKF_BASEPRI(framep) (((framep)->ps & PSL_IPL7) == 0)
80: #define CLKF_PC(framep) ((framep)->pc)
81:
82:
83: /*
84: * Preempt the current process if in interrupt from user mode,
85: * or after the current trap/syscall if in system mode.
86: */
87: #define need_resched() { want_resched++; aston(); }
88:
89: /*
90: * Give a profiling tick to the current process from the softclock
91: * interrupt. On hp300, request an ast to send us through trap(),
92: * marking the proc as needing a profiling tick.
93: */
94: #define profile_tick(p, framep) { (p)->p_flag |= SOWEUPC; aston(); }
95:
96: /*
97: * Notify the current process (p) that it has a signal pending,
98: * process as soon as possible.
99: */
100: #define signotify(p) aston()
101:
102: #define aston() (astpending++)
103:
104: int astpending; /* need to trap before returning to user mode */
105: int want_resched; /* resched() was called */
106:
107:
108: /*
109: * simulated software interrupt register
110: */
111: extern unsigned char ssir;
112:
113: #define SIR_NET 0x1
114: #define SIR_CLOCK 0x2
115:
116: #define siroff(x) ssir &= ~(x)
117: #define setsoftnet() ssir |= SIR_NET
118: #define setsoftclock() ssir |= SIR_CLOCK
119:
120:
121:
122: /*
123: * The rest of this should probably be moved to ../hp300/hp300cpu.h,
124: * although some of it could probably be put into generic 68k headers.
125: */
126:
127: /* values for machineid */
128: #define HP_320 0 /* 16Mhz 68020+HP MMU+16K external cache */
129: #define HP_330 1 /* 16Mhz 68020+68851 MMU */
130: #define HP_350 2 /* 25Mhz 68020+HP MMU+32K external cache */
131: #define HP_360 3 /* 25Mhz 68030 */
132: #define HP_370 4 /* 33Mhz 68030+64K external cache */
133: #define HP_340 5 /* 16Mhz 68030 */
134: #define HP_375 6 /* 50Mhz 68030+32K external cache */
135:
136: /* values for mmutype (assigned for quick testing) */
137: #define MMU_68030 -1 /* 68030 on-chip subset of 68851 */
138: #define MMU_HP 0 /* HP proprietary */
139: #define MMU_68851 1 /* Motorola 68851 */
140:
141: /* values for ectype */
142: #define EC_PHYS -1 /* external physical address cache */
143: #define EC_NONE 0 /* no external cache */
144: #define EC_VIRT 1 /* external virtual address cache */
145:
146: /* values for cpuspeed (not really related to clock speed due to caches) */
147: #define MHZ_8 1
148: #define MHZ_16 2
149: #define MHZ_25 3
150: #define MHZ_33 4
151: #define MHZ_50 6
152:
153: #ifdef KERNEL
154: extern int machineid, mmutype, ectype;
155: extern char *intiobase, *intiolimit;
156:
157: /* what is this supposed to do? i.e. how is it different than startrtclock? */
158: #define enablertclock()
159:
160: #endif
161:
162: /* physical memory sections */
163: #define ROMBASE (0x00000000)
164: #define INTIOBASE (0x00400000)
165: #define INTIOTOP (0x00600000)
166: #define EXTIOBASE (0x00600000)
167: #define EXTIOTOP (0x20000000)
168: #define MAXADDR (0xFFFFF000)
169:
170: /*
171: * Internal IO space:
172: *
173: * Ranges from 0x400000 to 0x600000 (IIOMAPSIZE).
174: *
175: * Internal IO space is mapped in the kernel from ``intiobase'' to
176: * ``intiolimit'' (defined in locore.s). Since it is always mapped,
177: * conversion between physical and kernel virtual addresses is easy.
178: */
179: #define ISIIOVA(va) \
180: ((char *)(va) >= intiobase && (char *)(va) < intiolimit)
181: #define IIOV(pa) ((int)(pa)-INTIOBASE+(int)intiobase)
182: #define IIOP(va) ((int)(va)-(int)intiobase+INTIOBASE)
183: #define IIOPOFF(pa) ((int)(pa)-INTIOBASE)
184: #define IIOMAPSIZE btoc(INTIOTOP-INTIOBASE) /* 2mb */
185:
186: /*
187: * External IO space:
188: *
189: * DIO ranges from select codes 0-63 at physical addresses given by:
190: * 0x600000 + (sc - 32) * 0x10000
191: * DIO cards are addressed in the range 0-31 [0x600000-0x800000) for
192: * their control space and the remaining areas, [0x200000-0x400000) and
193: * [0x800000-0x1000000), are for additional space required by a card;
194: * e.g. a display framebuffer.
195: *
196: * DIO-II ranges from select codes 132-255 at physical addresses given by:
197: * 0x1000000 + (sc - 132) * 0x400000
198: * The address range of DIO-II space is thus [0x1000000-0x20000000).
199: *
200: * DIO/DIO-II space is too large to map in its entirety, instead devices
201: * are mapped into kernel virtual address space allocated from a range
202: * of EIOMAPSIZE pages (vmparam.h) starting at ``extiobase''.
203: */
204: #define DIOBASE (0x600000)
205: #define DIOTOP (0x1000000)
206: #define DIOCSIZE (0x10000)
207: #define DIOIIBASE (0x01000000)
208: #define DIOIITOP (0x20000000)
209: #define DIOIICSIZE (0x00400000)
210:
211: /*
212: * HP MMU
213: */
214: #define MMUBASE IIOPOFF(0x5F4000)
215: #define MMUSSTP 0x0
216: #define MMUUSTP 0x4
217: #define MMUTBINVAL 0x8
218: #define MMUSTAT 0xC
219: #define MMUCMD MMUSTAT
220:
221: #define MMU_UMEN 0x0001 /* enable user mapping */
222: #define MMU_SMEN 0x0002 /* enable supervisor mapping */
223: #define MMU_CEN 0x0004 /* enable data cache */
224: #define MMU_BERR 0x0008 /* bus error */
225: #define MMU_IEN 0x0020 /* enable instruction cache */
226: #define MMU_FPE 0x0040 /* enable 68881 FP coprocessor */
227: #define MMU_WPF 0x2000 /* write protect fault */
228: #define MMU_PF 0x4000 /* page fault */
229: #define MMU_PTF 0x8000 /* page table fault */
230:
231: #define MMU_FAULT (MMU_PTF|MMU_PF|MMU_WPF|MMU_BERR)
232: #define MMU_ENAB (MMU_UMEN|MMU_SMEN|MMU_IEN|MMU_FPE)
233:
234: /*
235: * 68851 and 68030 MMU
236: */
237: #define PMMU_LVLMASK 0x0007
238: #define PMMU_INV 0x0400
239: #define PMMU_WP 0x0800
240: #define PMMU_ALV 0x1000
241: #define PMMU_SO 0x2000
242: #define PMMU_LV 0x4000
243: #define PMMU_BE 0x8000
244: #define PMMU_FAULT (PMMU_WP|PMMU_INV)
245:
246: /* 680X0 function codes */
247: #define FC_USERD 1 /* user data space */
248: #define FC_USERP 2 /* user program space */
249: #define FC_PURGE 3 /* HPMMU: clear TLB entries */
250: #define FC_SUPERD 5 /* supervisor data space */
251: #define FC_SUPERP 6 /* supervisor program space */
252: #define FC_CPU 7 /* CPU space */
253:
254: /* fields in the 68020 cache control register */
255: #define IC_ENABLE 0x0001 /* enable instruction cache */
256: #define IC_FREEZE 0x0002 /* freeze instruction cache */
257: #define IC_CE 0x0004 /* clear instruction cache entry */
258: #define IC_CLR 0x0008 /* clear entire instruction cache */
259:
260: /* additional fields in the 68030 cache control register */
261: #define IC_BE 0x0010 /* instruction burst enable */
262: #define DC_ENABLE 0x0100 /* data cache enable */
263: #define DC_FREEZE 0x0200 /* data cache freeze */
264: #define DC_CE 0x0400 /* clear data cache entry */
265: #define DC_CLR 0x0800 /* clear entire data cache */
266: #define DC_BE 0x1000 /* data burst enable */
267: #define DC_WA 0x2000 /* write allocate */
268:
269: #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
270: #define CACHE_OFF (DC_CLR|IC_CLR)
271: #define CACHE_CLR (CACHE_ON)
272: #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
273: #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)
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