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Annotation of Net2/arch/i386/isa/ic/ds8390.h, revision 1.1

1.1     ! root        1: /*-
        !             2:  * Copyright (c) 1991 The Regents of the University of California.
        !             3:  * All rights reserved.
        !             4:  *
        !             5:  * Redistribution and use in source and binary forms, with or without
        !             6:  * modification, are permitted provided that the following conditions
        !             7:  * are met:
        !             8:  * 1. Redistributions of source code must retain the above copyright
        !             9:  *    notice, this list of conditions and the following disclaimer.
        !            10:  * 2. Redistributions in binary form must reproduce the above copyright
        !            11:  *    notice, this list of conditions and the following disclaimer in the
        !            12:  *    documentation and/or other materials provided with the distribution.
        !            13:  * 3. All advertising materials mentioning features or use of this software
        !            14:  *    must display the following acknowledgement:
        !            15:  *     This product includes software developed by the University of
        !            16:  *     California, Berkeley and its contributors.
        !            17:  * 4. Neither the name of the University nor the names of its contributors
        !            18:  *    may be used to endorse or promote products derived from this software
        !            19:  *    without specific prior written permission.
        !            20:  *
        !            21:  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
        !            22:  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
        !            23:  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
        !            24:  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
        !            25:  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
        !            26:  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
        !            27:  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
        !            28:  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
        !            29:  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
        !            30:  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
        !            31:  * SUCH DAMAGE.
        !            32:  *
        !            33:  *     @(#)ds8390.h    7.1 (Berkeley) 5/9/91
        !            34:  */
        !            35: 
        !            36: /*
        !            37:  * Nominal Semidestructor DS8390 Ethernet Chip
        !            38:  * Register and bit definitions
        !            39:  */
        !            40: 
        !            41: /*
        !            42:  * Page register offset values
        !            43:  */
        !            44: #define ds_cmd         0x00            /* Command register:            */
        !            45: #define  DSCM_STOP      0x01           /*      Stop controller         */
        !            46: #define  DSCM_START     0x02           /*      Start controller        */
        !            47: #define  DSCM_TRANS     0x04           /*      Transmit packet         */
        !            48: #define  DSCM_RREAD     0x08           /*      Remote read             */
        !            49: #define  DSCM_RWRITE    0x10           /*      Remote write            */
        !            50: #define  DSCM_NODMA     0x20           /*      No Remote DMA present   */
        !            51: #define  DSCM_PG0       0x00           /*      Select Page 0           */
        !            52: #define  DSCM_PG1       0x40           /*      Select Page 1           */
        !            53: #define  DSCM_PG2       0x80           /*      Select Page 2?          */
        !            54: 
        !            55: #define ds0_pstart     0x01            /* Page Start register          */
        !            56: #define ds0_pstop      0x02            /* Page Stop register           */
        !            57: #define ds0_bnry       0x03            /* Boundary Pointer             */
        !            58: 
        !            59: #define ds0_tsr                0x04            /* Transmit Status (read-only)  */
        !            60: #define         DSTS_PTX        0x01           /*  Successful packet transmit  */ 
        !            61: #define         DSTS_COLL       0x04           /*  Packet transmit w/ collision*/ 
        !            62: #define         DSTS_COLL16     0x04           /*  Packet had >16 collisions & fail */ 
        !            63: #define         DSTS_UND        0x20           /*  FIFO Underrun on transmission*/ 
        !            64: 
        !            65: #define ds0_tpsr       ds0_tsr         /* Transmit Page (write-only)   */
        !            66: #define ds0_tbcr0      0x05            /* Transmit Byte count, low  WO */
        !            67: #define ds0_tbcr1      0x06            /* Transmit Byte count, high WO */
        !            68: 
        !            69: #define ds0_isr                0x07            /* Interrupt status register    */
        !            70: #define         DSIS_RX         0x01           /*  Successful packet reception */ 
        !            71: #define         DSIS_TX         0x02           /*  Successful packet transmission  */ 
        !            72: #define         DSIS_RXE        0x04           /*  Packet reception  w/error   */ 
        !            73: #define         DSIS_TXE        0x08           /*  Packet transmission  w/error*/ 
        !            74: #define         DSIS_ROVRN      0x10           /*  Receiver overrun in the ring*/
        !            75: #define         DSIS_CTRS       0x20           /*  Diagnostic counters need attn */
        !            76: #define         DSIS_RDC        0x40           /*  Remote DMA Complete         */
        !            77: #define         DSIS_RESET      0x80           /*  Reset Complete              */
        !            78: 
        !            79: #define ds0_rsar0      0x08            /* Remote start address low  WO */
        !            80: #define ds0_rsar1      0x09            /* Remote start address high WO */
        !            81: #define ds0_rbcr0      0x0A            /* Remote byte count low     WO */
        !            82: #define ds0_rbcr1      0x0B            /* Remote byte count high    WO */
        !            83: 
        !            84: #define ds0_rsr                0x0C            /* Receive status            RO */
        !            85: #define         DSRS_RPC        0x01           /*  Received Packet Complete    */
        !            86: 
        !            87: #define ds0_rcr                ds0_rsr         /* Receive configuration     WO */
        !            88: #define  DSRC_SEP       0x01           /* Save error packets           */
        !            89: #define  DSRC_AR        0x02           /* Accept Runt packets          */
        !            90: #define  DSRC_AB        0x04           /* Accept Broadcast packets     */
        !            91: #define  DSRC_AM        0x08           /* Accept Multicast packets     */
        !            92: #define  DSRC_PRO       0x10           /* Promiscuous physical         */
        !            93: #define  DSRC_MON       0x20           /* Monitor mode                 */
        !            94: 
        !            95: #define ds0_tcr                0x0D            /* Transmit configuration    WO */
        !            96: #define  DSTC_CRC      0x01            /* Inhibit CRC                  */
        !            97: #define  DSTC_LB0      0x02            /* Encoded Loopback Control     */
        !            98: #define  DSTC_LB1      0x04            /* Encoded Loopback Control     */
        !            99: #define  DSTC_ATD      0x08            /* Auto Transmit Disable        */
        !           100: #define  DSTC_OFST     0x10            /* Collision Offset Enable      */
        !           101: 
        !           102: #define ds0_rcvalctr   ds0_tcr         /* Receive alignment err ctr RO */
        !           103: 
        !           104: #define ds0_dcr                0x0E            /* Data configuration        WO */
        !           105: #define  DSDC_WTS       0x01           /* Word Transfer Select         */
        !           106: #define  DSDC_BOS       0x02           /* Byte Order Select            */
        !           107: #define  DSDC_LAS       0x04           /* Long Address Select          */
        !           108: #define  DSDC_BMS       0x08           /* Burst Mode Select            */
        !           109: #define  DSDC_AR        0x10           /* Autoinitialize Remote        */
        !           110: #define  DSDC_FT0       0x20           /* Fifo Threshold Select        */
        !           111: #define  DSDC_FT1       0x40           /* Fifo Threshold Select        */
        !           112: 
        !           113: #define ds0_rcvcrcctr  ds0_dcr         /* Receive CRC error counter RO */
        !           114: 
        !           115: #define ds0_imr                0x0F            /* Interrupt mask register   WO */
        !           116: #define  DSIM_PRXE      0x01           /*  Packet received enable      */
        !           117: #define  DSIM_PTXE      0x02           /*  Packet transmitted enable   */
        !           118: #define  DSIM_RXEE      0x04           /*  Receive error enable        */
        !           119: #define  DSIM_TXEE      0x08           /*  Transmit error enable       */
        !           120: #define  DSIM_OVWE      0x10           /*  Overwrite warning enable    */
        !           121: #define  DSIM_CNTE      0x20           /*  Counter overflow enable     */
        !           122: #define  DSIM_RDCE      0x40           /*  Dma complete enable         */
        !           123: 
        !           124: #define ds0_rcvfrmctr  ds0_imr         /* Receive Frame error cntr  RO */
        !           125: 
        !           126: 
        !           127: #define ds1_par0       ds0_pstart      /* Physical address register 0  */
        !           128:                                /* Physical address registers 1-4       */
        !           129: #define ds1_par5       ds0_tbcr1       /* Physical address register 5  */
        !           130: #define ds1_curr       ds0_isr         /* Current page (receive unit)  */
        !           131: #define ds1_mar0       ds0_rsar0       /* Multicast address register 0 */
        !           132:                                /* Multicast address registers 1-6      */
        !           133: #define ds1_mar7       ds0_imr         /* Multicast address register 7 */
        !           134: #define ds1_curr       ds0_isr         /* Current page (receive unit)  */
        !           135: 
        !           136: #define DS_PGSIZE      256             /* Size of RAM pages in bytes   */
        !           137: 
        !           138: /*
        !           139:  * Packet receive header, 1 per each buffer page used in receive packet
        !           140:  */
        !           141: struct prhdr {
        !           142:        u_char  pr_status;      /* is this a good packet, same as ds0_rsr */
        !           143:        u_char  pr_nxtpg;       /* next page of packet or next packet */
        !           144:        u_char  pr_sz0;
        !           145:        u_char  pr_sz1;
        !           146: };

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