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1.1 root 1: /*-
2: * Copyright (c) 1990 The Regents of the University of California.
3: * All rights reserved.
4: *
5: * This code is derived from software contributed to Berkeley by
6: * William Jolitz.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: * 3. All advertising materials mentioning features or use of this software
17: * must display the following acknowledgement:
18: * This product includes software developed by the University of
19: * California, Berkeley and its contributors.
20: * 4. Neither the name of the University nor the names of its contributors
21: * may be used to endorse or promote products derived from this software
22: * without specific prior written permission.
23: *
24: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34: * SUCH DAMAGE.
35: *
36: * @(#)icu.h 5.6 (Berkeley) 5/9/91
37: */
38:
39: /*
40: * AT/386 Interrupt Control constants
41: * W. Jolitz 8/89
42: */
43:
44: #ifndef __ICU__
45: #define __ICU__
46:
47: #ifndef LOCORE
48:
49: /*
50: * Interrupt "level" mechanism variables, masks, and macros
51: */
52: extern unsigned short imen; /* interrupt mask enable */
53: extern unsigned short cpl; /* current priority level mask */
54:
55: extern unsigned short highmask; /* group of interrupts masked with splhigh() */
56: extern unsigned short ttymask; /* group of interrupts masked with spltty() */
57: extern unsigned short biomask; /* group of interrupts masked with splbio() */
58: extern unsigned short netmask; /* group of interrupts masked with splimp() */
59:
60: #define INTREN(s) imen &= ~(s)
61: #define INTRDIS(s) imen |= (s)
62: #define INTRMASK(msk,s) msk |= (s)
63:
64: #else
65:
66: /*
67: * Macro's for interrupt level priority masks (used in interrupt vector entry)
68: */
69:
70: /* Mask a group of interrupts atomically */
71: #define INTR(unit,mask,offst) \
72: pushl $0 ; \
73: pushl $ T_ASTFLT ; \
74: pushal ; \
75: push %ds ; \
76: push %es ; \
77: movw $0x10, %ax ; \
78: movw %ax, %ds ; \
79: movw %ax,%es ; \
80: incl _cnt+V_INTR ; \
81: incl _isa_intr + offst * 4 ; \
82: movzwl _cpl,%eax ; \
83: pushl %eax ; \
84: pushl $ unit ; \
85: orw mask ,%ax ; \
86: movw %ax,_cpl ; \
87: orw _imen,%ax ; \
88: NOP ; \
89: outb %al,$ IO_ICU1+1 ; \
90: NOP ; \
91: movb %ah,%al ; \
92: outb %al,$ IO_ICU2+1 ; \
93: NOP ; \
94: inb $0x84,%al ; \
95: sti
96:
97: /* Interrupt vector exit macros */
98:
99: /* First eight interrupts (ICU1) */
100: #define INTREXIT1 \
101: movb $0x20,%al ; \
102: outb %al,$ IO_ICU1 ; \
103: jmp doreti
104:
105: /* Second eight interrupts (ICU2) */
106: #define INTREXIT2 \
107: movb $0x20,%al ; \
108: outb %al,$ IO_ICU1 ; \
109: outb %al,$ IO_ICU2 ; \
110: jmp doreti
111:
112: #endif
113:
114: /*
115: * Interrupt enable bits -- in order of priority
116: */
117: #define IRQ0 0x0001 /* highest priority - timer */
118: #define IRQ1 0x0002
119: #define IRQ_SLAVE 0x0004
120: #define IRQ8 0x0100
121: #define IRQ9 0x0200
122: #define IRQ2 IRQ9
123: #define IRQ10 0x0400
124: #define IRQ11 0x0800
125: #define IRQ12 0x1000
126: #define IRQ13 0x2000
127: #define IRQ14 0x4000
128: #define IRQ15 0x8000
129: #define IRQ3 0x0008
130: #define IRQ4 0x0010
131: #define IRQ5 0x0020
132: #define IRQ6 0x0040
133: #define IRQ7 0x0080 /* lowest - parallel printer */
134:
135: /*
136: * Interrupt Control offset into Interrupt descriptor table (IDT)
137: */
138: #define ICU_OFFSET 32 /* 0-31 are processor exceptions */
139: #define ICU_LEN 16 /* 32-47 are ISA interrupts */
140:
141: #endif __ICU__
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