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1.1 root 1: /*
2: * Copyright (c) 1991 The Regents of the University of California.
3: * All rights reserved.
4: *
5: * This code is derived from software contributed to Berkeley by
6: * Tim L. Tucker.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: * 3. All advertising materials mentioning features or use of this software
17: * must display the following acknowledgement:
18: * This product includes software developed by the University of
19: * California, Berkeley and its contributors.
20: * 4. Neither the name of the University nor the names of its contributors
21: * may be used to endorse or promote products derived from this software
22: * without specific prior written permission.
23: *
24: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34: * SUCH DAMAGE.
35: *
36: * A lot of this was derived from if_wereg.h and 3c503.asm.
1.1.1.2 ! root 37: *
! 38: * if_ec.h,v 1.4 1993/05/22 08:01:17 cgd Exp
1.1 root 39: */
1.1.1.2 ! root 40:
1.1 root 41: /*
42: * receive ring discriptor
43: *
44: * The National Semiconductor DS8390 Network interface controller uses
45: * the following receive ring headers. The way this works is that the
46: * memory on the interface card is chopped up into 256 bytes blocks.
47: * A contiguous portion of those blocks are marked for receive packets
48: * by setting start and end block #'s in the NIC. For each packet that
49: * is put into the receive ring, one of these headers (4 bytes each) is
50: * tacked onto the front.
51: */
52: struct ec_ring {
53: struct ecr_status { /* received packet status */
54: u_char rs_prx:1, /* packet received intack */
55: rs_crc:1, /* crc error */
56: rs_fae:1, /* frame alignment error */
57: rs_fo:1, /* fifo overrun */
58: rs_mpa:1, /* packet received intack */
59: rs_phy:1, /* packet received intack */
60: rs_dis:1, /* packet received intack */
61: rs_dfr:1; /* packet received intack */
62: } ec_rcv_status; /* received packet status */
63: u_char ec_next_packet; /* pointer to next packet */
64: u_short ec_count; /* bytes in packet (length + 4) */
65: };
66:
67: #define EC_PAGE_SIZE 256
68: #define EC_TXBUF_SIZE 0x06
69: #define EC_VMEM_OFFSET 0x20
70: #define EC_RXBUF_OFFSET 0x26
71: #define EC_RXBUF_END 0x40
72: #define EC_ROM_OFFSET 8
73: #define ETHER_ADDR_LEN 6
74: #define ETHER_MIN_LEN 64
75: #define ETHER_HDR_SIZE 14
76: /*
77: * Share memory management parameters.
78: */
79: #define XMIT_MTU 0x600
80: #define SM_TSTART_PG 0x020
81: #define SM_RSTART_PG 0x026
82: #define SM_RSTOP_PG 0x040
83: /*
84: * Description of header of each packet in receive area of shared memory.
85: */
86: #define EN_RBUF_STAT 0x0 /* Received frame status. */
87: #define EN_RBUF_NXT_PG 0x1 /* Page after this frame */
88: #define EN_RBUF_SIZE_LO 0x2 /* Length of this frame */
89: #define EN_RBUF_SIZE_HI 0x3 /* Length of this frame */
90: #define EN_RBUF_NHDR 0x4 /* Length of above header area */
91: /*
92: * E33 Control registers. (base + 40x)
93: */
94: #define E33G 0x0
95: #define E33G_STARTPG 0x0
96: #define E33G_STOPPG 0x1
97: #define E33G_NBURST 0x2
98: #define E33G_IOBASE 0x3
99: #define E33G_ROMBASE 0x4
100: #define E33G_GACFR 0x5
101: #define E33G_CNTRL 0x6
102: #define E33G_STATUS 0x7
103: #define E33G_IDCFR 0x8
104: #define E33G_DMAAH 0x9
105: #define E33G_DMAAL 0xa
106: #define E33G_VP2 0xb
107: #define E33G_VP1 0xc
108: #define E33G_VP0 0xd
109: #define E33G_FIFOH 0xe
110: #define E33G_FIFOL 0xf
111: /*
112: * Bits in E33G_GACFR register.
113: */
114: #define EGACFR_NORM 0x49
115: #define EGACFR_IRQOFF 0xc9
116: /*
117: * Control bits for E33G_CNTRL
118: */
119: #define ECNTRL_RESET 0x01 /* Software reset of ASIC and 8390. */
1.1.1.2 ! root 120: #define ECNTRL_ONBOARD 0x02 /* Enable on-board transceiver. */
1.1 root 121: #define ECNTRL_SAPROM 0x04 /* Map Address Prom. */
122: #define ECNTRL_DBLBFR 0x20 /* FIFO Configuration bit */
123: #define ECNTRL_OUTPUT 0x40 /* PC->3c503 direction if set*/
124: #define ECNTRL_START 0x80 /* Start DMA Logic. */
125: /*
126: * Bits in E33G status register.
127: */
128: #define ESTAT_DPRDY 0x80 /* Data port of FIFO ready */
129: #define ESTAT_UFLW 0x40 /* Tried to read FIFO when it was empty. */
130: #define ESTAT_OFLW 0x20 /* Tried to write FIFO when it was full */
131: #define ESTAT_DTC 0x10 /* Terminal count from PC bus DMA Logic */
132: #define ESTAT_DIP 0x8 /* DMA in progress */
133: /*
134: * 8390 chip registers.
135: */
136: #define EN_CCMD 0x0 /* Chip's command register. */
137: #define EN0_STARTPG 0x1 /* Starting page of ring buffer. */
138: #define EN0_STOPPG 0x2 /* Ending page + 1 of ring buffer */
139: #define EN0_BOUNDARY 0x3 /* Boundary page of ring buffer */
140: #define EN0_TSR 0x4 /* Transmit status register. */
141: #define EN0_TPSR 0x4 /* Transmit starting page. */
142: #define EN0_TCNTLO 0x5 /* Low byte of tx byte count */
143: #define EN0_TCNTHI 0x6 /* High byte of tx byte count */
144: #define EN0_ISR 0x7 /* Interrupt status register. */
145: #define EN0_RSARLO 0x8 /* Remote start address reg 0 */
146: #define EN0_RSARHI 0x9 /* Remote start address reg 1 */
147: #define EN0_RCNTLO 0xa /* Remote byte count reg */
148: #define EN0_RCNTHI 0xb /* Remote byte count reg */
149: #define EN0_RXCR 0xc /* RX Control reg */
150: #define EN0_TXCR 0xd /* TX Control reg */
151: #define EN0_COUNTER0 0xd /* Rcv alignment error counter */
152: #define EN0_DCFG 0xe /* Data configuration reg */
153: #define EN0_COUNTER1 0xe /* rcv CRC error counter */
154: #define EN0_IMR 0xf /* Interrupt mask reg */
155: #define EN0_COUNTER2 0xf /* rcv missed frame error counter */
156: #define EN1_PHYS 0x1 /* boards physical enet addr. */
157: #define EN1_CURPAG 0x7 /* current memory page. */
158: #define EN1_MULT 0x8 /* multicast filter mask array (8 bytes) */
159: /*
160: * Chip commands in EN_CCMD
161: */
162: #define ENC_STOP 0x1 /* Stop the chip. */
163: #define ENC_START 0x2 /* Start the chip */
164: #define ENC_TRANS 0x4 /* Transmit a frame. */
165: #define ENC_RREAD 0x8 /* Remote read. */
166: #define ENC_RWRITE 0x10 /* Remote write */
167: #define ENC_NODMA 0x20 /* No remote DMA used on this card */
168: #define ENC_PAGE0 0x0 /* Select page 0 of chip regs */
169: #define ENC_PAGE1 0x40 /* Select page 1 of chip regs */
170: /*
171: * Commands for RX control reg
172: */
173: #define ENRXCR_MON 0x20 /* Monitor mode (no packets rcvd) */
174: #define ENRXCR_PROMP 0x10 /* Promiscuous phys addresses. */
175: #define ENRXCR_MULTI 0x8 /* Multicast (if pass filter) */
176: #define ENRXCR_BCST 0x4 /* Accept broadcasts */
177: #define ENRXCR_BAD 0x3 /* Accept runts and bad CRC frames */
178: /*
179: * Commands for TX control reg
180: */
181: #define ENTXCR_LOOP 0x2 /* Set loopback mode */
182: /*
183: * bits on the EN0_DCFG config register.
184: */
185: #define ENDCFG_BM8 0x48 /* Set bust mode, 8 deep FIFO */
186: /*
187: * Bits in the EN0_ISR Interrup Status Register
188: */
189: #define ENISR_RX 0x1 /* receiver, no error */
190: #define ENISR_TX 0x2 /* transmitter, no error */
191: #define ENISR_RX_ERR 0x4 /* Receiver with error */
192: #define ENISR_TX_ERR 0x8 /* Transmitter with error */
193: #define ENISR_OVER 0x10 /* receiver overwrote the ring */
194: #define ENISR_COUNTERS 0x20 /* Counters need emptying. */
195: #define ENISR_RDC 0x40 /* Remote DMA complete. */
196: #define ENISR_RESET 0x80 /* Reset completed */
197: #define ENISR_ALL 0x3f /* Interrupts we will enable */
198: /*
199: * Bits in received packet status byte and EN0_RSR
200: */
201: #define ENPS_RXOK 0x1 /* received a good packet */
202: /*
203: * Bits in TX status reg.
204: */
205: #define ENTSR_PTX 0x1 /* Packet transmitted without error */
206: #define ENTSR_COLL 0x4 /* Collided at least once */
207: #define ENTSR_COLL16 0x8 /* Collided 16 times and was dropped */
208: #define ENTSR_FU 0x20 /* TX FIFO Underrun */
209:
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