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Annotation of Net2/arch/i386/isa/if_wereg.h, revision 1.1

1.1     ! root        1: /*-
        !             2:  * Copyright (c) 1991 The Regents of the University of California.
        !             3:  * All rights reserved.
        !             4:  *
        !             5:  * This code is derived from software contributed to Berkeley by
        !             6:  * Tim L. Tucker.
        !             7:  *
        !             8:  * Redistribution and use in source and binary forms, with or without
        !             9:  * modification, are permitted provided that the following conditions
        !            10:  * are met:
        !            11:  * 1. Redistributions of source code must retain the above copyright
        !            12:  *    notice, this list of conditions and the following disclaimer.
        !            13:  * 2. Redistributions in binary form must reproduce the above copyright
        !            14:  *    notice, this list of conditions and the following disclaimer in the
        !            15:  *    documentation and/or other materials provided with the distribution.
        !            16:  * 3. All advertising materials mentioning features or use of this software
        !            17:  *    must display the following acknowledgement:
        !            18:  *     This product includes software developed by the University of
        !            19:  *     California, Berkeley and its contributors.
        !            20:  * 4. Neither the name of the University nor the names of its contributors
        !            21:  *    may be used to endorse or promote products derived from this software
        !            22:  *    without specific prior written permission.
        !            23:  *
        !            24:  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
        !            25:  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
        !            26:  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
        !            27:  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
        !            28:  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
        !            29:  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
        !            30:  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
        !            31:  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
        !            32:  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
        !            33:  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
        !            34:  * SUCH DAMAGE.
        !            35:  *
        !            36:  *     @(#)if_wereg.h  7.1 (Berkeley) 5/9/91
        !            37:  */
        !            38: 
        !            39: /*
        !            40:  * Western Digital 8003 ethernet/starlan adapter 
        !            41:  */
        !            42:  
        !            43: /*
        !            44:  * Memory Select Register (MSR)
        !            45:  */
        !            46: union we_mem_sel {
        !            47:     struct memory_decode {
        !            48:         u_char msd_addr:6,             /* Memory decode bits           */
        !            49:               msd_enable:1,            /* Memory (RAM) enable          */
        !            50:               msd_reset:1;             /* Software reset               */
        !            51:     } msd_decode;
        !            52: #define ms_addr                msd_decode.msd_addr
        !            53: #define ms_enable      msd_decode.msd_enable
        !            54: #define ms_reset       msd_decode.msd_reset
        !            55:     u_char ms_byte;                    /* entire byte                  */
        !            56: };
        !            57: 
        !            58: /*
        !            59:  * receive ring discriptor
        !            60:  *
        !            61:  * The National Semiconductor DS8390 Network interface controller uses
        !            62:  * the following receive ring headers.  The way this works is that the
        !            63:  * memory on the interface card is chopped up into 256 bytes blocks.
        !            64:  * A contiguous portion of those blocks are marked for receive packets
        !            65:  * by setting start and end block #'s in the NIC.  For each packet that
        !            66:  * is put into the receive ring, one of these headers (4 bytes each) is
        !            67:  * tacked onto the front.
        !            68:  */
        !            69: struct we_ring {
        !            70:        struct wer_status {             /* received packet status       */
        !            71:            u_char rs_prx:1,                /* packet received intack   */
        !            72:                   rs_crc:1,                /* crc error                */
        !            73:                   rs_fae:1,                /* frame alignment error    */
        !            74:                   rs_fo:1,                 /* fifo overrun             */
        !            75:                   rs_mpa:1,                /* packet received intack   */
        !            76:                   rs_phy:1,                /* packet received intack   */
        !            77:                   rs_dis:1,                /* packet received intack   */
        !            78:                   rs_dfr:1;                /* packet received intack   */
        !            79:        } we_rcv_status;                /* received packet status       */
        !            80:        u_char  we_next_packet;         /* pointer to next packet       */
        !            81:        u_short we_count;               /* bytes in packet (length + 4) */
        !            82: };
        !            83: 
        !            84: /*
        !            85:  * Command word definition
        !            86:  */
        !            87: union we_command {
        !            88:     struct command_decode {
        !            89:        u_char csd_stp:1,               /* STOP!                        */
        !            90:               csd_sta:1,               /* START!                       */
        !            91:                csd_txp:1,              /* Transmit packet              */
        !            92:                csd_rd:3,               /* Remote DMA command           */
        !            93:                csd_ps:2;               /* Page select                  */
        !            94:     } csd_decode;
        !            95: #define cs_stp         csd_decode.csd_stp
        !            96: #define cs_sta         csd_decode.csd_sta
        !            97: #define cs_txp         csd_decode.csd_txp
        !            98: #define cs_rd          csd_decode.csd_rd
        !            99: #define cs_ps          csd_decode.csd_ps
        !           100:     u_char cs_byte;                    /* entire command byte          */
        !           101: };
        !           102: 
        !           103: /*
        !           104:  * Interrupt status definition
        !           105:  */
        !           106: union we_interrupt {
        !           107:     struct interrupt_decode {
        !           108:        u_char isd_prx:1,               /* Packet received              */
        !           109:               isd_ptx:1,               /* Packet transmitted           */
        !           110:                isd_rxe:1,              /* Receive error                */
        !           111:                isd_txe:1,              /* Transmit error               */
        !           112:                isd_ovw:1,              /* Overwrite warning            */
        !           113:                isd_cnt:1,              /* Counter overflow             */
        !           114:                isd_rdc:1,              /* Remote DMA complete          */
        !           115:                isd_rst:1;              /* Reset status                 */
        !           116:     } isd_decode;
        !           117: #define is_prx         isd_decode.isd_prx
        !           118: #define is_ptx         isd_decode.isd_ptx
        !           119: #define is_rxe         isd_decode.isd_rxe
        !           120: #define is_txe         isd_decode.isd_txe
        !           121: #define is_ovw         isd_decode.isd_ovw
        !           122: #define is_cnt         isd_decode.isd_cnt
        !           123: #define is_rdc         isd_decode.isd_rdc
        !           124: #define is_rst         isd_decode.isd_rst
        !           125:     u_char is_byte;                    /* entire interrupt byte        */
        !           126: };
        !           127:  
        !           128: /*
        !           129:  * Status word definition (transmit)
        !           130:  */
        !           131: union wet_status {
        !           132:     struct tstat {
        !           133:        u_char tsd_ptx:1,               /* Packet transmitted intack    */
        !           134:               tsd_dfr:1,               /* Non deferred transmition     */
        !           135:                tsd_col:1,              /* Transmit Collided            */
        !           136:                tsd_abt:1,              /* Transmit Aborted (coll > 16) */
        !           137:                tsd_crs:1,              /* Carrier Sense Lost           */
        !           138:                tsd_fu:1,               /* Fifo Underrun                */
        !           139:                tsd_chd:1,              /* CD Heartbeat                 */
        !           140:                tsd_owc:1;              /* Out of Window Collision      */
        !           141:     } tsd_decode;
        !           142: #define ts_ptx         tsd_decode.tsd_ptx
        !           143: #define ts_dfr         tsd_decode.tsd_dfr
        !           144: #define ts_col         tsd_decode.tsd_col
        !           145: #define ts_abt         tsd_decode.tsd_abt
        !           146: #define ts_crs         tsd_decode.tsd_crs
        !           147: #define ts_fu          tsd_decode.tsd_fu
        !           148: #define ts_chd         tsd_decode.tsd_chd
        !           149: #define ts_owc         tsd_decode.tsd_owc
        !           150:     u_char ts_byte;                    /* entire transmit byte         */
        !           151: };
        !           152: 
        !           153: /*
        !           154:  * General constant definitions
        !           155:  */
        !           156: #define        WD_STARLAN      0x02            /* WD8003S Identification       */
        !           157: #define        WD_ETHER        0x03            /* WD8003E Identification       */
        !           158: #define        WD_ETHER2       0x05            /* WD8003EBT Identification     */
        !           159: #define WD_CHECKSUM    0xFF            /* Checksum byte                */
        !           160: #define WD_PAGE_SIZE   256             /* Size of RAM pages in bytes   */
        !           161: #define WD_TXBUF_SIZE  6               /* Size of TX buffer in pages   */
        !           162: #define WD_ROM_OFFSET  8               /* i/o base offset to ROM       */
        !           163: #define WD_IO_PORTS    32              /* # of i/o addresses used      */
        !           164: #define WD_NIC_OFFSET  16              /* i/o base offset to NIC       */
        !           165: 
        !           166: /*
        !           167:  * Page register offset values
        !           168:  */
        !           169: #define WD_P0_COMMAND  0x00            /* Command register             */
        !           170: #define WD_P0_PSTART   0x01            /* Page Start register          */
        !           171: #define WD_P0_PSTOP    0x02            /* Page Stop register           */
        !           172: #define WD_P0_BNRY     0x03            /* Boundary Pointer             */
        !           173: #define WD_P0_TSR      0x04            /* Transmit Status (read-only)  */
        !           174: #define WD_P0_TPSR     WD_P0_TSR       /* Transmit Page (write-only)   */
        !           175: #define WD_P0_TBCR0    0x05            /* Transmit Byte count, low  WO */
        !           176: #define WD_P0_TBCR1    0x06            /* Transmit Byte count, high WO */
        !           177: #define WD_P0_ISR      0x07            /* Interrupt status register    */
        !           178: #define WD_P0_RBCR0    0x0A            /* Remote byte count low     WO */
        !           179: #define WD_P0_RBCR1    0x0B            /* Remote byte count high    WO */
        !           180: #define WD_P0_RSR      0x0C            /* Receive status            RO */
        !           181: #define WD_P0_RCR      WD_P0_RSR       /* Receive configuration     WO */
        !           182: #define WD_P0_TCR      0x0D            /* Transmit configuration    WO */
        !           183: #define WD_P0_DCR      0x0E            /* Data configuration        WO */
        !           184: #define WD_P0_IMR      0x0F            /* Interrupt masks           WO */
        !           185: #define WD_P1_COMMAND  0x00            /* Command register             */
        !           186: #define WD_P1_PAR0     0x01            /* Physical address register 0  */
        !           187: #define WD_P1_PAR1     0x02            /* Physical address register 1  */
        !           188: #define WD_P1_PAR2     0x03            /* Physical address register 2  */
        !           189: #define WD_P1_PAR3     0x04            /* Physical address register 3  */
        !           190: #define WD_P1_PAR4     0x05            /* Physical address register 4  */
        !           191: #define WD_P1_PAR5     0x06            /* Physical address register 5  */
        !           192: #define WD_P1_CURR     0x07            /* Current page (receive unit)  */
        !           193: #define WD_P1_MAR0     0x08            /* Multicast address register 0 */
        !           194: 
        !           195: /*
        !           196:  * Configuration constants (receive unit)
        !           197:  */
        !           198: #define WD_R_SEP       0x01            /* Save error packets           */
        !           199: #define WD_R_AR                0x02            /* Accept Runt packets          */
        !           200: #define WD_R_AB                0x04            /* Accept Broadcast packets     */
        !           201: #define WD_R_AM                0x08            /* Accept Multicast packets     */
        !           202: #define WD_R_PRO       0x10            /* Promiscuous physical         */
        !           203: #define WD_R_MON       0x20            /* Monitor mode                 */
        !           204: #define WD_R_RES1      0x40            /* reserved...                  */
        !           205: #define WD_R_RES2      0x80            /* reserved...                  */
        !           206: #define        WD_R_CONFIG     (WD_R_AB)
        !           207: 
        !           208: /*
        !           209:  * Configuration constants (transmit unit)
        !           210:  */
        !           211: #define WD_T_CRC       0x01            /* Inhibit CRC                  */
        !           212: #define WD_T_LB0       0x02            /* Encoded Loopback Control     */
        !           213: #define WD_T_LB1       0x04            /* Encoded Loopback Control     */
        !           214: #define WD_T_ATD       0x08            /* Auto Transmit Disable        */
        !           215: #define WD_T_OFST      0x10            /* Collision Offset Enable      */
        !           216: #define WD_T_RES1      0x20            /* reserved...                  */
        !           217: #define WD_T_RES2      0x40            /* reserved...                  */
        !           218: #define WD_T_RES3      0x80            /* reserved...                  */
        !           219: #define        WD_T_CONFIG     (0)
        !           220: 
        !           221: /*
        !           222:  * Configuration constants (data unit)
        !           223:  */
        !           224: #define WD_D_WTS       0x01            /* Word Transfer Select         */
        !           225: #define WD_D_BOS       0x02            /* Byte Order Select            */
        !           226: #define WD_D_LAS       0x04            /* Long Address Select          */
        !           227: #define WD_D_BMS       0x08            /* Burst Mode Select            */
        !           228: #define WD_D_AR                0x10            /* Autoinitialize Remote        */
        !           229: #define WD_D_FT0       0x20            /* Fifo Threshold Select        */
        !           230: #define WD_D_FT1       0x40            /* Fifo Threshold Select        */
        !           231: #define WD_D_RES       0x80            /* reserved...                  */
        !           232: #define        WD_D_CONFIG     (WD_D_FT1|WD_D_BMS)
        !           233: 
        !           234: /*
        !           235:  * Configuration constants (interrupt mask register)
        !           236:  */
        !           237: #define WD_I_PRXE      0x01            /* Packet received enable       */
        !           238: #define WD_I_PTXE      0x02            /* Packet transmitted enable    */
        !           239: #define WD_I_RXEE      0x04            /* Receive error enable         */
        !           240: #define WD_I_TXEE      0x08            /* Transmit error enable        */
        !           241: #define WD_I_OVWE      0x10            /* Overwrite warning enable     */
        !           242: #define WD_I_CNTE      0x20            /* Counter overflow enable      */
        !           243: #define WD_I_RDCE      0x40            /* Dma complete enable          */
        !           244: #define WD_I_RES       0x80            /* reserved...                  */
        !           245: #define WD_I_CONFIG     (WD_I_PRXE|WD_I_PTXE|WD_I_RXEE|WD_I_TXEE)

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