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1.1 root 1: /*-
2: * Copyright (c) 1991 The Regents of the University of California.
3: * All rights reserved.
4: *
5: * This code is derived from software contributed to Berkeley by
6: * Tim L. Tucker.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: * 3. All advertising materials mentioning features or use of this software
17: * must display the following acknowledgement:
18: * This product includes software developed by the University of
19: * California, Berkeley and its contributors.
20: * 4. Neither the name of the University nor the names of its contributors
21: * may be used to endorse or promote products derived from this software
22: * without specific prior written permission.
23: *
24: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34: * SUCH DAMAGE.
35: *
36: * @(#)if_wereg.h 7.1 (Berkeley) 5/9/91
37: */
38:
39: /*
40: * Western Digital 8003 ethernet/starlan adapter
41: */
42:
43: /*
44: * Memory Select Register (MSR)
45: */
46: union we_mem_sel {
47: struct memory_decode {
48: u_char msd_addr:6, /* Memory decode bits */
49: msd_enable:1, /* Memory (RAM) enable */
50: msd_reset:1; /* Software reset */
51: } msd_decode;
52: #define ms_addr msd_decode.msd_addr
53: #define ms_enable msd_decode.msd_enable
54: #define ms_reset msd_decode.msd_reset
55: u_char ms_byte; /* entire byte */
56: };
57:
58: /*
1.1.1.3 ! root 59: * LA Address Register (LAAR)
! 60: */
! 61: union we_laar {
! 62: struct lan_addr_reg {
! 63: u_char addr_l19_b:1, /* Address Line 19 for enabling */
! 64: /* 16 bit NIC access to shared RAM */
! 65: unused_b:5, /* unused (or unknown) bits */
! 66: lan_16_en_b:1, /* Enables 16bit shrd RAM for LAN */
! 67: mem_16_en_b:1; /* Enables 16bit shrd RAM for host */
! 68: } laar_decode;
! 69: #define addr_l19 laar_decode.addr_l19_b
! 70: #define lan_16_en laar_decode.lan_16_en_b
! 71: #define mem_16_en laar_decode.mem_16_en_b
! 72: u_char laar_byte; /* entire byte */
! 73: };
! 74:
! 75: /*
1.1 root 76: * receive ring discriptor
77: *
78: * The National Semiconductor DS8390 Network interface controller uses
79: * the following receive ring headers. The way this works is that the
80: * memory on the interface card is chopped up into 256 bytes blocks.
81: * A contiguous portion of those blocks are marked for receive packets
82: * by setting start and end block #'s in the NIC. For each packet that
83: * is put into the receive ring, one of these headers (4 bytes each) is
84: * tacked onto the front.
85: */
86: struct we_ring {
87: struct wer_status { /* received packet status */
88: u_char rs_prx:1, /* packet received intack */
89: rs_crc:1, /* crc error */
90: rs_fae:1, /* frame alignment error */
91: rs_fo:1, /* fifo overrun */
92: rs_mpa:1, /* packet received intack */
93: rs_phy:1, /* packet received intack */
94: rs_dis:1, /* packet received intack */
95: rs_dfr:1; /* packet received intack */
96: } we_rcv_status; /* received packet status */
97: u_char we_next_packet; /* pointer to next packet */
98: u_short we_count; /* bytes in packet (length + 4) */
99: };
100:
101: /*
102: * Command word definition
103: */
104: union we_command {
105: struct command_decode {
106: u_char csd_stp:1, /* STOP! */
107: csd_sta:1, /* START! */
108: csd_txp:1, /* Transmit packet */
109: csd_rd:3, /* Remote DMA command */
110: csd_ps:2; /* Page select */
111: } csd_decode;
112: #define cs_stp csd_decode.csd_stp
113: #define cs_sta csd_decode.csd_sta
114: #define cs_txp csd_decode.csd_txp
115: #define cs_rd csd_decode.csd_rd
116: #define cs_ps csd_decode.csd_ps
117: u_char cs_byte; /* entire command byte */
118: };
119:
120: /*
121: * Interrupt status definition
122: */
123: union we_interrupt {
124: struct interrupt_decode {
125: u_char isd_prx:1, /* Packet received */
126: isd_ptx:1, /* Packet transmitted */
127: isd_rxe:1, /* Receive error */
128: isd_txe:1, /* Transmit error */
129: isd_ovw:1, /* Overwrite warning */
130: isd_cnt:1, /* Counter overflow */
131: isd_rdc:1, /* Remote DMA complete */
132: isd_rst:1; /* Reset status */
133: } isd_decode;
134: #define is_prx isd_decode.isd_prx
135: #define is_ptx isd_decode.isd_ptx
136: #define is_rxe isd_decode.isd_rxe
137: #define is_txe isd_decode.isd_txe
138: #define is_ovw isd_decode.isd_ovw
139: #define is_cnt isd_decode.isd_cnt
140: #define is_rdc isd_decode.isd_rdc
141: #define is_rst isd_decode.isd_rst
142: u_char is_byte; /* entire interrupt byte */
143: };
144:
145: /*
146: * Status word definition (transmit)
147: */
148: union wet_status {
149: struct tstat {
150: u_char tsd_ptx:1, /* Packet transmitted intack */
151: tsd_dfr:1, /* Non deferred transmition */
152: tsd_col:1, /* Transmit Collided */
153: tsd_abt:1, /* Transmit Aborted (coll > 16) */
154: tsd_crs:1, /* Carrier Sense Lost */
155: tsd_fu:1, /* Fifo Underrun */
156: tsd_chd:1, /* CD Heartbeat */
157: tsd_owc:1; /* Out of Window Collision */
158: } tsd_decode;
159: #define ts_ptx tsd_decode.tsd_ptx
160: #define ts_dfr tsd_decode.tsd_dfr
161: #define ts_col tsd_decode.tsd_col
162: #define ts_abt tsd_decode.tsd_abt
163: #define ts_crs tsd_decode.tsd_crs
164: #define ts_fu tsd_decode.tsd_fu
165: #define ts_chd tsd_decode.tsd_chd
166: #define ts_owc tsd_decode.tsd_owc
167: u_char ts_byte; /* entire transmit byte */
168: };
169:
170: /*
171: * General constant definitions
172: */
1.1.1.2 root 173:
174: /* Bits in the REGE register */
175: #define WD_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */
176: #define WD_LARGERAM 0x40 /* Large RAM */
177: #define WD_SOFTCONFIG 0x20 /* Soft config */
178: #define WD_REVMASK 0x1e /* Revision mask */
179: #define WD_ETHERNET 0x01 /* Ethernet (vs. Starlan) */
180:
1.1 root 181: #define WD_CHECKSUM 0xFF /* Checksum byte */
182: #define WD_PAGE_SIZE 256 /* Size of RAM pages in bytes */
183: #define WD_TXBUF_SIZE 6 /* Size of TX buffer in pages */
184: #define WD_ROM_OFFSET 8 /* i/o base offset to ROM */
185: #define WD_IO_PORTS 32 /* # of i/o addresses used */
186: #define WD_NIC_OFFSET 16 /* i/o base offset to NIC */
187:
188: /*
189: * Page register offset values
190: */
191: #define WD_P0_COMMAND 0x00 /* Command register */
192: #define WD_P0_PSTART 0x01 /* Page Start register */
193: #define WD_P0_PSTOP 0x02 /* Page Stop register */
194: #define WD_P0_BNRY 0x03 /* Boundary Pointer */
195: #define WD_P0_TSR 0x04 /* Transmit Status (read-only) */
196: #define WD_P0_TPSR WD_P0_TSR /* Transmit Page (write-only) */
197: #define WD_P0_TBCR0 0x05 /* Transmit Byte count, low WO */
198: #define WD_P0_TBCR1 0x06 /* Transmit Byte count, high WO */
199: #define WD_P0_ISR 0x07 /* Interrupt status register */
200: #define WD_P0_RBCR0 0x0A /* Remote byte count low WO */
201: #define WD_P0_RBCR1 0x0B /* Remote byte count high WO */
202: #define WD_P0_RSR 0x0C /* Receive status RO */
203: #define WD_P0_RCR WD_P0_RSR /* Receive configuration WO */
204: #define WD_P0_TCR 0x0D /* Transmit configuration WO */
205: #define WD_P0_DCR 0x0E /* Data configuration WO */
206: #define WD_P0_IMR 0x0F /* Interrupt masks WO */
207: #define WD_P1_COMMAND 0x00 /* Command register */
208: #define WD_P1_PAR0 0x01 /* Physical address register 0 */
209: #define WD_P1_PAR1 0x02 /* Physical address register 1 */
210: #define WD_P1_PAR2 0x03 /* Physical address register 2 */
211: #define WD_P1_PAR3 0x04 /* Physical address register 3 */
212: #define WD_P1_PAR4 0x05 /* Physical address register 4 */
213: #define WD_P1_PAR5 0x06 /* Physical address register 5 */
214: #define WD_P1_CURR 0x07 /* Current page (receive unit) */
215: #define WD_P1_MAR0 0x08 /* Multicast address register 0 */
216:
217: /*
218: * Configuration constants (receive unit)
219: */
220: #define WD_R_SEP 0x01 /* Save error packets */
221: #define WD_R_AR 0x02 /* Accept Runt packets */
222: #define WD_R_AB 0x04 /* Accept Broadcast packets */
223: #define WD_R_AM 0x08 /* Accept Multicast packets */
224: #define WD_R_PRO 0x10 /* Promiscuous physical */
225: #define WD_R_MON 0x20 /* Monitor mode */
226: #define WD_R_RES1 0x40 /* reserved... */
227: #define WD_R_RES2 0x80 /* reserved... */
228: #define WD_R_CONFIG (WD_R_AB)
229:
230: /*
231: * Configuration constants (transmit unit)
232: */
233: #define WD_T_CRC 0x01 /* Inhibit CRC */
234: #define WD_T_LB0 0x02 /* Encoded Loopback Control */
235: #define WD_T_LB1 0x04 /* Encoded Loopback Control */
236: #define WD_T_ATD 0x08 /* Auto Transmit Disable */
237: #define WD_T_OFST 0x10 /* Collision Offset Enable */
238: #define WD_T_RES1 0x20 /* reserved... */
239: #define WD_T_RES2 0x40 /* reserved... */
240: #define WD_T_RES3 0x80 /* reserved... */
241: #define WD_T_CONFIG (0)
242:
243: /*
244: * Configuration constants (data unit)
245: */
246: #define WD_D_WTS 0x01 /* Word Transfer Select */
247: #define WD_D_BOS 0x02 /* Byte Order Select */
248: #define WD_D_LAS 0x04 /* Long Address Select */
249: #define WD_D_BMS 0x08 /* Burst Mode Select */
250: #define WD_D_AR 0x10 /* Autoinitialize Remote */
251: #define WD_D_FT0 0x20 /* Fifo Threshold Select */
252: #define WD_D_FT1 0x40 /* Fifo Threshold Select */
253: #define WD_D_RES 0x80 /* reserved... */
254: #define WD_D_CONFIG (WD_D_FT1|WD_D_BMS)
1.1.1.3 ! root 255: #define WD_D_CONFIG16 (WD_D_FT1|WD_D_BMS|WD_D_LAS|WD_D_WTS)
1.1 root 256:
257: /*
258: * Configuration constants (interrupt mask register)
259: */
260: #define WD_I_PRXE 0x01 /* Packet received enable */
261: #define WD_I_PTXE 0x02 /* Packet transmitted enable */
262: #define WD_I_RXEE 0x04 /* Receive error enable */
263: #define WD_I_TXEE 0x08 /* Transmit error enable */
264: #define WD_I_OVWE 0x10 /* Overwrite warning enable */
265: #define WD_I_CNTE 0x20 /* Counter overflow enable */
266: #define WD_I_RDCE 0x40 /* Dma complete enable */
267: #define WD_I_RES 0x80 /* reserved... */
268: #define WD_I_CONFIG (WD_I_PRXE|WD_I_PTXE|WD_I_RXEE|WD_I_TXEE)
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