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1.1 root 1: /*-
2: * Copyright (c) 1991 The Regents of the University of California.
3: * All rights reserved.
4: *
5: * This code is derived from software contributed to Berkeley by
6: * William Jolitz.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: * 3. All advertising materials mentioning features or use of this software
17: * must display the following acknowledgement:
18: * This product includes software developed by the University of
19: * California, Berkeley and its contributors.
20: * 4. Neither the name of the University nor the names of its contributors
21: * may be used to endorse or promote products derived from this software
22: * without specific prior written permission.
23: *
24: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34: * SUCH DAMAGE.
35: *
36: * @(#)isa.c 7.2 (Berkeley) 5/13/91
37: */
1.1.1.4 ! root 38: static char rcsid[] = "$Header: /cvsroot/src/sys/arch/i386/isa/Attic/isa.c,v 1.5 1993/04/09 16:24:26 cgd Exp $";
1.1 root 39:
40: /*
41: * code to manage AT bus
1.1.1.4 ! root 42: *
! 43: * 92/08/18 Frank P. MacLachlan ([email protected]):
! 44: * Fixed uninitialized variable problem and added code to deal
! 45: * with DMA page boundaries in isa_dmarangecheck(). Fixed word
! 46: * mode DMA count compution and reorganized DMA setup code in
! 47: * isa_dmastart()
1.1 root 48: */
49:
50: #include "param.h"
51: #include "systm.h"
52: #include "conf.h"
53: #include "file.h"
54: #include "buf.h"
55: #include "uio.h"
56: #include "syslog.h"
1.1.1.3 root 57: #include "malloc.h"
58: #include "rlist.h"
1.1 root 59: #include "machine/segments.h"
1.1.1.3 root 60: #include "vm/vm.h"
1.1 root 61: #include "i386/isa/isa_device.h"
1.1.1.3 root 62: #include "i386/isa/isa.h"
1.1 root 63: #include "i386/isa/icu.h"
1.1.1.3 root 64: #include "i386/isa/ic/i8237.h"
65: #include "i386/isa/ic/i8042.h"
1.1 root 66:
1.1.1.4 ! root 67: /*
! 68: ** Register definitions for DMA controller 1 (channels 0..3):
! 69: */
! 70: #define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */
! 71: #define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */
! 72: #define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */
! 73: #define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */
! 74:
! 75: /*
! 76: ** Register definitions for DMA controller 2 (channels 4..7):
! 77: */
! 78: #define DMA2_CHN(c) (IO_DMA1 + 2*(2*(c))) /* addr reg for channel c */
! 79: #define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */
! 80: #define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */
! 81: #define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */
! 82:
1.1.1.3 root 83: int config_isadev(struct isa_device *, u_short *);
84: #ifdef notyet
85: struct rlist *isa_iomem;
86:
87: /*
88: * Configure all ISA devices
89: */
90: isa_configure() {
91: struct isa_device *dvp;
92: struct isa_driver *dp;
93:
94: splhigh();
95: INTREN(IRQ_SLAVE);
96: /*rlist_free(&isa_iomem, 0xa0000, 0xfffff);*/
97: for (dvp = isa_devtab_tty; dvp; dvp++)
98: (void) config_isadev(dvp, &ttymask);
99: for (dvp = isa_devtab_bio; dvp; dvp++)
100: (void) config_isadev(dvp, &biomask);
101: for (dvp = isa_devtab_net; dvp; dvp++)
102: (void) config_isadev(dvp, &netmask);
103: for (dvp = isa_devtab_null; dvp; dvp++)
104: (void) config_isadev(dvp, 0);
105: #include "sl.h"
106: #if NSL > 0
107: netmask |= ttymask;
108: ttymask |= netmask;
109: #endif
110: /* printf("biomask %x ttymask %x netmask %x\n", biomask, ttymask, netmask); */
111: splnone();
112: }
113:
114: /*
115: * Configure an ISA device.
116: */
117: config_isadev(isdp, mp)
118: struct isa_device *isdp;
119: u_short *mp;
120: {
121: struct isa_driver *dp;
122: static short drqseen, irqseen;
123:
124: if (dp = isdp->id_driver) {
125: /* if a device with i/o memory, convert to virtual address */
126: if (isdp->id_maddr) {
127: extern unsigned int atdevbase;
128:
129: isdp->id_maddr -= IOM_BEGIN;
130: isdp->id_maddr += atdevbase;
131: }
132: isdp->id_alive = (*dp->probe)(isdp);
133: if (isdp->id_alive) {
134:
135: printf("%s%d at port 0x%x ", dp->name,
136: isdp->id_unit, isdp->id_iobase);
137:
138: /* check for conflicts */
139: if (irqseen & isdp->id_irq) {
140: printf("INTERRUPT CONFLICT - irq%d\n",
141: ffs(isdp->id_irq) - 1);
142: return (0);
143: }
144: if (isdp->id_drq != -1
145: && (drqseen & (1<<isdp->id_drq))) {
146: printf("DMA CONFLICT - drq%d\n", isdp->id_drq);
147: return (0);
148: }
149: /* NEED TO CHECK IOMEM CONFLICT HERE */
150:
151: /* allocate and wire in device */
152: if(isdp->id_irq) {
153: int intrno;
154:
155: intrno = ffs(isdp->id_irq)-1;
156: printf("irq %d ", intrno);
157: INTREN(isdp->id_irq);
158: if(mp)INTRMASK(*mp,isdp->id_irq);
159: setidt(NRSVIDT + intrno, isdp->id_intr,
160: SDT_SYS386IGT, SEL_KPL);
161: irqseen |= isdp->id_irq;
162: }
163: if (isdp->id_drq != -1) {
164: printf("drq %d ", isdp->id_drq);
165: drqseen |= 1 << isdp->id_drq;
166: }
167:
168: (*dp->attach)(isdp);
169:
170: printf("on isa\n");
171: }
172: return (1);
173: } else return(0);
174: }
1.1.1.4 ! root 175: #else /* notyet */
1.1 root 176: /*
177: * Configure all ISA devices
178: */
179: isa_configure() {
180: struct isa_device *dvp;
181: struct isa_driver *dp;
182:
183: splhigh();
184: INTREN(IRQ_SLAVE);
185: for (dvp = isa_devtab_tty; config_isadev(dvp,&ttymask); dvp++);
1.1.1.2 root 186: for (dvp = isa_devtab_bio; config_isadev(dvp,&biomask); dvp++);
1.1 root 187: for (dvp = isa_devtab_net; config_isadev(dvp,&netmask); dvp++);
188: for (dvp = isa_devtab_null; config_isadev(dvp,0); dvp++);
189: #include "sl.h"
190: #if NSL > 0
191: netmask |= ttymask;
192: ttymask |= netmask;
193: #endif
194: /* biomask |= ttymask ; can some tty devices use buffers? */
1.1.1.3 root 195: /* printf("biomask %x ttymask %x netmask %x\n", biomask, ttymask, netmask); */
1.1 root 196: splnone();
197: }
198:
199: /*
200: * Configure an ISA device.
201: */
202: config_isadev(isdp, mp)
203: struct isa_device *isdp;
1.1.1.3 root 204: u_short *mp;
1.1 root 205: {
206: struct isa_driver *dp;
207:
208: if (dp = isdp->id_driver) {
209: if (isdp->id_maddr) {
1.1.1.3 root 210: extern u_int atdevbase;
1.1 root 211:
212: isdp->id_maddr -= 0xa0000;
213: isdp->id_maddr += atdevbase;
214: }
215: isdp->id_alive = (*dp->probe)(isdp);
216: if (isdp->id_alive) {
217: printf("%s%d", dp->name, isdp->id_unit);
1.1.1.4 ! root 218: printf(" at 0x%x", isdp->id_iobase);
! 219: if ((isdp->id_iobase + isdp->id_alive - 1) !=
! 220: isdp->id_iobase)
! 221: printf("-0x%x",
! 222: isdp->id_iobase + isdp->id_alive - 1);
! 223: printf(" ");
! 224: if(isdp->id_irq)
! 225: printf("irq %d ", ffs(isdp->id_irq)-1);
! 226: if (isdp->id_drq != -1)
! 227: printf("drq %d ", isdp->id_drq);
! 228: if (isdp->id_maddr != 0)
! 229: printf("maddr 0x%x ", kvtop(isdp->id_maddr));
! 230: if (isdp->id_msize != 0)
! 231: printf("msize %d ", isdp->id_msize);
! 232: if (isdp->id_flags != 0)
! 233: printf("flags 0x%x ", isdp->id_flags);
! 234: printf("on isa\n");
! 235:
1.1 root 236: (*dp->attach)(isdp);
237: if(isdp->id_irq) {
238: int intrno;
239:
240: intrno = ffs(isdp->id_irq)-1;
241: INTREN(isdp->id_irq);
1.1.1.4 ! root 242: if(mp)
! 243: INTRMASK(*mp,isdp->id_irq);
1.1 root 244: setidt(ICU_OFFSET+intrno, isdp->id_intr,
245: SDT_SYS386IGT, SEL_KPL);
246: }
247: }
248: return (1);
249: } else return(0);
250: }
1.1.1.4 ! root 251: #endif /* (!) notyet */
1.1 root 252:
253: #define IDTVEC(name) __CONCAT(X,name)
1.1.1.3 root 254: /* default interrupt vector table entries */
1.1 root 255: extern IDTVEC(intr0), IDTVEC(intr1), IDTVEC(intr2), IDTVEC(intr3),
256: IDTVEC(intr4), IDTVEC(intr5), IDTVEC(intr6), IDTVEC(intr7),
257: IDTVEC(intr8), IDTVEC(intr9), IDTVEC(intr10), IDTVEC(intr11),
258: IDTVEC(intr12), IDTVEC(intr13), IDTVEC(intr14), IDTVEC(intr15);
1.1.1.3 root 259:
260: static *defvec[16] = {
261: &IDTVEC(intr0), &IDTVEC(intr1), &IDTVEC(intr2), &IDTVEC(intr3),
262: &IDTVEC(intr4), &IDTVEC(intr5), &IDTVEC(intr6), &IDTVEC(intr7),
263: &IDTVEC(intr8), &IDTVEC(intr9), &IDTVEC(intr10), &IDTVEC(intr11),
264: &IDTVEC(intr12), &IDTVEC(intr13), &IDTVEC(intr14), &IDTVEC(intr15) };
265:
266: /* out of range default interrupt vector gate entry */
267: extern IDTVEC(intrdefault);
1.1 root 268:
269: /*
270: * Fill in default interrupt table (in case of spuruious interrupt
271: * during configuration of kernel, setup interrupt control unit
272: */
273: isa_defaultirq() {
1.1.1.3 root 274: int i;
1.1 root 275:
1.1.1.3 root 276: /* icu vectors */
277: for (i = NRSVIDT ; i < NRSVIDT+ICU_LEN ; i++)
278: setidt(i, defvec[i], SDT_SYS386IGT, SEL_KPL);
1.1 root 279:
1.1.1.3 root 280: /* out of range vectors */
281: for (i = NRSVIDT; i < NIDT; i++)
282: setidt(i, &IDTVEC(intrdefault), SDT_SYS386IGT, SEL_KPL);
283:
284: /* clear npx intr latch */
1.1 root 285: outb(0xf1,0);
1.1.1.3 root 286:
287: /* initialize 8259's */
288: outb(IO_ICU1, 0x11); /* reset; program device, four bytes */
289: outb(IO_ICU1+1, NRSVIDT); /* starting at this vector index */
290: outb(IO_ICU1+1, 1<<2); /* slave on line 2 */
291: outb(IO_ICU1+1, 1); /* 8086 mode */
292: outb(IO_ICU1+1, 0xff); /* leave interrupts masked */
293: outb(IO_ICU1, 2); /* default to ISR on read */
294:
295: outb(IO_ICU2, 0x11); /* reset; program device, four bytes */
296: outb(IO_ICU2+1, NRSVIDT+8); /* staring at this vector index */
297: outb(IO_ICU2+1,2); /* my slave id is 2 */
298: outb(IO_ICU2+1,1); /* 8086 mode */
299: outb(IO_ICU2+1, 0xff); /* leave interrupts masked */
300: outb(IO_ICU2, 2); /* default to ISR on read */
1.1 root 301: }
302:
1.1.1.3 root 303: /* region of physical memory known to be contiguous */
304: vm_offset_t isaphysmem;
305: static caddr_t dma_bounce[8]; /* XXX */
306: static char bounced[8]; /* XXX */
307: #define MAXDMASZ 512 /* XXX */
308:
309: /* high byte of address is stored in this port for i-th dma channel */
310: static short dmapageport[8] =
311: { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a };
1.1 root 312:
1.1.1.3 root 313: /*
314: * isa_dmacascade(): program 8237 DMA controller channel to accept
315: * external dma control by a board.
316: */
317: void isa_dmacascade(unsigned chan)
1.1.1.4 ! root 318: {
1.1.1.3 root 319: if (chan > 7)
320: panic("isa_dmacascade: impossible request");
1.1 root 321:
1.1.1.3 root 322: /* set dma channel mode, and set dma channel mode */
1.1.1.4 ! root 323: if ((chan & 4) == 0) {
! 324: outb(DMA1_MODE, DMA37MD_CASCADE | chan);
! 325: outb(DMA1_SMSK, chan);
! 326: } else {
! 327: outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3));
! 328: outb(DMA2_SMSK, chan & 3);
! 329: }
1.1.1.3 root 330: }
1.1 root 331:
1.1.1.3 root 332: /*
333: * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment
334: * problems by using a bounce buffer.
335: */
336: void isa_dmastart(int flags, caddr_t addr, unsigned nbytes, unsigned chan)
337: { vm_offset_t phys;
1.1.1.4 ! root 338: int waport;
1.1.1.3 root 339: caddr_t newaddr;
340:
1.1.1.4 ! root 341: if ( chan > 7
! 342: || (chan < 4 && nbytes > (1<<16))
! 343: || (chan >= 4 && (nbytes > (1<<17) || (u_int)addr & 1)))
1.1.1.3 root 344: panic("isa_dmastart: impossible request");
345:
1.1.1.4 ! root 346: if (isa_dmarangecheck(addr, nbytes, chan)) {
1.1 root 347: if (dma_bounce[chan] == 0)
1.1.1.3 root 348: dma_bounce[chan] =
349: /*(caddr_t)malloc(MAXDMASZ, M_TEMP, M_WAITOK);*/
350: (caddr_t) isaphysmem + NBPG*chan;
351: bounced[chan] = 1;
352: newaddr = dma_bounce[chan];
353: *(int *) newaddr = 0; /* XXX */
354:
355: /* copy bounce buffer on write */
356: if (!(flags & B_READ))
357: bcopy(addr, newaddr, nbytes);
358: addr = newaddr;
1.1 root 359: }
360:
1.1.1.3 root 361: /* translate to physical */
362: phys = pmap_extract(pmap_kernel(), (vm_offset_t)addr);
1.1 root 363:
1.1.1.3 root 364: if ((chan & 4) == 0) {
1.1.1.4 ! root 365: /*
! 366: * Program one of DMA channels 0..3. These are
! 367: * byte mode channels.
! 368: */
! 369: /* set dma channel mode, and reset address ff */
! 370: if (flags & B_READ)
! 371: outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan);
! 372: else
! 373: outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan);
! 374: outb(DMA1_FFC, 0);
! 375:
! 376: /* send start address */
! 377: waport = DMA1_CHN(chan);
1.1.1.3 root 378: outb(waport, phys);
379: outb(waport, phys>>8);
1.1.1.4 ! root 380: outb(dmapageport[chan], phys>>16);
1.1.1.3 root 381:
1.1.1.4 ! root 382: /* send count */
1.1.1.3 root 383: outb(waport + 1, --nbytes);
384: outb(waport + 1, nbytes>>8);
1.1.1.4 ! root 385:
! 386: /* unmask channel */
! 387: outb(DMA1_SMSK, chan);
1.1.1.3 root 388: } else {
1.1.1.4 ! root 389: /*
! 390: * Program one of DMA channels 4..7. These are
! 391: * word mode channels.
! 392: */
! 393: /* set dma channel mode, and reset address ff */
! 394: if (flags & B_READ)
! 395: outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3));
! 396: else
! 397: outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3));
! 398: outb(DMA2_FFC, 0);
! 399:
! 400: /* send start address */
! 401: waport = DMA2_CHN(chan - 4);
! 402: outb(waport, phys>>1);
! 403: outb(waport, phys>>9);
! 404: outb(dmapageport[chan], phys>>16);
! 405:
! 406: /* send count */
! 407: nbytes >>= 1;
1.1.1.3 root 408: outb(waport + 2, --nbytes);
409: outb(waport + 2, nbytes>>8);
410:
1.1.1.4 ! root 411: /* unmask channel */
! 412: outb(DMA2_SMSK, chan & 3);
! 413: }
1.1.1.3 root 414: }
415:
416: void isa_dmadone(int flags, caddr_t addr, int nbytes, int chan)
417: {
418:
419: /* copy bounce buffer on read */
420: /*if ((flags & (B_PHYS|B_READ)) == (B_PHYS|B_READ))*/
421: if (bounced[chan]) {
422: bcopy(dma_bounce[chan], addr, nbytes);
423: bounced[chan] = 0;
424: }
425: }
426:
427: /*
428: * Check for problems with the address range of a DMA transfer
1.1.1.4 ! root 429: * (non-contiguous physical pages, outside of bus address space,
! 430: * crossing DMA page boundaries).
1.1.1.3 root 431: * Return true if special handling needed.
432: */
433:
1.1.1.4 ! root 434: isa_dmarangecheck(caddr_t va, unsigned length, unsigned chan) {
! 435: vm_offset_t phys, priorpage = 0, endva;
! 436: u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1);
1.1.1.3 root 437:
438: endva = (vm_offset_t)round_page(va + length);
439: for (; va < (caddr_t) endva ; va += NBPG) {
440: phys = trunc_page(pmap_extract(pmap_kernel(), (vm_offset_t)va));
441: #define ISARAM_END RAM_END
442: if (phys == 0)
443: panic("isa_dmacheck: no physical page present");
444: if (phys > ISARAM_END)
445: return (1);
1.1.1.4 ! root 446: if (priorpage) {
! 447: if (priorpage + NBPG != phys)
! 448: return (1);
! 449: /* check if crossing a DMA page boundary */
! 450: if (((u_int)priorpage ^ (u_int)phys) & dma_pgmsk)
! 451: return (1);
! 452: }
1.1.1.3 root 453: priorpage = phys;
454: }
455: return (0);
456: }
457:
458: /* head of queue waiting for physmem to become available */
459: struct buf isa_physmemq;
460:
461: /* blocked waiting for resource to become free for exclusive use */
462: static isaphysmemflag;
463: /* if waited for and call requested when free (B_CALL) */
464: static void (*isaphysmemunblock)(); /* needs to be a list */
465:
466: /*
467: * Allocate contiguous physical memory for transfer, returning
468: * a *virtual* address to region. May block waiting for resource.
469: * (assumed to be called at splbio())
470: */
471: caddr_t
472: isa_allocphysmem(caddr_t va, unsigned length, void (*func)()) {
473:
474: isaphysmemunblock = func;
475: while (isaphysmemflag & B_BUSY) {
476: isaphysmemflag |= B_WANTED;
477: sleep(&isaphysmemflag, PRIBIO);
478: }
479: isaphysmemflag |= B_BUSY;
480:
481: return((caddr_t)isaphysmem);
1.1 root 482: }
483:
484: /*
1.1.1.3 root 485: * Free contiguous physical memory used for transfer.
486: * (assumed to be called at splbio())
487: */
488: void
489: isa_freephysmem(caddr_t va, unsigned length) {
490:
491: isaphysmemflag &= ~B_BUSY;
492: if (isaphysmemflag & B_WANTED) {
493: isaphysmemflag &= B_WANTED;
494: wakeup(&isaphysmemflag);
495: if (isaphysmemunblock)
496: (*isaphysmemunblock)();
497: }
498: }
499:
500: /*
1.1 root 501: * Handle a NMI, possibly a machine check.
502: * return true to panic system, false to ignore.
503: */
504: isa_nmi(cd) {
505:
506: log(LOG_CRIT, "\nNMI port 61 %x, port 70 %x\n", inb(0x61), inb(0x70));
507: return(0);
508: }
509:
510: /*
511: * Caught a stray interrupt, notify
512: */
513: isa_strayintr(d) {
514:
1.1.1.3 root 515: /* DON'T BOTHER FOR NOW! */
1.1 root 516: /* for some reason, we get bursts of intr #7, even if not enabled! */
1.1.1.4 ! root 517: /*
! 518: * Well the reason you got bursts of intr #7 is because someone
! 519: * raised an interrupt line and dropped it before the 8259 could
! 520: * prioritize it. This is documented in the intel data book. This
! 521: * means you have BAD hardware! I have changed this so that only
! 522: * the first 10 get logged, then it quits logging them, and puts
! 523: * out a special message. rgrimes 3/25/1993
! 524: */
! 525: extern u_long isa_stray_intrcnt;
! 526:
! 527: isa_stray_intrcnt++;
! 528: if (isa_stray_intrcnt <= 10)
! 529: log(LOG_ERR,"ISA strayintr %x\n", d);
! 530: if (isa_stray_intrcnt == 10)
! 531: log(LOG_CRIT,"Too many ISA strayintr not logging any more\n");
1.1.1.3 root 532: }
533:
534: /*
535: * Wait "n" microseconds. Relies on timer 0 to have 1Mhz clock, regardless
536: * of processor board speed. Note: timer had better have been programmed
537: * before this is first used!
538: */
539: DELAY(n) {
540: int tick = getit(0,0) & 1;
541:
542: while (n--) {
543: /* wait approximately 1 micro second */
544: while (tick == getit(0,0) & 1) ;
545:
546: tick = getit(0,0) & 1;
547: }
548: }
549:
550: getit(unit, timer) {
551: int port = (unit ? IO_TIMER2 : IO_TIMER1) + timer, val;
552:
553: val = inb(port);
554: val = (inb(port) << 8) + val;
555: return (val);
556: }
557:
558: extern int hz;
559:
560: static beeping;
561: static
562: sysbeepstop(f)
563: {
564: /* disable counter 2 */
565: outb(0x61, inb(0x61) & 0xFC);
566: if (f)
567: timeout(sysbeepstop, 0, f);
568: else
569: beeping = 0;
570: }
571:
572: void sysbeep(int pitch, int period)
573: {
574:
575: outb(0x61, inb(0x61) | 3); /* enable counter 2 */
576: outb(0x43, 0xb6); /* set command for counter 2, 2 byte write */
577:
578: outb(0x42, pitch);
579: outb(0x42, (pitch>>8));
580:
581: if (!beeping) {
582: beeping = period;
583: timeout(sysbeepstop, period/2, period);
584: }
585: }
586:
587: /*
588: * Pass command to keyboard controller (8042)
589: */
590: unsigned kbc_8042cmd(val) {
591:
592: while (inb(KBSTATP)&KBS_IBF);
593: if (val) outb(KBCMDP, val);
594: while (inb(KBSTATP)&KBS_IBF);
595: return (inb(KBDATAP));
1.1 root 596: }
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