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1.1 root 1: /*-
2: * Copyright (c) 1990 The Regents of the University of California.
3: * All rights reserved.
4: *
5: * This code is derived from software contributed to Berkeley by
6: * William Jolitz.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: * 3. All advertising materials mentioning features or use of this software
17: * must display the following acknowledgement:
18: * This product includes software developed by the University of
19: * California, Berkeley and its contributors.
20: * 4. Neither the name of the University nor the names of its contributors
21: * may be used to endorse or promote products derived from this software
22: * without specific prior written permission.
23: *
24: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34: * SUCH DAMAGE.
35: *
36: * @(#)isa.h 5.7 (Berkeley) 5/9/91
37: */
38:
39: /*
40: * ISA Bus conventions
41: */
42:
43: #ifndef LOCORE
44: unsigned char inb(), rtcin();
45: void outb();
1.1.1.2 root 46: extern unsigned int atdevbase; /* offset in virtual memory of ISA io mem */
47: void sysbeep(int,int);
48: unsigned kbd_8042cmd(int);
1.1 root 49: #endif
50:
51:
52: /*
53: * Input / Output Port Assignments
54: */
55:
56: #ifndef IO_BEGIN
57: #define IO_ISABEGIN 0x000 /* 0x000 - Beginning of I/O Registers */
58:
59: /* CPU Board */
60: #define IO_DMA1 0x000 /* 8237A DMA Controller #1 */
61: #define IO_ICU1 0x020 /* 8259A Interrupt Controller #1 */
62: #define IO_TIMER1 0x040 /* 8252 Timer #1 */
63: #define IO_TIMER2 0x048 /* 8252 Timer #2 */
64: #define IO_KBD 0x060 /* 8042 Keyboard */
65: #define IO_RTC 0x070 /* RTC */
66: #define IO_NMI IO_RTC /* NMI Control */
67: #define IO_DMAPG 0x080 /* DMA Page Registers */
68: #define IO_ICU2 0x0A0 /* 8259A Interrupt Controller #2 */
69: #define IO_DMA2 0x0C0 /* 8237A DMA Controller #2 */
70: #define IO_NPX 0x0F0 /* Numeric Coprocessor */
71:
72: /* Cards */
73: /* 0x100 - 0x16F Open */
74:
75: #define IO_WD2 0x170 /* Secondary Fixed Disk Controller */
76:
77: /* 0x178 - 0x1EF Open */
78:
79: #define IO_WD1 0x1f0 /* Primary Fixed Disk Controller */
80: #define IO_GAME 0x200 /* Game Controller */
81:
82: /* 0x208 - 0x277 Open */
83:
84: #define IO_LPT2 0x278 /* Parallel Port #2 */
85:
86: /* 0x280 - 0x2F7 Open */
87:
88: #define IO_COM2 0x2f8 /* COM2 i/o address */
89:
1.1.1.3 ! root 90: /* 0x300 - 0x32F Open */
! 91:
! 92: #define IO_BT0 0x330 /* bustek 742a default addr. */
! 93: #define IO_AHA0 0x330 /* adaptec 1542 default addr. */
! 94: #define IO_UHA0 0x330 /* ultrastore 14f default addr. */
! 95: #define IO_BT1 0x334 /* bustek 742a default addr. */
! 96: #define IO_AHA1 0x334 /* adaptec 1542 default addr. */
! 97:
! 98: /* 0x338 - 0x34F Open */
! 99:
! 100: #define IO_WDS 0x350 /* WD7000 scsi */
! 101:
! 102: /* 0x354 - 0x36F Open */
1.1 root 103:
104: #define IO_FD2 0x370 /* secondary base i/o address */
105: #define IO_LPT1 0x378 /* Parallel Port #1 */
106:
107: /* 0x380 - 0x3AF Open */
108:
109: #define IO_MDA 0x3B0 /* Monochome Adapter */
110: #define IO_LPT3 0x3BC /* Monochome Adapter Printer Port */
111: #define IO_VGA 0x3C0 /* E/VGA Ports */
112: #define IO_CGA 0x3D0 /* CGA Ports */
113:
114: /* 0x3E0 - 0x3EF Open */
115:
116: #define IO_FD1 0x3f0 /* primary base i/o address */
117: #define IO_COM1 0x3f8 /* COM1 i/o address */
118:
119: #define IO_ISAEND 0x3FF /* - 0x3FF End of I/O Registers */
120: #endif IO_ISABEGIN
121:
122: /*
123: * Input / Output Memory Physical Addresses
124: */
125:
126: #ifndef IOM_BEGIN
127: #define IOM_BEGIN 0x0a0000 /* Start of I/O Memory "hole" */
128: #define IOM_END 0x100000 /* End of I/O Memory "hole" */
129: #define IOM_SIZE (IOM_END - IOM_BEGIN)
130: #endif IOM_BEGIN
131:
132: /*
133: * RAM Physical Address Space (ignoring the above mentioned "hole")
134: */
135:
136: #ifndef RAM_BEGIN
137: #define RAM_BEGIN 0x0000000 /* Start of RAM Memory */
138: #define RAM_END 0x1000000 /* End of RAM Memory */
139: #define RAM_SIZE (RAM_END - RAM_BEGIN)
140: #endif RAM_BEGIN
141:
142: /*
143: * Oddball Physical Memory Addresses
144: */
145: #ifndef COMPAQ_RAMRELOC
146: #define COMPAQ_RAMRELOC 0x80c00000 /* Compaq RAM relocation/diag */
147: #define COMPAQ_RAMSETUP 0x80c00002 /* Compaq RAM setup */
148: #define WEITEK_FPU 0xC0000000 /* WTL 2167 */
149: #define CYRIX_EMC 0xC0000000 /* Cyrix EMC */
150: #endif COMPAQ_RAMRELOC
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