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Annotation of Net2/arch/i386/netboot/dp8390.h, revision 1.1

1.1     ! root        1: /* netboot
        !             2:  *
        !             3:  * dp8390.h,v
        !             4:  * Revision 1.1  1993/07/08  16:03:56  brezak
        !             5:  * Diskless boot prom code from Jim McKim ([email protected])
        !             6:  *
        !             7:  * Revision 1.1.1.1  1993/05/28  11:41:07  mckim
        !             8:  * Initial version.
        !             9:  *
        !            10:  *
        !            11:  * source in this file came from
        !            12:  * the Mach ethernet boot written by Leendert van Doorn.
        !            13:  *
        !            14:  * National Semiconductor DP8390 Network Interface Controller
        !            15:  */
        !            16: 
        !            17: /* page 0: for reading */
        !            18: #define DP_CR          0x00    /* read side of command register */
        !            19: #define DP_CLDA0       0x01    /* current local DMA address 0 */
        !            20: #define DP_CLDA1       0x02    /* current local DMA address 1 */
        !            21: #define DP_BNRY                0x03    /* boundary pointer */
        !            22: #define DP_TSR         0x04    /* transmit status register */
        !            23: #define DP_NCR         0x05    /* number of collisions register */
        !            24: #define DP_FIFO                0x06    /* FIFO */
        !            25: #define DP_ISR         0x07    /* interrupt status register */
        !            26: #define DP_CRDA0       0x08    /* current remote DMA address 0 */
        !            27: #define DP_CRDA1       0x09    /* current remote DMA address 1 */
        !            28: #define DP_RSR         0x0C    /* receive status register */
        !            29: #define DP_CNTR0       0x0D    /* tally counter 0 */
        !            30: #define DP_CNTR1       0x0E    /* tally counter 1 */
        !            31: #define DP_CNTR2       0x0F    /* tally counter 2 */
        !            32: 
        !            33: /* page 0: for writing */
        !            34: #define DP_CR          0x00    /* write side of command register */
        !            35: #define DP_PSTART      0x01    /* page start register */
        !            36: #define DP_PSTOP       0x02    /* page stop register */
        !            37: #define DP_BNRY                0x03    /* boundary pointer */
        !            38: #define DP_TPSR                0x04    /* transmit page start register */
        !            39: #define DP_TBCR0       0x05    /* transmit byte count register 0 */
        !            40: #define DP_TBCR1       0x06    /* transmit byte count register 1 */
        !            41: #define DP_ISR         0x07    /* interrupt status register */
        !            42: #define DP_RSAR0       0x08    /* remote start address register 0 */
        !            43: #define DP_RSAR1       0x09    /* remote start address register 1 */
        !            44: #define DP_RBCR0       0x0A    /* remote byte count register 0 */
        !            45: #define DP_RBCR1       0x0B    /* remote byte count register 1 */
        !            46: #define DP_RCR         0x0C    /* receive configuration register */
        !            47: #define DP_TCR         0x0D    /* transmit configuration register */
        !            48: #define DP_DCR         0x0E    /* data configuration register */
        !            49: #define DP_IMR         0x0F    /* interrupt mask register */
        !            50: 
        !            51: /* page 1: read/write */
        !            52: #define DP_CR          0x00    /* command register */
        !            53: #define DP_PAR0                0x01    /* physical address register 0 */
        !            54: #define DP_PAR1                0x02    /* physical address register 1 */
        !            55: #define DP_PAR2                0x03    /* physical address register 2 */
        !            56: #define DP_PAR3                0x04    /* physical address register 3 */
        !            57: #define DP_PAR4                0x05    /* physical address register 4 */
        !            58: #define DP_PAR5                0x06    /* physical address register 5 */
        !            59: #define DP_CURR                0x07    /* current page register */
        !            60: #define DP_MAR0                0x08    /* multicast address register 0 */
        !            61: #define DP_MAR1                0x09    /* multicast address register 1 */
        !            62: #define DP_MAR2                0x0A    /* multicast address register 2 */
        !            63: #define DP_MAR3                0x0B    /* multicast address register 3 */
        !            64: #define DP_MAR4                0x0C    /* multicast address register 4 */
        !            65: #define DP_MAR5                0x0D    /* multicast address register 5 */
        !            66: #define DP_MAR6                0x0E    /* multicast address register 6 */
        !            67: #define DP_MAR7                0x0F    /* multicast address register 7 */
        !            68: 
        !            69: /* bits in command register */
        !            70: #define CR_STP         0x01            /* stop: software reset */
        !            71: #define CR_STA         0x02            /* start: activate NIC */
        !            72: #define CR_TXP         0x04            /* transmit packet */
        !            73: #define CR_DMA         0x38            /* mask for DMA control */
        !            74: #   define CR_DM_NOP       0x00        /* DMA: no operation */
        !            75: #   define CR_DM_RR        0x08        /* DMA: remote read */
        !            76: #   define CR_DM_RW        0x10        /* DMA: remote write */
        !            77: #   define CR_DM_SP        0x18        /* DMA: send packet */
        !            78: #   define CR_DM_ABORT     0x20        /* DMA: abort remote DMA operation */
        !            79: #define CR_PS          0xC0            /* mask for page select */
        !            80: #   define CR_PS_P0        0x00        /* register page 0 */
        !            81: #   define CR_PS_P1        0x40        /* register page 1 */
        !            82: #   define CR_PS_T0        0x80        /* test mode register map */
        !            83: #   define CR_SP_T1        0xC0        /* test mode register map */
        !            84: 
        !            85: /* bits in interrupt status register */
        !            86: #define ISR_PRX                0x01            /* packet received with no errors */
        !            87: #define ISR_PTX                0x02            /* packet transmitted with no errors */
        !            88: #define ISR_RXE                0x04            /* receive error */
        !            89: #define ISR_TXE                0x08            /* transmit error */
        !            90: #define ISR_OVW                0x10            /* overwrite warning */
        !            91: #define ISR_CNT                0x20            /* counter overflow */
        !            92: #define ISR_RDC                0x40            /* remote DMA complete */
        !            93: #define ISR_RST                0x80            /* reset status */
        !            94: 
        !            95: /* bits in interrupt mask register */
        !            96: #define IMR_PRXE       0x01            /* packet received ienable */
        !            97: #define IMR_PTXE       0x02            /* packet transmitted ienable */
        !            98: #define IMR_RXEE       0x04            /* receive error ienable */
        !            99: #define IMR_TXEE       0x08            /* transmit error ienable */
        !           100: #define IMR_OVWE       0x10            /* overwrite warning ienable */
        !           101: #define IMR_CNTE       0x20            /* counter overflow ienable */
        !           102: #define IMR_RDCE       0x40            /* DMA complete ienable */
        !           103: 
        !           104: /* bits in data control register */
        !           105: #define DCR_WTS                0x01            /* word transfer select */
        !           106: #   define DCR_BYTEWIDE        0x00            /* WTS: byte wide transfers */
        !           107: #   define DCR_WORDWIDE        0x01            /* WTS: word wide transfers */
        !           108: #define DCR_BOS                0x02            /* byte order select */
        !           109: #   define DCR_LTLENDIAN     0x00      /* BOS: little endian */
        !           110: #   define DCR_BIGENDIAN     0x02      /* BOS: big endian */
        !           111: #define DCR_LAS                0x04            /* long address select */
        !           112: #define DCR_BMS                0x08            /* burst mode select */
        !           113: #define DCR_AR         0x10            /* autoinitialize remote */
        !           114: #define DCR_FTS                0x60            /* FIFO threshold select */
        !           115: #   define DCR_2BYTES      0x00        /* 2 bytes */
        !           116: #   define DCR_4BYTES      0x40        /* 4 bytes */
        !           117: #   define DCR_8BYTES      0x20        /* 8 bytes */
        !           118: #   define DCR_12BYTES     0x60        /* 12 bytes */
        !           119: 
        !           120: /* bits in transmit configuration register */
        !           121: #define TCR_CRC                0x01            /* inhibit CRC */
        !           122: #define TCR_ELC                0x06            /* encoded loopback control */
        !           123: #   define TCR_NORMAL      0x00        /* ELC: normal operation */
        !           124: #   define TCR_INTERNAL            0x02        /* ELC: internal loopback */
        !           125: #   define TCR_0EXTERNAL    0x04       /* ELC: external loopback LPBK=0 */
        !           126: #   define TCR_1EXTERNAL    0x06       /* ELC: external loopback LPBK=1 */
        !           127: #define TCR_ATD                0x08            /* auto transmit */
        !           128: #define TCR_OFST       0x10            /* collision offset enable (be nice) */
        !           129: 
        !           130: /* bits in transmit status register */
        !           131: #define TSR_PTX                0x01            /* packet transmitted (without error)*/
        !           132: #define TSR_DFR                0x02            /* transmit deferred */
        !           133: #define TSR_COL                0x04            /* transmit collided */
        !           134: #define TSR_ABT                0x08            /* transmit aborted */
        !           135: #define TSR_CRS                0x10            /* carrier sense lost */
        !           136: #define TSR_FU         0x20            /* fifo underrun */
        !           137: #define TSR_CDH                0x40            /* CD heartbeat */
        !           138: #define TSR_OWC                0x80            /* out of window collision */
        !           139: 
        !           140: /* bits in receive configuration register */
        !           141: #define RCR_SEP                0x01            /* save errored packets */
        !           142: #define RCR_AR         0x02            /* accept runt packets */
        !           143: #define RCR_AB         0x04            /* accept broadcast */
        !           144: #define RCR_AM         0x08            /* accept multicast */
        !           145: #define RCR_PRO                0x10            /* physical promiscuous */
        !           146: #define RCR_MON                0x20            /* monitor mode */
        !           147: 
        !           148: /* bits in receive status register */
        !           149: #define RSR_PRX                0x01            /* packet received intact */
        !           150: #define RSR_CRC                0x02            /* CRC error */
        !           151: #define RSR_FAE                0x04            /* frame alignment error */
        !           152: #define RSR_FO         0x08            /* FIFO overrun */
        !           153: #define RSR_MPA                0x10            /* missed packet */
        !           154: #define RSR_PHY                0x20            /* multicast address match !! */
        !           155: #define RSR_DIS                0x40            /* receiver disabled */
        !           156: 
        !           157: /* dp8390 configuration information */
        !           158: typedef struct {
        !           159:     u_short    dc_reg;                 /* dp8390 base address */
        !           160:     u_long     dc_mem;                 /* base memory */
        !           161:     u_char     dc_tpsr;                /* transmit start page */
        !           162:     u_char     dc_pstart;              /* receive start page */
        !           163:     u_char     dc_pstop;               /* receive end page */
        !           164: } dpconf_t;
        !           165: 
        !           166: 
        !           167: /* dp8390 receive header */
        !           168: typedef struct {
        !           169:     u_char     dh_status;              /* copy of rsr */
        !           170:     u_char     dh_next;                /* pointer to next packet */
        !           171:     u_char     dh_rbcl;                /* receive byte count low */
        !           172:     u_char     dh_rbch;                /* receive byte count high */
        !           173: } dphdr_t;

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