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Annotation of Net2/arch/tahoe/if/if_acereg.h, revision 1.1

1.1     ! root        1: /*-
        !             2:  * Copyright (c) 1991 The Regents of the University of California.
        !             3:  * All rights reserved.
        !             4:  *
        !             5:  * This code is derived from software contributed to Berkeley by
        !             6:  * Computer Consoles Inc.
        !             7:  *
        !             8:  * Redistribution and use in source and binary forms, with or without
        !             9:  * modification, are permitted provided that the following conditions
        !            10:  * are met:
        !            11:  * 1. Redistributions of source code must retain the above copyright
        !            12:  *    notice, this list of conditions and the following disclaimer.
        !            13:  * 2. Redistributions in binary form must reproduce the above copyright
        !            14:  *    notice, this list of conditions and the following disclaimer in the
        !            15:  *    documentation and/or other materials provided with the distribution.
        !            16:  * 3. All advertising materials mentioning features or use of this software
        !            17:  *    must display the following acknowledgement:
        !            18:  *     This product includes software developed by the University of
        !            19:  *     California, Berkeley and its contributors.
        !            20:  * 4. Neither the name of the University nor the names of its contributors
        !            21:  *    may be used to endorse or promote products derived from this software
        !            22:  *    without specific prior written permission.
        !            23:  *
        !            24:  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
        !            25:  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
        !            26:  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
        !            27:  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
        !            28:  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
        !            29:  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
        !            30:  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
        !            31:  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
        !            32:  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
        !            33:  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
        !            34:  * SUCH DAMAGE.
        !            35:  *
        !            36:  *     @(#)if_acereg.h 7.2 (Berkeley) 5/8/91
        !            37:  */
        !            38: 
        !            39: /*
        !            40:  * VERSAbus ACC ethernet controller definitions
        !            41:  */
        !            42: 
        !            43: /*
        !            44:  * Register definitions
        !            45:  */
        !            46: struct acedevice {
        !            47:        short   station[6];             /* station address */
        !            48:        short   bcastena[2];            /* broadcast enable */
        !            49:        short   hash[8];                /* multicast hash codes */
        !            50:        short   csr;                    /* control and status register */
        !            51:        short   tseg;                   /* current transmit segment # */
        !            52:        short   rseg;                   /* current receive  segment # */
        !            53:        short   segb;                   /* segment boundary register */
        !            54:        short   lrf;                    /* lost receive frame counter */
        !            55:        short   ivct;                   /* interrupt vector register */
        !            56:        short   resv;                   /* reserved for future use */
        !            57:        short   fcoll;                  /* force collision register */
        !            58: };
        !            59: 
        !            60: /*
        !            61:  * Transmit segment in dual ported ram.
        !            62:  */
        !            63: struct tx_segment {
        !            64:        short   tx_csr;         /* packet status */
        !            65:        char    tx_data[2014];
        !            66:        short   tx_backoff[16]; /* random backoff counters */
        !            67: };
        !            68: 
        !            69: /*
        !            70:  * Receive segment in dual ported ram.
        !            71:  */
        !            72: struct rx_segment {
        !            73:        short   rx_csr;         /* packet status */
        !            74:        char    rx_data[2046];
        !            75: };
        !            76: 
        !            77: /*
        !            78:  * ACC statistics block.
        !            79:  */ 
        !            80: struct ace_stats {
        !            81:        int     rx_datagrams;           /* valid packets received */
        !            82:        int     rx_crc_errors;          /* CRC errors */
        !            83:        int     rx_overruns;            /* packets too large */
        !            84:        int     rx_underruns;           /* packets too small */
        !            85:        int     rx_align_errors;        /* packets w/ odd byte count */
        !            86:        int     rx_reserved;
        !            87:        int     rx_busy;                /* recv segment filled */
        !            88:        int     rx_mbuf;                /* out of mbufs */
        !            89:        int     rx_oddoff;              /* odd offset in mbuf */
        !            90:        int     rx_rintcnt;             /* recvr interrupt */
        !            91: 
        !            92:        int     tx_datagrams;           /* packets xmit'd */
        !            93:        int     tx_retries;             /* collision retries */
        !            94:        int     tx_discarded;           /* packets w/ max retries */
        !            95:        int     tx_busy;                /* xmit segment filled in acestart */
        !            96:        int     tx_cbusy;               /* xmit segment filled in acecint */
        !            97:        int     tx_mbuf;                /* total mbufs */
        !            98:        int     tx_oddoff;              /* odd offset in mbuf */
        !            99:        int     tx_outcnt;              /* calls to aceoutput */
        !           100:        int     tx_startcnt;            /* calls to acestart */
        !           101:        int     tx_cintcnt;             /* xmit's completed */
        !           102: };
        !           103: 
        !           104: /*
        !           105:  * Control status definitions.
        !           106:  */
        !           107: #define CSR_OBCENA     0x0200  /* enable xmit of odd byte count */
        !           108: #define CSR_ACTIVE     0x0080  /* board active */
        !           109: #define CSR_RESET      0x0040  /* reset board */
        !           110: #define CSR_PROMISC    0x0020  /* enable promiscous mode */
        !           111: #define CSR_CRCDIS     0x0010  /* disable CRC generation */
        !           112: #define CSR_LOOP3      0x0008  /* enable loopback mode 3 */
        !           113: #define CSR_LOOP2      0x0004  /* enable loopback mode 2 */
        !           114: #define CSR_IENA       0x0002  /* interrupt enable */
        !           115: #define CSR_GO         0x0001  /* enable micro-engine */
        !           116: 
        !           117: #define        ACE_CSRBITS \
        !           118:     "\20\12OBCENA\10ACTIVE\7RESET\6PROMISC\5CRCDIS\4LOOP3\3LOOP2\2IENA\1GO"
        !           119: /*
        !           120:  * Transmit packet status definitions.
        !           121:  */
        !           122: #define TCS_TBFULL     (short)0x8000   /* buffer filled, send it */
        !           123: #define TCS_TBC                (short)0x07FF   /* byte count */
        !           124: #define TCS_TBMT       (short)0x8000   /* buffer empty */
        !           125: #define TCS_RTFAIL     (short)0x4000   /* retries failed */
        !           126: #define TCS_RTC                (short)0x000F   /* collision retry mask */
        !           127: 
        !           128: /*
        !           129:  * Receive packet status definitions.
        !           130:  */
        !           131: #define RCS_RBMT       0x8000          /* buffer ready for recv */
        !           132: #define RCS_RBFULL     0x8000          /* buffer full, take data */
        !           133: #define RCS_ROVRN      0x4000          /* overrun error */
        !           134: #define RCS_RCRC       0x2000          /* CRC error */
        !           135: #define RCS_RODD       0x1000          /* odd byte count error */
        !           136: #define RCS_RBC                0x07FF          /* byte count mask */
        !           137: 
        !           138: #define        ACE_RCSBITS     "\20\20RBFULL\17ROVRN\16RCSR\15RODD"
        !           139: 
        !           140: #define CRC_SIZE       4         /* number of bytes in a rx seg's CRC */
        !           141: #define RCW_SIZE       2         /* number of bytes in a rx seg's csr */
        !           142: #define SEG_MAX                15        /* largest valid segment number */
        !           143: #define ET_MINLEN       64        /* min frame size */
        !           144: #define ET_MAXLEN       1514      /* max frame size w/o CRC & RCW */

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