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Annotation of Net2/arch/tahoe/vba/drreg.h, revision 1.1

1.1     ! root        1: /*
        !             2:  * Copyright (c) 1988 The Regents of the University of California.
        !             3:  * All rights reserved.
        !             4:  *
        !             5:  * This code is derived from software contributed to Berkeley by
        !             6:  * Computer Consoles Inc.
        !             7:  *
        !             8:  * Redistribution and use in source and binary forms, with or without
        !             9:  * modification, are permitted provided that the following conditions
        !            10:  * are met:
        !            11:  * 1. Redistributions of source code must retain the above copyright
        !            12:  *    notice, this list of conditions and the following disclaimer.
        !            13:  * 2. Redistributions in binary form must reproduce the above copyright
        !            14:  *    notice, this list of conditions and the following disclaimer in the
        !            15:  *    documentation and/or other materials provided with the distribution.
        !            16:  * 3. All advertising materials mentioning features or use of this software
        !            17:  *    must display the following acknowledgement:
        !            18:  *     This product includes software developed by the University of
        !            19:  *     California, Berkeley and its contributors.
        !            20:  * 4. Neither the name of the University nor the names of its contributors
        !            21:  *    may be used to endorse or promote products derived from this software
        !            22:  *    without specific prior written permission.
        !            23:  *
        !            24:  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
        !            25:  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
        !            26:  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
        !            27:  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
        !            28:  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
        !            29:  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
        !            30:  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
        !            31:  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
        !            32:  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
        !            33:  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
        !            34:  * SUCH DAMAGE.
        !            35:  *
        !            36:  *     @(#)drreg.h     7.3 (Berkeley) 6/28/90
        !            37:  */
        !            38: 
        !            39: /*
        !            40:     ------------------------------------------
        !            41:     Must include <h/types.h> and <h/buf.h>
        !            42:     ------------------------------------------
        !            43: */
        !            44: 
        !            45: #define        DRINTV  0x9c            /* Has to match with ml/scb.s */
        !            46: #define DRADDMOD 0x01          /* Addr modifier used to access TAHOE memory */
        !            47: #define DR_ZERO 0
        !            48: #define DRPRI  (PZERO+1)
        !            49: 
        !            50: #define DR_TICK 600            /* Default # of clock ticks between call
        !            51:                                   to local timer watchdog routine */
        !            52: #define        DR_TOCK 2               /* default # of calls to local watch dog
        !            53:                                   before an IO or wait is determined to
        !            54:                                   have timeout */
        !            55: 
        !            56: 
        !            57: struct rsdevice {
        !            58:     ushort dr_cstat;           /* Control & status registers */
        !            59:     ushort dr_data;            /* Input/Ouptut data registers */
        !            60:     char dr_addmod;            /* Address modifier for DMA */
        !            61:     char dr_intvect;           /* Interrupt vector */
        !            62:     ushort dr_pulse;           /* Pulse command register */
        !            63:     ushort dr_xx08;            /* Not used */
        !            64:     ushort dr_xx0A;            /* Not used */
        !            65:     ushort dr_xx0C;            /* Not used */
        !            66:     ushort dr_xx0E;            /* Not used */
        !            67:     ushort dr_xx10;            /* Not used */
        !            68:     ushort dr_walo;            /* Low DMA address register --when written-- */
        !            69:     ushort dr_range;           /* DMA range counter */
        !            70:     ushort dr_ralo;            /* Low DMA address register --when read-- */
        !            71:     ushort dr_xx18;            /* Not used */
        !            72:     ushort dr_wahi;            /* High DMA address register --when written-- */
        !            73:     ushort dr_xx1C;            /* Not used */
        !            74:     ushort dr_rahi;            /* High DMA address register --when read-- */
        !            75: };
        !            76: 
        !            77: 
        !            78: struct dr_aux {
        !            79:        struct rsdevice *dr_addr; /* Physical addr of currently active DR11 */
        !            80:        struct buf *dr_actf;    /* Pointers to DR11's active buffers list */
        !            81:        unsigned int dr_flags;  /* State: Hold open, active,... */
        !            82:        ushort dr_cmd;          /* Hold cmd placed here by ioctl
        !            83:                                   for later execution by rsstrategy() */
        !            84:        ushort dr_op;           /* Current operation: DR_READ/DR_WRITE */
        !            85:        long   dr_bycnt;        /* Total byte cnt of current operation */
        !            86:                                /* decremented by completion interrupt */
        !            87:        caddr_t dr_oba;         /* original xfer addr, count */
        !            88:        long   dr_obc;
        !            89:        unsigned long
        !            90:                rtimoticks,     /* No of ticks before timing out on no stall
        !            91:                                   read */
        !            92:                wtimoticks,     /* No of ticks before timing out on no stall
        !            93:                                   write */
        !            94:                currenttimo;    /* the number of current timeout call to
        !            95:                                   omrwtimo() */
        !            96:        ushort dr_istat;        /* Latest interrupt status */
        !            97:        struct buf dr_buf;
        !            98: 
        !            99:        /*ushort dr_time;               /* # of ticks until timeout */
        !           100:        /*ushort dr_tock;               /* # of ticks accumulated */
        !           101:        /*ushort dr_cseq;               /* Current sequence number */
        !           102:        /*ushort dr_lseq;               /* Last sequence number */
        !           103: };
        !           104: 
        !           105: /*     Command used by drioctl() 
        !           106: */
        !           107: struct dr11io {
        !           108:        ushort arg[8];
        !           109: };
        !           110: 
        !           111: #define RSADDR(unit)    ((struct rsdevice *)drinfo[unit]->ui_addr)
        !           112: 
        !           113: /*     Control register bits */
        !           114: #define        RDMA    0x8000          /* reset DMA end-of-range flag */
        !           115: #define        RATN    0x4000          /* reset attention flag */
        !           116: #define RPER   0x2000          /* reset device parity error flag */
        !           117: #define MCLR   0x1000          /* master clear board and INT device */
        !           118: #define CYCL   0x0100          /* forces DMA cycle if DMA enabled */
        !           119: #define IENB   0x0040          /* enables interrupt */
        !           120: #define FCN3   0x0008          /* func. bit 3 to device (FNCT3 H) */
        !           121: #define FCN2   0x0004          /* func. bit 2 to device (FNCT2 H) */
        !           122:                                /* also asserts ACLO FCNT2 H to device */
        !           123: #define FCN1   0x0002          /* func. bit 1 to device (FNCT1 H) */
        !           124: #define GO     0x0001          /* enable DMA and pulse GO to device */
        !           125: 
        !           126: /*     Status register bits */
        !           127: #define        DMAF    0x8000          /* indicates DMA end-of-range */
        !           128: #define        ATTF    0x4000          /* indicates attention false-to-true */
        !           129: #define ATTN   0x2000          /* current state of ATTENTION H input */
        !           130: #define PERR   0x1000          /* Set by external parity error */
        !           131: #define STTA   0x0800          /* STATUS A H input state */
        !           132: #define STTB   0x0400          /* STATUS B H input state */
        !           133: #define STTC   0x0200          /* STATUS C H input state */
        !           134: #define REDY   0x0080          /* board ready for cmd (dma not on) */
        !           135: #define IENF   0x0040          /* Interrupt enabled if on */
        !           136: #define BERR   0x0020          /* Set if bus error during DMA */
        !           137: #define TERR   0x0010          /* Set if bus timeout during DMA */
        !           138: #define FC3S   0x0008          /* State of FCN3 latch */
        !           139: #define FC2S   0x0004          /* State of FCN2 latch */
        !           140: #define FC1S   0x0002          /* State of FCN1 latch */
        !           141: #define DLFG   0x0001          /* 0 -> IKON-10083 *** 1 -> IKON-10077 */
        !           142: 
        !           143: /*     Pulse command register bits */
        !           144: #define SMSK   0x0040          /* pulse interrupt mask on:  Set IENB */
        !           145: #define RMSK   0x0020          /* pulse interrupt mask off: Reset IENB */
        !           146: 
        !           147: 
        !           148: /*     
        !           149:  *     DR11 driver's internal flags -- to be stored in dr_flags 
        !           150: */
        !           151: #define DR_FMSK                0x0000E /* function bits mask */
        !           152: #define        DR_OPEN         0x00001 /* This dr11 has been opened */
        !           153: #define DR_PRES                0x00002 /* This dr11 is present */
        !           154: #define DR_ACTV                0x00004 /* waiting for end-of-range */
        !           155: #define DR_ATWT        0x00008 /* waiting for attention interrupt */
        !           156: #define DR_ATRX        0x00010 /* attn received-resets when read */
        !           157: #define DR_TMDM                0x00020 /* timeout waiting for end-of-range */
        !           158: #define DR_TMAT                0x00040 /* timeout waiting for attention */
        !           159: #define DR_DMAX                0x00080 /* end-of-range interrupt received */
        !           160: #define DR_PCYL                0x00100 /* set cycle with next go */
        !           161: #define DR_DFCN        0x00200 /* donot update function bits until next  go */
        !           162: #define DR_DACL                0x00400 /* defer alco pulse until go */
        !           163: #define DR_LOOPTST     0x02000 /* This dr11 is in loopback test mode */
        !           164: #define DR_LNKMODE     0x04000 /* This dr11 is in link mode */
        !           165: #define        DR_NORSTALL     0x10000 /* Device is set to no stall mode for reads. */
        !           166: #define        DR_NOWSTALL     0x20000 /* Device is set to no stall mode for writes. */
        !           167: #define        DR_TIMEDOUT     0x40000 /* The device timed out on a stall mode R/W */
        !           168: 
        !           169: /*     
        !           170:  *     DR11 driver's internal flags -- to be stored in dr_op 
        !           171: */
        !           172: #define        DR_READ         FCN1
        !           173: #define DR_WRITE       0
        !           174: 
        !           175: /*
        !           176:  *     Ioctl commands
        !           177: */
        !           178: #define DRWAIT         _IOWR('d',1,long)
        !           179: #define        DRPIOW          _IOWR('d',2,long)
        !           180: #define DRPACL         _IOWR('d',3,long)
        !           181: #define DRDACL         _IOWR('d',4,long)
        !           182: #define DRPCYL         _IOWR('d',5,long)
        !           183: #define DRDFCN                 _IOWR('d',6,long)
        !           184: #define DRRPER                 _IOWR('d',7,long)
        !           185: #define DRRATN         _IOWR('d',8,long)
        !           186: #define DRRDMA                 _IOWR('d',9,long)
        !           187: #define DRSFCN                 _IOWR('d',10,long)
        !           188: 
        !           189: #define        DRSETRSTALL     _IOWR('d',13,long)
        !           190: #define        DRSETNORSTALL   _IOWR('d',14,long)
        !           191: #define        DRGETRSTALL     _IOWR('d',15,long)
        !           192: #define        DRSETRTIMEOUT   _IOWR('d',16,long)
        !           193: #define        DRGETRTIMEOUT   _IOWR('d',17,long)
        !           194: #define        DRSETWSTALL     _IOWR('d',18,long)
        !           195: #define        DRSETNOWSTALL   _IOWR('d',19,long)
        !           196: #define        DRGETWSTALL     _IOWR('d',20,long)
        !           197: #define        DRSETWTIMEOUT   _IOWR('d',21,long)
        !           198: #define        DRGETWTIMEOUT   _IOWR('d',22,long)
        !           199: #define        DRWRITEREADY    _IOWR('d',23,long)
        !           200: #define        DRREADREADY     _IOWR('d',24,long)
        !           201: #define        DRBUSY          _IOWR('d',25,long)
        !           202: #define        DRRESET         _IOWR('d',26,long)
        !           203: 
        !           204: /* The block size for buffering and DMA transfers. */
        !           205: /* OM_BLOCKSIZE must be even and <= 32768. Multiples of 512 are prefered. */
        !           206: #define        OM_BLOCKSIZE    32768
        !           207: 
        !           208: 
        !           209: /* --- Define ioctl call used by dr11 utility device --  */
        !           210: 
        !           211: #define DR11STAT       _IOWR('d',30,struct dr11io)   /* Get status dr11, unit 
        !           212:                                                   number is dr11io.arg[0] */
        !           213: #define DR11LOOP       _IOR('d',31,struct dr11io)   /* Perform loopback test */
        !           214: 
        !           215: /* ---------------------------------------------------- */
        !           216: 

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