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1.1 root 1: /*
2: * Copyright (c) 1986 The Regents of the University of California.
3: * All rights reserved.
4: *
5: * Redistribution and use in source and binary forms, with or without
6: * modification, are permitted provided that the following conditions
7: * are met:
8: * 1. Redistributions of source code must retain the above copyright
9: * notice, this list of conditions and the following disclaimer.
10: * 2. Redistributions in binary form must reproduce the above copyright
11: * notice, this list of conditions and the following disclaimer in the
12: * documentation and/or other materials provided with the distribution.
13: * 3. All advertising materials mentioning features or use of this software
14: * must display the following acknowledgement:
15: * This product includes software developed by the University of
16: * California, Berkeley and its contributors.
17: * 4. Neither the name of the University nor the names of its contributors
18: * may be used to endorse or promote products derived from this software
19: * without specific prior written permission.
20: *
21: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31: * SUCH DAMAGE.
32: *
33: * @(#)ikreg.h 7.3 (Berkeley) 6/28/90
34: */
35:
36: /*
37: * IKON DR-11W register definitions.
38: */
39: struct ikdevice {
40: u_short ik_csr; /* control status register */
41: u_short ik_data; /* data in/out register */
42: u_char ik_mod; /* address modifier */
43: u_char ik_vec; /* interrupt vector */
44: u_short ik_pulse; /* pulse commands (w) */
45: u_short ik_fill[5];
46: u_short ik_balo; /* low word of dma beginning address (w) */
47: u_short ik_wc; /* dma word count */
48: u_short ik_calo; /* low word of dma current address (r) */
49: u_short ik_fill1;
50: u_short ik_bahi; /* high word of dma beginning address (w) */
51: u_short ik_fill2;
52: u_short ik_cahi; /* high word of dma current address (r) */
53: };
54:
55: /*
56: * CSR control definitions (write-only).
57: */
58: #define IKCSR_GO 0x0001 /* start dma */
59: #define IKCSR_FNC1 0x0002 /* function bit 1 */
60: #define IKCSR_FNC2 0x0004 /* function bit 2 */
61: #define IKCSR_FNC3 0x0008 /* function bit 3 */
62: /* bits 4-5 are unused */
63: #define IKCSR_IENA 0x0040 /* enable/disable interrupts */
64: /* bit 7 is unused */
65: #define IKCSR_CYCLE 0x0100 /* force dma to cycle */
66: /* bits 9-11 are unused */
67: #define IKCSR_MCLR 0x1000 /* master clear board */
68: #define IKCSR_RPERR 0x2000 /* reset parity error */
69: #define IKCSR_RATTF 0x4000 /* reset attention */
70: #define IKCSR_RDMAF 0x8000 /* reset dma completion */
71:
72: /*
73: * CSR status definitions (read-only).
74: */
75: #define IKCSR_DEV 0x0001 /* device flag (0 = 10083, 1 = 10077) */
76: /* bits 1-3 reflect the function latch state */
77: #define IKCSR_TIMO 0x0010 /* bus timeout during dma */
78: #define IKCSR_BERR 0x0020 /* bus error during dma */
79: /* bit 6 reflects interrupt enable state */
80: #define IKCSR_READY 0x0080 /* device ready for next command */
81: /* bit 8 should be 0 */
82: #define IKCSR_STATC 0x0200 /* status bit C */
83: #define IKCSR_STATB 0x0400 /* status bit B */
84: #define IKCSR_STATA 0x0800 /* status bit A */
85: #define IKCSR_PERR 0x1000 /* parity error during pi/o or dma */
86: #define IKCSR_ATTN 0x2000 /* current state of attention bit */
87: #define IKCSR_ATTF 0x4000 /* latched attention t-f transition */
88: #define IKCSR_DMAF 0x8000 /* dma completed or terminated */
89:
90: #define IKCSR_BITS \
91: "\020\1DEV\2FNC1\3FNC2\4FNC3\5TIMO\6BERR\7IENA\10READY\12STATC\13STATB\14STATA\
92: \15PERR\16ATTN\17ATTF\20DMAF"
93:
94: /*
95: * Pulse command register definitions (write-only).
96: */
97: #define IKPULSE_GO 0x0001 /* enable dma */
98: #define IKPULSE_FNC2 0x0004 /* pulse function bit 1 */
99: #define IKPULSE_RIENA 0x0020 /* reset IKCSR_IENA */
100: #define IKPULSE_SIENA 0x0040 /* set IKCSR_IENA */
101: #define IKPULSE_CYCL 0x0100 /* force dma to cycle */
102: #define IKPULSE_MCLR 0x1000 /* initialize interface */
103: #define IKPULSE_RPERR 0x2000 /* reset IKCSR_PERR */
104: #define IKPULSE_RATTF 0x4000 /* reset IKCSR_ATTF */
105: #define IKPULSE_RDMAF 0x8000 /* reset IKCSR_DMAF */
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