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1.1 root 1: /*
2: * Copyright (c) 1988 Regents of the University of California.
3: * All rights reserved.
4: *
5: * This code is derived from software contributed to Berkeley by
6: * Chris Torek.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: * 3. All advertising materials mentioning features or use of this software
17: * must display the following acknowledgement:
18: * This product includes software developed by the University of
19: * California, Berkeley and its contributors.
20: * 4. Neither the name of the University nor the names of its contributors
21: * may be used to endorse or promote products derived from this software
22: * without specific prior written permission.
23: *
24: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34: * SUCH DAMAGE.
35: *
36: * @(#)bireg.h 7.3 (Berkeley) 6/28/90
37: */
38:
39: /*
40: * VAXBI node definitions.
41: */
42:
43: /*
44: * BI node addresses
45: */
46: #define BI_BASE(bi) ((struct bi_node *) (0x20000000 + (bi)*0x2000000))
47: #define NNODEBI 16 /* 16 nodes per BI */
48: /* `local space' 0x20800000 /* ??? */
49:
50: #ifndef LOCORE
51: /*
52: * BI nodes all start with BI interface registers (those on the BIIC chip).
53: * These are followed with interface-specific registers.
54: *
55: * NB: This structure does NOT include the four GPRs (not anymore!)
56: */
57: struct biiregs {
58: u_short bi_dtype; /* device type */
59: u_short bi_revs; /* revisions */
60: u_long bi_csr; /* control and status register */
61: u_long bi_ber; /* bus error register */
62: u_long bi_eintrcsr; /* error interrupt control register */
63: u_long bi_intrdes; /* interrupt destination register */
64: /* the rest are not required for all nodes */
65: u_long bi_ipintrmsk; /* IP interrupt mask register */
66: u_long bi_fipsdes; /* Force-Bit IPINTR/STOP destination reg */
67: u_long bi_ipintrsrc; /* IPINTR source register */
68: u_long bi_sadr; /* starting address register */
69: u_long bi_eadr; /* ending address register */
70: u_long bi_bcicsr; /* BCI control and status register */
71: u_long bi_wstat; /* write status register */
72: u_long bi_fipscmd; /* Force-Bit IPINTR/STOP command reg */
73: u_long bi_xxx1[3]; /* unused */
74: u_long bi_uintrcsr; /* user interface interrupt control reg */
75: u_long bi_xxx2[43]; /* unused */
76: /* although these are on the BIIC, their interpretation varies */
77: /* u_long bi_gpr[4]; /* general purpose registers */
78: };
79:
80: /*
81: * A generic BI node.
82: */
83: struct bi_node {
84: struct biiregs biic; /* interface */
85: u_long bi_xxx[1988]; /* pad to 8K */
86: };
87:
88: /*
89: * A cpu node.
90: */
91: struct bi_cpu {
92: struct biiregs biic; /* interface chip */
93: u_long bi_gpr[4]; /* gprs (unused) */
94: u_long bi_sosr; /* slave only status register */
95: u_long bi_xxx[63]; /* pad */
96: u_long bi_rxcd; /* receive console data register */
97: };
98: #endif LOCORE
99:
100: /* device types */
101: #define BIDT_MS820 0x0001 /* MS820 memory board */
102: #define BIDT_DWBUA 0x0102 /* DWBUA Unibus adapter */
103: #define BIDT_KLESI 0x0103 /* KLESI-B adapter */
104: #define BIDT_KA820 0x0105 /* KA820 cpu */
105: #define BIDT_DB88 0x0106 /* DB88 adapter */
106: #define BIDT_DMB32 0x0109 /* DMB32 adapter */
107: #define BIDT_KDB50 0x010e /* KDB50 disk controller */
108: #define BIDT_DEBNK 0x410e /* BI Ethernet (Lance) + TK50 */
109: #define BIDT_DEBNA 0x410f /* BI Ethernet (Lance) adapter */
110:
111: #ifdef notdef /* CPU (KA820) bits in bi_revs */
112: #define BI_CPUREV(x) (((x) >> 11)) /* CPU revision code */
113: #define BI_UPATCHREV(x) (((x) >> 1) & 0x3ff) /* microcode patch rev */
114: #define BI_SPATCHREV(x) (((x) & 1) /* secondary patch rev */
115: #endif
116:
117: /* bits in bi_csr */
118: #define BICSR_IREV(x) ((u_char)((x) >> 24)) /* VAXBI interface rev */
119: #define BICSR_TYPE(x) ((u_char)((x) >> 16)) /* BIIC type */
120: #define BICSR_HES 0x8000 /* hard error summary */
121: #define BICSR_SES 0x4000 /* soft error summary */
122: #define BICSR_INIT 0x2000 /* initialise node */
123: #define BICSR_BROKE 0x1000 /* broke */
124: #define BICSR_STS 0x0800 /* self test status */
125: #define BICSR_NRST 0x0400 /* node reset */
126: #define BICSR_UWP 0x0100 /* unlock write pending */
127: #define BICSR_HEIE 0x0080 /* hard error interrupt enable */
128: #define BICSR_SEIE 0x0040 /* soft error interrupt enable */
129: #define BICSR_ARB_MASK 0x0030 /* mask to get arbitration codes */
130: #define BICSR_ARB_NONE 0x0030 /* no arbitration */
131: #define BICSR_ARB_LOG 0x0020 /* low priority */
132: #define BICSR_ARB_HIGH 0x0010 /* high priority */
133: #define BICSR_ARB_RR 0x0000 /* round robin */
134: #define BICSR_NODEMASK 0x000f /* node ID */
135:
136: #define BICSR_BITS \
137: "\20\20HES\17SES\16INIT\15BROKE\14STS\13NRST\11UWP\10HEIE\7SEIE"
138:
139: /* bits in bi_ber */
140: #define BIBER_MBZ 0x8000fff0
141: #define BIBER_NMR 0x40000000 /* no ack to multi-responder command */
142: #define BIBER_MTCE 0x20000000 /* master transmit check error */
143: #define BIBER_CTE 0x10000000 /* control transmit error */
144: #define BIBER_MPE 0x08000000 /* master parity error */
145: #define BIBER_ISE 0x04000000 /* interlock sequence error */
146: #define BIBER_TDF 0x02000000 /* transmitter during fault */
147: #define BIBER_IVE 0x01000000 /* ident vector error */
148: #define BIBER_CPE 0x00800000 /* command parity error */
149: #define BIBER_SPE 0x00400000 /* slave parity error */
150: #define BIBER_RDS 0x00200000 /* read data substitute */
151: #define BIBER_RTO 0x00100000 /* retry timeout */
152: #define BIBER_STO 0x00080000 /* stall timeout */
153: #define BIBER_BTO 0x00040000 /* bus timeout */
154: #define BIBER_NEX 0x00020000 /* nonexistent address */
155: #define BIBER_ICE 0x00010000 /* illegal confirmation error */
156: #define BIBER_UPEN 0x00000008 /* user parity enable */
157: #define BIBER_IPE 0x00000004 /* ID parity error */
158: #define BIBER_CRD 0x00000002 /* corrected read data */
159: #define BIBER_NPE 0x00000001 /* null bus parity error */
160: #define BIBER_HARD 0x4fff0000
161:
162: #define BIBER_BITS \
163: "\20\37NMR\36MTCE\35CTE\34MPE\33ISE\32TDF\31IVE\30CPE\
164: \27SPE\26RDS\25RTO\24STO\23BTO\22NEX\21ICE\4UPEN\3IPE\2CRD\1NPE"
165:
166: /* bits in bi_eintrcsr */
167: #define BIEIC_INTRAB 0x01000000 /* interrupt abort */
168: #define BIEIC_INTRC 0x00800000 /* interrupt complete */
169: #define BIEIC_INTRSENT 0x00200000 /* interrupt command sent */
170: #define BIEIC_INTRFORCE 0x00100000 /* interrupt force */
171: #define BIEIC_LEVELMASK 0x000f0000 /* mask for interrupt levels */
172: #define BIEIC_IPL17 0x00080000 /* ipl 0x17 */
173: #define BIEIC_IPL16 0x00040000 /* ipl 0x16 */
174: #define BIEIC_IPL15 0x00020000 /* ipl 0x15 */
175: #define BIEIC_IPL14 0x00010000 /* ipl 0x14 */
176: #define BIEIC_VECMASK 0x00003ffc /* vector mask for error intr */
177:
178: /* bits in bi_intrdes */
179: #define BIDEST_MASK 0x0000ffff /* one bit per node to be intr'ed */
180:
181: /* bits in bi_ipintrmsk */
182: #define BIIPINTR_MASK 0xffff0000 /* one per node to allow to ipintr */
183:
184: /* bits in bi_fipsdes */
185: #define BIFIPSD_MASK 0x0000ffff
186:
187: /* bits in bi_ipintrsrc */
188: #define BIIPSRC_MASK 0xffff0000
189:
190: /* sadr and eadr are simple addresses */
191:
192: /* bits in bi_bcicsr */
193: #define BCI_BURSTEN 0x00020000 /* burst mode enable */
194: #define BCI_IPSTOP_FRC 0x00010000 /* ipintr/stop force */
195: #define BCI_MCASTEN 0x00008000 /* multicast space enable */
196: #define BCI_BCASTEN 0x00004000 /* broadcast enable */
197: #define BCI_STOPEN 0x00002000 /* stop enable */
198: #define BCI_RSRVDEN 0x00001000 /* reserved enable */
199: #define BCI_IDENTEN 0x00000800 /* ident enable */
200: #define BCI_INVALEN 0x00000400 /* inval enable */
201: #define BCI_WINVEN 0x00000200 /* write invalidate enable */
202: #define BCI_UINTEN 0x00000100 /* user interface csr space enable */
203: #define BCI_BIICEN 0x00000080 /* BIIC csr space enable */
204: #define BCI_INTEN 0x00000040 /* interrupt enable */
205: #define BCI_IPINTEN 0x00000020 /* ipintr enable */
206: #define BCI_PIPEEN 0x00000010 /* pipeline NXT enable */
207: #define BCI_RTOEVEN 0x00000008 /* read timeout EV enable */
208:
209: #define BCI_BITS \
210: "\20\22BURSTEN\21IPSTOP_FRC\20MCASTEN\
211: \17BCASTEN\16STOPEN\15RSRVDEN\14IDENTEN\13INVALEN\12WINVEN\11UINTEN\
212: \10BIICEN\7INTEN\6IPINTEN\5PIPEEN\4RTOEVEN"
213:
214: /* bits in bi_wstat */
215: #define BIW_GPR3 0x80000000 /* gpr 3 was written */
216: #define BIW_GPR2 0x40000000 /* gpr 2 was written */
217: #define BIW_GPR1 0x20000000 /* gpr 1 was written */
218: #define BIW_GPR0 0x10000000 /* gpr 0 was written */
219:
220: /* bits in force-bit ipintr/stop command register 8/
221: #define BIFIPSC_CMDMASK 0x0000f000 /* command */
222: #define BIFIPSC_MIDEN 0x00000800 /* master ID enable */
223:
224: /* bits in bi_uintcsr */
225: #define BIUI_INTAB 0xf0000000 /* interrupt abort level */
226: #define BIUI_INTC 0x0f000000 /* interrupt complete bits */
227: #define BIUI_SENT 0x00f00000 /* interrupt sent bits */
228: #define BIUI_FORCE 0x000f0000 /* force interrupt level */
229: #define BIUI_EVECEN 0x00008000 /* external vector enable */
230: #define BIUI_VEC 0x00003ffc /* interrupt vector */
231:
232: /* tell if a bi device is a slave (hence has SOSR) */
233: #define BIDT_ISSLAVE(x) (((x) & 0x7f00) == 0)
234:
235: /* bits in bi_sosr */
236: #define BISOSR_MEMSIZE 0x1ffc0000 /* memory size */
237: #define BISOSR_BROKE 0x00001000 /* broke */
238:
239: /* bits in bi_rxcd */
240: #define BIRXCD_BUSY2 0x80000000 /* busy 2 */
241: #define BIRXCD_NODE2 0x0f000000 /* node id 2 */
242: #define BIRXCD_CHAR2 0x00ff0000 /* character 2 */
243: #define BIRXCD_BUSY1 0x00008000 /* busy 1 */
244: #define BIRXCD_NODE1 0x00000f00 /* node id 1 */
245: #define BIRXCD_CHAR1 0x000000ff /* character 1 */
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