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1.1 root 1: /*
2: * Copyright (c) 1982, 1986 Regents of the University of California.
3: * All rights reserved.
4: *
5: * Redistribution and use in source and binary forms, with or without
6: * modification, are permitted provided that the following conditions
7: * are met:
8: * 1. Redistributions of source code must retain the above copyright
9: * notice, this list of conditions and the following disclaimer.
10: * 2. Redistributions in binary form must reproduce the above copyright
11: * notice, this list of conditions and the following disclaimer in the
12: * documentation and/or other materials provided with the distribution.
13: * 3. All advertising materials mentioning features or use of this software
14: * must display the following acknowledgement:
15: * This product includes software developed by the University of
16: * California, Berkeley and its contributors.
17: * 4. Neither the name of the University nor the names of its contributors
18: * may be used to endorse or promote products derived from this software
19: * without specific prior written permission.
20: *
21: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31: * SUCH DAMAGE.
32: *
33: * @(#)if_dereg.h 7.3 (Berkeley) 6/28/90
34: */
35:
36: /*
37: * DEC DEUNA interface
38: */
39: struct dedevice {
40: union {
41: short p0_w;
42: char p0_b[2];
43: } u_p0;
44: #define pcsr0 u_p0.p0_w
45: #define pclow u_p0.p0_b[0]
46: #define pchigh u_p0.p0_b[1]
47: short pcsr1;
48: short pcsr2;
49: short pcsr3;
50: };
51:
52: /*
53: * PCSR 0 bit descriptions
54: */
55: #define PCSR0_SERI 0x8000 /* Status error interrupt */
56: #define PCSR0_PCEI 0x4000 /* Port command error interrupt */
57: #define PCSR0_RXI 0x2000 /* Receive done interrupt */
58: #define PCSR0_TXI 0x1000 /* Transmit done interrupt */
59: #define PCSR0_DNI 0x0800 /* Done interrupt */
60: #define PCSR0_RCBI 0x0400 /* Receive buffer unavail intrpt */
61: #define PCSR0_FATI 0x0100 /* Fatal error interrupt */
62: #define PCSR0_INTR 0x0080 /* Interrupt summary */
63: #define PCSR0_INTE 0x0040 /* Interrupt enable */
64: #define PCSR0_RSET 0x0020 /* DEUNA reset */
65: #define PCSR0_CMASK 0x000f /* command mask */
66:
67: #define PCSR0_BITS "\20\20SERI\17PCEI\16RXI\15TXI\14DNI\13RCBI\11FATI\10INTR\7INTE\6RSET"
68:
69: /* bits 0-3 are for the PORT_COMMAND */
70: #define CMD_NOOP 0x0
71: #define CMD_GETPCBB 0x1 /* Get PCB Block */
72: #define CMD_GETCMD 0x2 /* Execute command in PCB */
73: #define CMD_STEST 0x3 /* Self test mode */
74: #define CMD_START 0x4 /* Reset xmit and receive ring ptrs */
75: #define CMD_BOOT 0x5 /* Boot DEUNA */
76: #define CMD_PDMD 0x8 /* Polling demand */
77: #define CMD_TMRO 0x9 /* Sanity timer on */
78: #define CMD_TMRF 0xa /* Sanity timer off */
79: #define CMD_RSTT 0xb /* Reset sanity timer */
80: #define CMD_STOP 0xf /* Suspend operation */
81:
82: /*
83: * PCSR 1 bit descriptions
84: */
85: #define PCSR1_XPWR 0x8000 /* Transceiver power BAD */
86: #define PCSR1_ICAB 0x4000 /* Interconnect cabling BAD */
87: #define PCSR1_STCODE 0x3f00 /* Self test error code */
88: #define PCSR1_PCTO 0x0080 /* Port command timed out */
89: #define PCSR1_ILLINT 0x0040 /* Illegal interrupt */
90: #define PCSR1_TIMEOUT 0x0020 /* Timeout */
91: #define PCSR1_POWER 0x0010 /* Power fail */
92: #define PCSR1_RMTC 0x0008 /* Remote console reserved */
93: #define PCSR1_STMASK 0x0007 /* State */
94:
95: /* bit 0-3 are for STATE */
96: #define STAT_RESET 0x0
97: #define STAT_PRIMLD 0x1 /* Primary load */
98: #define STAT_READY 0x2
99: #define STAT_RUN 0x3
100: #define STAT_UHALT 0x5 /* UNIBUS halted */
101: #define STAT_NIHALT 0x6 /* NI halted */
102: #define STAT_NIUHALT 0x7 /* NI and UNIBUS Halted */
103:
104: #define PCSR1_BITS "\20\20XPWR\17ICAB\10PCTO\7ILLINT\6TIMEOUT\5POWER\4RMTC"
105:
106: /*
107: * Port Control Block Base
108: */
109: struct de_pcbb {
110: short pcbb0; /* function */
111: short pcbb2; /* command specific */
112: short pcbb4;
113: short pcbb6;
114: };
115:
116: /* PCBB function codes */
117: #define FC_NOOP 0x00 /* NO-OP */
118: #define FC_LSUADDR 0x01 /* Load and start microaddress */
119: #define FC_RDDEFAULT 0x02 /* Read default physical address */
120: #define FC_RDPHYAD 0x04 /* Read physical address */
121: #define FC_WTPHYAD 0x05 /* Write physical address */
122: #define FC_RDMULTI 0x06 /* Read multicast address list */
123: #define FC_WTMULTI 0x07 /* Read multicast address list */
124: #define FC_RDRING 0x08 /* Read ring format */
125: #define FC_WTRING 0x09 /* Write ring format */
126: #define FC_RDCNTS 0x0a /* Read counters */
127: #define FC_RCCNTS 0x0b /* Read and clear counters */
128: #define FC_RDMODE 0x0c /* Read mode */
129: #define FC_WTMODE 0x0d /* Write mode */
130: #define FC_RDSTATUS 0x0e /* Read port status */
131: #define FC_RCSTATUS 0x0f /* Read and clear port status */
132: #define FC_DUMPMEM 0x10 /* Dump internal memory */
133: #define FC_LOADMEM 0x11 /* Load internal memory */
134: #define FC_RDSYSID 0x12 /* Read system ID parameters */
135: #define FC_WTSYSID 0x13 /* Write system ID parameters */
136: #define FC_RDSERAD 0x14 /* Read load server address */
137: #define FC_WTSERAD 0x15 /* Write load server address */
138:
139: /*
140: * Unibus Data Block Base (UDBB) for ring buffers
141: */
142: struct de_udbbuf {
143: short b_tdrbl; /* Transmit desc ring base low 16 bits */
144: char b_tdrbh; /* Transmit desc ring base high 2 bits */
145: char b_telen; /* Length of each transmit entry */
146: short b_trlen; /* Number of entries in the XMIT desc ring */
147: short b_rdrbl; /* Receive desc ring base low 16 bits */
148: char b_rdrbh; /* Receive desc ring base high 2 bits */
149: char b_relen; /* Length of each receive entry */
150: short b_rrlen; /* Number of entries in the RECV desc ring */
151: };
152:
153: /*
154: * Transmit/Receive Ring Entry
155: */
156: struct de_ring {
157: short r_slen; /* Segment length */
158: short r_segbl; /* Segment address (low 16 bits) */
159: char r_segbh; /* Segment address (hi 2 bits) */
160: u_char r_flags; /* Status flags */
161: u_short r_tdrerr; /* Errors */
162: #define r_lenerr r_tdrerr
163: short r_rid; /* Request ID */
164: };
165:
166: #define XFLG_OWN 0x80 /* If 0 then owned by driver */
167: #define XFLG_ERRS 0x40 /* Error summary */
168: #define XFLG_MTCH 0x20 /* Address match on xmit request */
169: #define XFLG_MORE 0x10 /* More than one entry required */
170: #define XFLG_ONE 0x08 /* One collision encountered */
171: #define XFLG_DEF 0x04 /* Transmit deferred */
172: #define XFLG_STP 0x02 /* Start of packet */
173: #define XFLG_ENP 0x01 /* End of packet */
174:
175: #define XFLG_BITS "\10\10OWN\7ERRS\6MTCH\5MORE\4ONE\3DEF\2STP\1ENP"
176:
177: #define XERR_BUFL 0x8000 /* Buffer length error */
178: #define XERR_UBTO 0x4000 /* UNIBUS tiemout
179: #define XERR_LCOL 0x1000 /* Late collision */
180: #define XERR_LCAR 0x0800 /* Loss of carrier */
181: #define XERR_RTRY 0x0400 /* Failed after 16 retries */
182: #define XERR_TDR 0x03ff /* TDR value */
183:
184: #define XERR_BITS "\20\20BUFL\17UBTO\15LCOL\14LCAR\13RTRY"
185:
186: #define RFLG_OWN 0x80 /* If 0 then owned by driver */
187: #define RFLG_ERRS 0x40 /* Error summary */
188: #define RFLG_FRAM 0x20 /* Framing error */
189: #define RFLG_OFLO 0x10 /* Message overflow */
190: #define RFLG_CRC 0x08 /* CRC error */
191: #define RFLG_STP 0x02 /* Start of packet */
192: #define RFLG_ENP 0x01 /* End of packet */
193:
194: #define RFLG_BITS "\10\10OWN\7ERRS\6FRAM\5OFLO\4CRC\2STP\1ENP"
195:
196: #define RERR_BUFL 0x8000 /* Buffer length error */
197: #define RERR_UBTO 0x4000 /* UNIBUS tiemout */
198: #define RERR_NCHN 0x2000 /* No data chaining */
199: #define RERR_MLEN 0x0fff /* Message length */
200:
201: #define RERR_BITS "\20\20BUFL\17UBTO\16NCHN"
202:
203: /* mode description bits */
204: #define MOD_HDX 0x0001 /* Half duplex mode */
205: #define MOD_LOOP 0x0004 /* Enable internal loopback */
206: #define MOD_DTCR 0x0008 /* Disables CRC generation */
207: #define MOD_DMNT 0x0200 /* Disable maintenance features */
208: #define MOD_ECT 0x0400 /* Enable collision test */
209: #define MOD_TPAD 0x1000 /* Transmit message pad enable */
210: #define MOD_DRDC 0x2000 /* Disable data chaining */
211: #define MOD_ENAL 0x4000 /* Enable all multicast */
212: #define MOD_PROM 0x8000 /* Enable promiscuous mode */
213:
214: struct de_buf {
215: struct ether_header db_head; /* header */
216: char db_data[ETHERMTU]; /* packet data */
217: int db_crc; /* CRC - on receive only */
218: };
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