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1.1 root 1: /*
2: * Copyright (c) 1982, 1986 Regents of the University of California.
3: * All rights reserved.
4: *
5: * This code is derived from software contributed to Berkeley by
6: * Excelan Inc.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: * 3. All advertising materials mentioning features or use of this software
17: * must display the following acknowledgement:
18: * This product includes software developed by the University of
19: * California, Berkeley and its contributors.
20: * 4. Neither the name of the University nor the names of its contributors
21: * may be used to endorse or promote products derived from this software
22: * without specific prior written permission.
23: *
24: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34: * SUCH DAMAGE.
35: *
36: * @(#)if_exreg.h 7.3 (Berkeley) 6/28/90
37: */
38:
39: struct exdevice {
40: char xd_porta; /* write on porta resets EXOS */
41: char xd_pad_a;
42: char xd_portb; /* write on portb interrupts EXOS */
43: /* read on portb returns status bits */
44: char xd_pad_b;
45: };
46:
47: /* EXOS I/O PORT A write definitions */
48: #define EX_RESET 0 /* value doesn't really matter... */
49:
50: /* EXOS I/O PORT B write definitions */
51: #define EX_NTRUPT 0
52:
53: /* EXOS I/O PORT B read definitions */
54: #define EX_TESTOK 1 /* set when self-diagnostics passed */
55: #define EX_UNREADY (1<<3) /* set until EXOS ready to read from B */
56:
57: /* message buffer status field definitions */
58: #define MH_OWNER 1 /* mask for status bit for owner */
59: #define MH_HOST 0 /* if 0, the host owns the buffer */
60: #define MH_EXOS 1 /* if 1, the EXOS owns the buffer */
61:
62: /* EXOS Link Level request codes */
63: #define LLTRANSMIT 0xC /* send a packet */
64: #define LLRTRANSMIT 0xE /* send a packet, and self-receive */
65: #define LLRECEIVE 0xD /* receive a packet */
66: #define LLNET_MODE 0x8 /* read/write mode control objects */
67: #define LLNET_ADDRS 0x9 /* read/write receive address slots */
68: #define LLNET_RECV 0xA /* read/alter receive slot enable bit */
69: #define LLNET_STSTCS 0xB /* read/reset network statistics objects */
70:
71: /* Link Level return codes common to all requests */
72: #define LL_OK 0 /* successful completion */
73: #define LLX_MODE 0xA1 /* EXOS not in link level mode (impossible) */
74:
75: /* LLTRANSMIT unique return codes */
76: #define LLXM_1RTRY 0x1 /* successful xmission, 1 retry */
77: #define LLXM_RTRYS 0x2 /* successful xmission, more than 1 retry */
78: #define LLXM_NSQE 0x8 /* successful xmission, no SQE TEST signal */
79: #define LLXM_CLSN 0x10 /* xmission failed, excess retries */
80: #define LLXM_NCS 0x20 /* xmission failed, no carrier sense */
81: #define LLXM_LNGTH 0x40 /* xmission failed, bad packet length */
82: #define XMIT_BITS "\7\7LENGTH\6CARRIER\5XCLSNS\4SQETST"
83: #define LLXM_ERROR (LLXM_NSQE|LLXM_CLSN|LLXM_NCS|LLXM_LNGTH)
84:
85: /* LLRECEIVE unique return codes */
86: #define LLRC_TRUNC 0x4 /* pkt received, but truncated to fit buffer */
87: #define LLRC_ALIGN 0x10 /* pkt received, but with alignment error */
88: #define LLRC_CRC 0x20 /* pkt received, but with CRC error */
89: #define LLRC_BUFLEN 0x40 /* no pkt received, buffer less than 64 bytes */
90: /* this should never happen here */
91: #define RECV_BITS "\7\7BUFLEN\6CRC\5ALIGN\3TRUNC"
92:
93: /* LLNET_ADDRS unique return codes */
94: #define LLNA_BADSLOT 0xD1 /* slot doesn't exist or can't be accessed */
95: #define LLNA_BADADDR 0xD3 /* invalid address for designated slot */
96:
97: /* LLNET_RECV unique return codes */
98: #define LLNR_BADSLOT 0xD1 /* slot doesn't exist or can't be accessed */
99: #define LLNR_BADADDR 0xD2 /* designated slot was empty */
100:
101: /* address slot object indices */
102: #define NULLSLOT 0 /* the null slot */
103: #define MINMCSLOT 1 /* minimum multicast slot index */
104: #define MAXMCSLOT 8 /* default maximum multicast slot index */
105: #define PHYSSLOT 253 /* physical slot index */
106: #define UNVRSSLOT 254 /* universal slot index */
107: #define BROADSLOT 255 /* broadcast slot index */
108:
109: /* request mask bit definitions */
110: #define WRITE_OBJ 1 /* write the object */
111: #define READ_OBJ 2 /* read the object */
112: #define ENABLE_RCV 4 /* enable reception on designated slot */
113:
114: /* NET_MODE options mask bit definitions */
115: #define OPT_ALIGN 0x10 /* receive packets with alignment errors */
116: #define OPT_CRC 0x20 /* receive packets with CRC errors */
117: #define OPT_DSABLE 0x80 /* disconnect controller hardware */
118:
119: /* NET_MODE mode field value definitions */
120: #define MODE_OFF 0 /* stop transmission and reception */
121: #define MODE_PERF 1 /* perfect multicast address filtering */
122: #define MODE_HW 2 /* hardware-only multicast address filtering */
123: #define MODE_PROM 3 /* promiscuous reception */
124:
125: #define NFRAGMENTS 1 /* number fragments that the EXOS will scatter/gather */
126: #define EXMAXRBUF 1520 /* per EXOS 101 manual 5.3.7 (maybe 1518 would do) */
127:
128: /*
129: * N.B. Structures below are carefully constructed so that
130: * they correspond to the message formats that NX firmware
131: * defines. None of them should contain any compiler-instigated
132: * padding. Be especially careful about VAX C longword alignment!
133: */
134:
135: struct stat_array {
136: u_long sa_fsent; /* frames sent without errors */
137: u_long sa_xsclsn; /* frames aborted excess collisions */
138: u_long sa_nsqe; /* frames subject to heartbeat failure */
139: u_long sa_undef; /* undefined (TDR on EXOS 101) */
140: u_long sa_frcvd; /* frames received no errors */
141: u_long sa_align; /* frames received alignment error */
142: u_long sa_crc; /* frames received crc error */
143: u_long sa_flost; /* frames lost */
144: };
145:
146: struct buf_blk { /* packet/buffer block descriptor */
147: u_short bb_len; /* length of block, in bytes */
148: u_short bb_addr[2]; /* address of block */
149: /*
150: * Array above is really a single u_long field.
151: * We kludge its definition to defeat word-alignment.
152: * Access would look like:
153: * longaddr = *(u_long *)bp->.mb_er.er_blks[0].bb_addr;
154: */
155: };
156:
157: struct net_mode { /* read/write mode control objects */
158: /*12*/ u_char nm_rqst; /* request code */
159: /*13*/ u_char nm_rply; /* reply code */
160: /*14*/ u_char nm_mask; /* bit-wise switches for read, write */
161: /*15*/ u_char nm_optn; /* acceptable packet reception errors */
162: /*16*/ u_char nm_mode; /* EXOS filtering mode */
163: /*17*/
164: };
165:
166: struct net_addrs { /* read/write receive address slots */
167: /*12*/ u_char na_rqst; /* request code */
168: /*13*/ u_char na_rply; /* reply code */
169: /*14*/ u_char na_mask; /* bit-wise switches for read, write */
170: /*15*/ u_char na_slot; /* index of address slot */
171: /*16*/ u_char na_addrs[6]; /* address read and/or written */
172: /*22*/
173: };
174:
175: struct net_recv { /* read/alter receive slot enable bit */
176: /*12*/ u_char nr_rqst; /* request code */
177: /*13*/ u_char nr_rply; /* reply code */
178: /*14*/ u_char nr_mask; /* bit-wise switches for read, write */
179: /*15*/ u_char nr_slot; /* index of address slot */
180: /*16*/
181: };
182:
183: struct net_ststcs { /* read/reset network statistics objects */
184: /*12*/ u_char ns_rqst; /* request code */
185: /*13*/ u_char ns_rply; /* reply code */
186: /*14*/ u_char ns_mask; /* bit-wise switches for read, write */
187: /*15*/ u_char ns_rsrv; /* reserved for EXOS */
188: /*16*/ u_short ns_nobj; /* number of objects to work on */
189: /*18*/ u_short ns_xobj; /* index of first object to work on */
190: /*20*/ u_long ns_bufp; /* pointer to statistics buffer */
191: /*24*/
192: };
193:
194: struct enet_xmit { /* send a packet on the Ethernet */
195: /*12*/ u_char et_rqst; /* request code */
196: /*13*/ u_char et_rply; /* reply code */
197: /*14*/ u_char et_slot; /* address slot matching dest address */
198: /*15*/ u_char et_nblock; /* number of blocks composing packet */
199: /*16*/ struct buf_blk et_blks[NFRAGMENTS]; /* array of block descriptors */
200: /*22-64*/
201: };
202:
203: struct enet_recv { /* receive a packet on the Ethernet */
204: /*12*/ u_char er_rqst; /* request code */
205: /*13*/ u_char er_rply; /* reply code */
206: /*14*/ u_char er_slot; /* address slot matching dest address */
207: /*15*/ u_char er_nblock; /* number of blocks composing buffer */
208: /*16*/ struct buf_blk er_blks[NFRAGMENTS]; /* array of block descriptors */
209: /*22-64*/
210: };
211:
212: /* we send requests and receive replys with the EXOS using this structure */
213: struct ex_msg {
214: /*00*/ u_short mb_link; /* address of next message buffer */
215: /*02*/ u_char mb_rsrv; /* reserved for use by EXOS */
216: /*03*/ u_char mb_status; /* used bit-wise for message protocol */
217: /*04*/ u_short mb_length; /* length, in bytes, of the rest */
218: /*06*/ short mb_1rsrv; /* reserved for used by EXOS */
219: /*08*/ long mb_mid; /* available to user */
220: /*12*/ union mb_all {
221: struct net_mode mb_net_mode;
222: struct net_addrs mb_net_addrs;
223: struct net_recv mb_net_recv;
224: struct net_ststcs mb_net_ststcs;
225: struct enet_xmit mb_enet_xmit;
226: struct enet_recv mb_enet_recv;
227: } mb_all;
228: /* following field is used only by host, not read by board */
229: struct ex_msg *mb_next; /* host's pointer to next message */
230: };
231: #define mb_nm mb_all.mb_net_mode
232: #define mb_na mb_all.mb_net_addrs
233: #define mb_nr mb_all.mb_net_recv
234: #define mb_ns mb_all.mb_net_ststcs
235: #define mb_et mb_all.mb_enet_xmit
236: #define mb_er mb_all.mb_enet_recv
237: #define mb_rqst mb_nm.nm_rqst
238: #define mb_rply mb_nm.nm_rply
239: #define MBDATALEN (sizeof(union mb_all)+6)
240:
241: struct confmsg {
242: /*00*/ u_short cm_1rsrv; /* reserved, must be 1 */
243: /*02*/ char cm_vc[4]; /* returns ASCII version code */
244: /*06*/ u_char cm_cc; /* returns config completion code */
245: /*07*/ u_char cm_opmode; /* specifies operation mode */
246: /*08*/ u_short cm_dfo; /* specifies host data format option */
247: /*10*/ u_char cm_dcn1; /* reserved, must be 1 */
248: /*11*/ u_char cm_2rsrv[2]; /* reserved, must be 0 */
249: /*13*/ u_char cm_ham; /* specifies host address mode */
250: /*14*/ u_char cm_3rsrv; /* reserved, must be 0 */
251: /*15*/ u_char cm_mapsiz; /* reserved, must be 0 */
252: /*16*/ u_char cm_byteptrn[4]; /* host data format option test pattern */
253: /*20*/ u_short cm_wordptrn[2];
254: /*24*/ u_long cm_lwordptrn;
255: /*28*/ u_char cm_rsrvd[20];
256: /*48*/ u_long cm_mba; /* use 0xFFFFFFFF in link level mode */
257: /*52*/ u_char cm_nproc; /* use 0xFF in link level mode */
258: /*53*/ u_char cm_nmbox; /* use 0xFF in link level mode */
259: /*54*/ u_char cm_nmcast; /* use 0xFF in link level mode */
260: /*55*/ u_char cm_nhost; /* use 1 in link level mode */
261:
262: /* the next five parameters define the request message queue */
263: /*56*/ u_long cm_h2xba; /* base address of message queue */
264: /*60*/ u_short cm_h2xhdr; /* address offset of msg Q header */
265: /*62*/ u_char cm_h2xtyp; /* interrupt type */
266: /*63*/ u_char cm_h2xval; /* interrupt value (not used) */
267: /*64*/ u_short cm_h2xaddr; /* interrupt vector */
268: /*66*/ u_short cm_h2xpad; /* pad out unused portion of vector */
269:
270: /* the next five parameters define the reply message queue */
271: /*68*/ u_long cm_x2hba; /* base address of message queue */
272: /*72*/ u_short cm_x2hhdr; /* address offset of msg Q header */
273: /*74*/ u_char cm_x2htyp; /* interrupt type */
274: /*75*/ u_char cm_x2hval; /* interrupt value (not used) */
275: /*76*/ u_short cm_x2haddr; /* interrupt vector */
276: /*78*/ u_short cm_x2hpad; /* pad out unused portion of vector */
277: /*80*/
278: };
279:
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