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1.1 root 1: /*-
2: * Copyright (c) 1986 MICOM-Interlan, Inc., Boxborough Mass
3: * Copyright (c) 1991 The Regents of the University of California.
4: * All rights reserved.
5: *
6: * Redistribution and use in source and binary forms, with or without
7: * modification, are permitted provided that the following conditions
8: * are met:
9: * 1. Redistributions of source code must retain the above copyright
10: * notice, this list of conditions and the following disclaimer.
11: * 2. Redistributions in binary form must reproduce the above copyright
12: * notice, this list of conditions and the following disclaimer in the
13: * documentation and/or other materials provided with the distribution.
14: * 3. All advertising materials mentioning features or use of this software
15: * must display the following acknowledgement:
16: * This product includes software developed by the University of
17: * California, Berkeley and its contributors.
18: * 4. Neither the name of the University nor the names of its contributors
19: * may be used to endorse or promote products derived from this software
20: * without specific prior written permission.
21: *
22: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32: * SUCH DAMAGE.
33: *
34: * @(#)npreg.h 7.4 (Berkeley) 5/9/91
35: */
36:
37: /*
38: * Merged header file for MICOM-Interlan NP100.
39: */
40:
41: /*
42: * np100.h version 1.3
43: *
44: * This version retrieved: 8/18/86 @ 18:58:44
45: * This delta created: 8/18/86 @ 18:27:32
46: */
47: /*
48: * Typedefs for the VAX
49: */
50:
51: typedef short sign16; /* 16 bit signed value */
52: typedef unsigned short unsign16; /* 16 bit unsigned value */
53: typedef unsigned unsign32; /* 32 bit unsigned value */
54: typedef long paddr_t; /* Physical addresses */
55:
56:
57: /*
58: * Tunables
59: */
60:
61:
62: #define NUMCQE 40 /* Number of CQE's per board */
63:
64: /* Host configuration word in Status Block */
65:
66: /*
67: * To disable the lock/unlock internal function calls clear the 0x8000
68: * bit in the host configuration word (HOSTCONF)
69: */
70:
71: #define HOSTCONF 0x0109 /* See above */
72: #define LOWBYTE 1
73: #define HIGHBYTE 0
74: #define BUFFMAPPED 0
75:
76: /*
77: * Memory mapping definintions for PM68DUAL hardware.
78: */
79:
80: #ifdef PM68DUAL
81: #define PISHMEM 0x200000
82: #define PISHMEMSIZE 2
83: #define PIOFF 0x8000 /* change this to unique mem add. */
84: #define PIWINDOW MBUSBUFR + PIOFF
85: #define WINDOWSIZE 2
86: #endif
87: #define NPMAXXFR 32768 /* Maximum number of bytes / read */
88:
89: /*
90: * Define the protocols supported by the NP Driver.
91: */
92:
93: #define NONE 0x00 /* No protocols active for a process */
94: #define NPMAINT 0x01 /* Maintenance protocol, superusers only */
95: #define NPNTS 0x02 /* NTS Terminal Server */
96: #define NPIDP 0x04 /* Direct Datalink Access */
97: #define NPDLA 0x04 /* Direct Datalink Access */
98: #define NPXNS 0x06 /* Xerox NS ITP */
99: #define NPTCP 0x08 /* TCP/IP */
100: #define NPISO 0x0A /* ISO */
101: #define NPCLCONN 0xFF /* Closed connection, i.e. no protocol */
102:
103: /*
104: * Convert the protocol to a value used in the Device Protocol Mask field
105: * of the Shared Memory Status Block.
106: */
107:
108: #define PROTOMASK(x) ( 1 << (x) )
109:
110: /*
111: * Special requests handled by the NP Driver
112: */
113:
114: #define OS_STP 03400 /* Shut down connection on I Board */
115: #define NPSTOP 3 /* Conversion from above (OS_STP) */
116: #define NPCHNGP 50 /* Change the protocol on a connection */
117: #define NPCHNGB 51 /* Change the Board number */
118:
119: /*
120: * Miscellaneous
121: */
122:
123: #define ON 0x8000 /* Used for Command Q's scan and change flag */
124: #define UBADDRMASK 0x3FFFF /* 18 bit UNIBUS address */
125: #define INTMASK 0xFFFFFFFC /* Used for address validation */
126: #define CMDMASK 0xFFFF /* Mask ioctl cmd field (see ioctl.h) */
127: #define NPPSADDR 0x324 /* Pointer to addr of on-board panic string */
128: #define PANLEN 133 /* length of the panic buffer */
129:
130: /*
131: * Map function code from user to I-Board format
132: */
133:
134: #define FUNCTMAP(x) (((x) << 6) | 077) /* Maps user function to NP funcs */
135:
136: /*
137: * Round up to a 16 byte boundary
138: */
139:
140: #define ROUND16(x) (((x) + 15) & (~0x0F)) /* Round to 16 byte boundary */
141: #define ADDR24 1 /* Used by iomalloc() to specify 24 bit address */
142:
143: #define NPERRSHIFT 8 /* Used in function ReqDone() */
144: #define NPOK 0
145:
146: #define LOWORD(X) (((ushort *)&(X))[0])
147: #define HIWORD(X) (((ushort *)&(X))[1])
148:
149: /* Everyday flag settings */
150:
151: #define NPSET 1
152: #define NPCLEAR 0
153:
154: /*
155: * Command Queue Elements are the primary data structure for passing data
156: * between the driver and the device.
157: */
158:
159: struct CQE {
160:
161: struct npreq *cqe_reqid;/* Address of asssociated npreq */
162: union {
163: unsign32 cqe_Famid; /* Family ID (Process ID) - wn */
164: unsign16 cqe_PrtSig[2]; /* port and signal - tn */
165: } u1;
166: #define cqe_famid u1.cqe_Famid
167: #define cqe_port u1.cqe_PrtSig[0]
168: #define cqe_signal u1.cqe_PrtSig[1]
169: unsign16 cqe_func; /* I/O function to be performed */
170: #ifdef mc68000
171: char cqe_prot; /* Protocol type for I/O request */
172: char cqe_lenrpb; /* Length of the RPB in bytes */
173: #else
174: char cqe_lenrpb; /* Length of the RPB in bytes */
175: char cqe_prot; /* Protocol type for I/O request */
176: #endif
177: union {
178: unsign16 cqe_ustS[2]; /* Protocol status return */
179: unsign32 cqe_ustL; /* Protocol status return */
180: } u2;
181: #define cqe_ust0 u2.cqe_ustS[0]
182: #define cqe_ust1 u2.cqe_ustS[1]
183: #define cqe_usts u2.cqe_ustL
184: unsign16 cqe_devrsv; /* Reserved for use by device only! */
185: #ifdef mc68000
186: char cqe_char; /* CQE characteristics */
187: char cqe_sts; /* Status return from device to user */
188: char cqe_wind; /* Buffer mapping window size (page units) */
189: char cqe_nbuf; /* Number of data buffers for I/O */
190: #else
191: char cqe_sts; /* Status return from device to user */
192: char cqe_char; /* CQE characteristics */
193: char cqe_nbuf; /* Number of data buffers for I/O */
194: char cqe_wind; /* Buffer mapping window size (page units) */
195: #endif
196: unsign16 cqe_bcnt; /* Total number of bytes in the data buffer */
197: union {
198: unsign16 cqe_Unused; /* Unused */
199: struct {
200: char cqe_Maxbcnt; /* Maximum size of buffer */
201: char cqe_Bflags; /* Used by the SPI */
202: } s;
203: } u3;
204: #define cqe_unused u3.cqe_Unused
205: #define cqe_maxbcnt u3.s.cqe_Maxbcnt
206: #define cqe_bflags u3.s.cqe_Bflags
207: unsign16 cqe_dma[2]; /* Address of the MULTIBUS data buffer */
208: unsign16 rpb1; /* Word 1 of protocol parameters */
209: unsign16 rpb2; /* Word 2 of protocol parameters */
210: unsign16 rpb3; /* Word 3 of protocol parameters */
211: unsign16 rpb4; /* Word 4 of protocol parameters */
212: unsign16 rpb5; /* Word 5 of protocol parameters */
213: unsign16 rpb6; /* Word 6 of protocol parameters */
214: unsign16 rpb7; /* Word 7 of protocol parameters */
215: unsign16 rpb8; /* Word 8 of protocol parameters */
216: unsign16 rpb9; /* Word 9 of protocol parameters */
217: unsign16 rpb10; /* Word 10 of protocol parameters */
218: unsign16 rpb11; /* Word 11 of protocol parameters */
219: unsign16 rpb12; /* Word 12 of protocol parameters */
220:
221: };
222:
223: /*
224: * NP Driver Request structure contains information about a request
225: * maintained solely by the driver. One per CQE, plus a header.
226: */
227:
228: struct npreq {
229:
230: struct npreq *forw; /* Forward pointer for active list */
231: struct npreq *back; /* Backward pointer for active list */
232: struct npreq *free; /* Next member on free list */
233: struct CQE *element; /* CQE associated with this request */
234: int flags; /* Always useful */
235: int reqcnt; /* Request count for reqtab */
236: int bufoffset; /* Offset into buffer for turns */
237: int bytecnt; /* Number of bytes to transfer */
238: caddr_t virtmem; /* Virtual address of buffer */
239: int mapbase; /* Address of the mapping register */
240: int mapsize; /* Size of mapped area */
241: caddr_t bufaddr; /* Address of the user buffer */
242: struct buf buf; /* Buf structure needed for mem. mgmt */
243: struct proc *procp; /* Pointer to process of requestor */
244: caddr_t user; /* Structure passed by user from itpuser.h */
245: int (*intr)(); /* Ptr to routine to call at interrupt time */
246: int int_param; /* Paramater to be used by above routine */
247: };
248:
249: /*
250: * Npmaster structure, one per device, is used for boardwise centralization
251: * of relevant information including queues, I/O addresses and request pools.
252: */
253:
254: struct npmaster {
255:
256: struct npmaster *next; /* Linked list of these, NULL terminator */
257: struct npspace *shmemp; /* Shared memory address (driver <-> device) */
258: struct uba_device *devp; /* UBA Device for this unit */
259: struct NPREG *iobase; /* I/O base address for this board */
260: struct npreq *reqtab; /* Header for pool of CQE requests */
261: int iomapbase; /* Base index of I/O map reg's allocated */
262: int flags; /* State of the Board */
263: int unit; /* Unit number of this device */
264: int vector; /* Interrupt vector for this unit */
265: };
266:
267: struct NPREG {
268: unsign16 CSR0; /* Control Status Register 0 */
269: unsign16 CSR1; /* Control Status Register 1 */
270: unsign16 CSR2; /* Control Status Register 2 */
271: unsign16 CSR3; /* Control Status Register 3 */
272:
273: };
274:
275: /*
276: * The following structures are used for communicating with the
277: * Intelligent Board and are located in Shared Memory.
278: */
279:
280: /*
281: * Status Block
282: */
283:
284: struct NpStat{
285:
286: unsign16 sb_drw; /* Device Request Word */
287: unsign16 sb_hcw; /* Host Configuration Word */
288: unsign16 sb_dcw; /* Device Configuration Word */
289: unsign16 sb_dpm; /* Device Protocol Mask */
290: unsign16 sb_dcq; /* Offset to Device CQ */
291: unsign16 sb_hcq; /* Offset to Host CQ */
292: };
293:
294: /*
295: * Command Queue, two per device. One is owned by the driver and the other
296: * is owned by the device.
297: */
298:
299: struct CmdQue {
300:
301: unsign16 scanflag; /* Scan Flag, MSB set if being scanned */
302: unsign16 chngflag; /* Change Flag, MSB set by initiator */
303: unsign16 cq_wrap; /* Offset to last CQE entry +2 */
304: unsign16 cq_add; /* Offset to add a CQE to the queue */
305: unsign16 cq_rem; /* Offset to remove a CQE from the queue */
306: unsign16 cq_cqe[NUMCQE]; /* Command Queue Element Offsets */
307: };
308:
309: /*
310: * Structure of the shared memory area per board. Declared this way to avoid
311: * compiler word alignment vagaries when computing offsets.
312: */
313:
314: struct npspace {
315:
316: struct NpStat statblock; /* Status Block */
317: struct CmdQue devcq; /* Device's Command Queue */
318: struct CmdQue hostcq; /* Host's Command Queue */
319: struct CQE elements[NUMCQE]; /* Shared Command Queue Elements */
320: unsign16 filler[8]; /* Here for 16 byte alignment */
321: };
322:
323: /*
324: * Structure of array of base addresses of I-Board controllers
325: * (See global data definitions in np.c)
326: */
327:
328: struct npbase {
329: caddr_t baseaddr;
330: };
331:
332: /* State of the NP Driver as kept in NpState */
333:
334: #define ICPAVAIL 0x01 /* ICP is waiting for a request */
335:
336: /* Tells ICP Process that there are no more requests for this board */
337:
338: #define BRDDONE 1
339:
340: /* Flags used by the driver (npreq structure) to monitor status of requests */
341:
342: #define REQDONE 0x01 /* Request completed */
343: #define IOIFC 0x02 /* Internal Function Code Request */
344: #define IOERR 0x04 /* Error on Request */
345: #define NPPEND 0x08 /* Unused at this time */
346: #define IOABORT 0x10 /* Request aborted by ICP */
347: #define KERNREQ 0x20 /* Request was from the kernel */
348: #define WANTREQ 0x40 /* Process is waiting for a npreq structure */
349: #define NPUIO 0x80 /* Process doing physio */
350: #define REQALOC 0x100 /* Request has been allocated */
351: #define REQUSE 0x200 /* Request is in request queue */
352:
353: /* Service Request Commands from the Intelligent Board */
354:
355: #define NOREQ 0x00 /* No service requested */
356: #define NPLOAD 0x01 /* Dump request */
357: #define NPDUMP 0x02 /* Load request */
358: #define NPPANIC 0x100 /* Panic request */
359:
360: /* Definitions of Status returned from the I-Board */
361:
362: #define NPDONE 0x01 /* Normal completion */
363: #define NPIFC 0x00 /* Internal Function Code request */
364: #define NPPERR 0x80 /* Protocol error */
365: #define NPMERR 0x82 /* Memory allocation failure on I-Board */
366:
367: /* Definitions of IFC type requests from I-Board */
368:
369: #define NPLOCK 0x64 /* Lock the process's data area */
370: #define NPUNLOCK 0xA4 /* Unlock the process */
371: #define NPREMAP 0x124 /* Window turn */
372:
373: /* Definition of flags for the Npmaster structure */
374:
375: #define CSRPEND 0x01 /* CSR0 command pending */
376: #define PANICREQ 0x02 /* Panic request */
377: #define DUMPREQ 0x04 /* Dump request */
378: #define LOADREQ 0x08 /* Load request */
379: #define BOARDREQ 0x10 /* Any request by the board */
380: #define BADBOARD 0x20 /* Board disabled */
381: #define AVAILABLE 0x40 /* Board available */
382: #define BRDRESET 0x80 /* Board is being reset */
383: #define PANIC1 0x100 /* Driver wants panic address */
384: #define PANIC2 0x200 /* Driver wants panic string */
385: #define PANIC3 0x400 /* Clear first byte of panic string */
386: #define LSTCMD 0x800 /* Clear last command during NPIO */
387: #define SCANNING 0x1000 /* We are scanning for cqe's */
388:
389: /*
390: * Debugging Constants
391: */
392:
393: #define DEBENTRY 0x0001 /* debug entry points */
394: #define DEBMEM 0x0002 /* debug memory */
395: #define DEBREQ 0x0004 /* debug requests */
396: #define DEBCQE 0x0008 /* debug cqe's */
397: #define DEBCQ 0x0010 /* debug cq's */
398: #define DEBMAINT 0x0020 /* debug maintainance requests */
399: #define DEBINTR 0x0040 /* debug interrupt routines */
400: #define DEBINIT 0x0080 /* debug initialization routines */
401: #define DEBIFC 0x0100 /* debug Internal function codes */
402: #define DEBIOCTL 0x0200 /* debug ioctl calls */
403: #define DEBOPEN 0x0400 /* debug open calls */
404: #define DEBIO 0x0800 /* debug read & write calls */
405: #define DEBCSR 0x1000 /* debug CSR commands */
406: #define DEBLOCK 0x2000 /* debug lock / unlock calls */
407: #define NOBOARD 0x4000 /* debug user/host interface */
408: #define DEBCANCEL 0x8000 /* debug cancel command */
409:
410: /*
411: * npreg.h version 1.3
412: *
413: * This version retrieved: 8/18/86 @ 18:58:46
414: * This delta created: 8/18/86 @ 18:27:42
415: */
416:
417: /*
418: * NPREG.H
419: *
420: * This file contain definitions of specific hardware interest
421: * to be used when communicating with the NI1510 Network Processor
422: * Board. More complete information can be found in the NI1510
423: * Multibus compatible Ethernet Communications Processor Hardware
424: * Specification.
425: */
426:
427: /*
428: * npcmd.h version 1.3
429: *
430: * This version retrieved: 8/18/86 @ 18:58:45
431: * This delta created: 8/18/86 @ 18:27:38
432: */
433: #ifdef KERNEL
434: # define IoVOID 0
435: #else
436: # define IoVOID IOC_VOID
437: #endif
438:
439: #define NPRESET (IoVOID|0x01) /* reset the board */
440: #define NPSTART (IoVOID|0x04) /* start board execution */
441: #define NPGPANIC (IoVOID|0x05) /* Get panic message */
442: #define NPINIT (IoVOID|0x06) /* initialize software on board */
443: #define NPSTATS (IoVOID|0x07)
444: #define NPRCSR0 (IoVOID|0x08) /* read CSR0 */
445: #define NPRCSR1 (IoVOID|0x09) /* read CSR1 */
446: #define NPRCSR2 (IoVOID|0x0a) /* read CSR2 */
447: #define NPRCSR3 (IoVOID|0x0b) /* read CSR3 */
448: #define NPWCSR0 (IoVOID|0x0c) /* write CSR0 */
449: #define NPWCSR1 (IoVOID|0x0d) /* write CSR1 */
450: #define NPWCSR2 (IoVOID|0x0e) /* write CSR2 */
451: #define NPWCSR3 (IoVOID|0x0f) /* write CSR3 */
452: #define NPPOLL (IoVOID|0x10)
453: #define NPKILL (IoVOID|0x11)
454: #define NPSETPROT (IoVOID|0x12) /* set the protocol to use */
455: #define NPSETBOARD (IoVOID|0x13) /* set board to use */
456: #define NPSETNPDEB (IoVOID|0x14) /* set nc debuging level */
457: #define NPSETADDR (IoVOID|0x15) /* set host address */
458: #define NPNETBOOT (IoVOID|0x16) /* boot from the network */
459: #define NPSETLAST (IoVOID|0x17) /* set last command flag in NPIO */
460: #define NPCLRICNT (IoVOID|0x18) /* clear interupt count */
461: #define NPGETICNT (IoVOID|0x19) /* get interupt count */
462: #define NPGETIVEC (IoVOID|0x1a) /* get interupt vector */
463: #define NPMAPMEM (IoVOID|0x1b) /* map user memory to shmem */
464:
465: #define NP_SET 1031 /* set memory mapping */
466: #define NP_USET 1032 /* unset memory mapping */
467:
468: struct np_mem {
469: long mem_type;
470: char *mem_addr;
471: long mem_count;
472: } ;
473:
474: #define NNPCNN 4 /* Number of connections per board */
475: #define NPUNIT(a) ((minor(a) >> 4) & 0x0F)
476: #define NPCONN(a) ((minor(a)) & 0x03)
477:
478: #define TRUE 1
479: #define FALSE 0
480:
481: #define IBOOTADDR 0xF8000l /* Addr of 80186 Boot ROM */
482: #define INETBOOT 0xF8087l
483: #define IXEQADDR 0x400 /* Where to begin Board image XEQ */
484: #define DIAGTIME 1200 /* Time for timeout /HZ seconds */
485:
486: #define DELAYTIME 1000000L /* delay count */
487: #define NPDELAY(N) {register int n = (N) >> 1; while(--n > 0); }
488:
489: /* Handy macros for talking to the Board */
490:
491: #define RESET(x) (WCSR3(x->iobase,0xff))
492: #define CLEARINT(x) {unsign16 y; y = RCSR2(x->iobase); }
493: #define INTNI(x) (WCSR1(x->iobase,0xFF))
494:
495: /* Command and Status Register (CSR) Definitions */
496:
497: /*
498: * CSR0 is the only direct means for data transfer between the host processor
499: * and the 3510. Access is controlled by the 80186 who sets the CSR1 Enable and
500: * Ready bits to allow writing here. Writing to this register will always
501: * result in an interrupt to the 80186.
502: */
503:
504: /*
505: * Bit definitions for CSR1.
506: */
507:
508: #define NPRFU 0x01 /* Reserved for Future Use */
509: #define NPHOK 0x02 /* Hardware OK */
510: #define NPLAN 0x04 /* Logic 0 indicates operational LAN exists */
511: #define NP_IP 0x08 /* Interrupt pending from this board */
512: #define NP_IE 0x10 /* Interrupts enabled for this board */
513: #define NPRDR 0x20 /* Set when 80186 writes data into CSR0 */
514: #define NPRDY 0x40 /* CSR0 ready to accept data */
515: #define NPENB 0x80 /* CSR0 available for use by the host */
516:
517: /*
518: * Bit defintions for CSR0 Command Block
519: */
520:
521: #define NPLST 0x20 /* Last Command */
522: #define NPCMD 0x80 /* Shared Memory Address */
523: #define NPBGN 0x200 /* Begin Execution in On-Board Memory */
524: #define NPCBI 0x800 /* Interrupt at completion of Command Block */
525: #define NPDMP 0x2000 /* Dump 80186 On-Board Memory to Multibus */
526: #define NPLD 0x8000 /* Load 80186 On-board Memory from Multibus */
527:
528: /*
529: * CSR0 Count definitions. These are the lengths of the Command Blocks for the
530: * CSR0 commands above (not counting the Command Word itself).
531: */
532:
533: #define LSTCNT 0
534: #define CMDCNT 2
535: #define BGNCNT 2
536: #define CBICNT 1
537: #define DMPCNT 5
538: #define LDCNT 5
539: #define IOCNT 5
540:
541: /* Macros for reading and writing CSR's (Control and Status Registers) */
542:
543: #define WCSR0(x,y) ((x)->CSR0 = y)
544: #define WCSR1(x,y) ((x)->CSR1 = y)
545: #define WCSR2(x,y) ((x)->CSR2 = y)
546: #define WCSR3(x,y) ((x)->CSR3 = y)
547:
548: #define RCSR0(x) ((x)->CSR0)
549: #define RCSR1(x) ((x)->CSR1)
550: #define RCSR2(x) ((x)->CSR2)
551: #define RCSR3(x) ((x)->CSR3)
552:
553: struct npconn {
554:
555: struct npmaster *unit; /* Unit number (board) of this connection */
556: unsign16 protocol; /* Protocol used on this connection */
557: struct buf np_wbuf; /* write buf structure for raw access */
558: struct buf np_rbuf; /* read buf structure for raw access */
559: };
560:
561: /* ICP Board Requests */
562:
563: #define ICPLOAD 0x02
564: #define ICPDUMP 0x03
565: #define ICPPANIC 0x05
566: #define ICPPOLL 0x10
567:
568: /*
569: * npdebug.h version 1.3
570: *
571: * This version retrieved: 8/18/86 @ 18:58:46
572: * This delta created: 8/18/86 @ 18:27:39
573: */
574:
575: /*
576: * Debugging Constants
577: */
578:
579: #define DEBENTRY 0x0001 /* debug entry points */
580: #define DEBMEM 0x0002 /* debug memory */
581: #define DEBREQ 0x0004 /* debug requests */
582: #define DEBCQE 0x0008 /* debug cqe's */
583: #define DEBCQ 0x0010 /* debug cq's */
584: #define DEBMAINT 0x0020 /* debug maintainance requests */
585: #define DEBINTR 0x0040 /* debug interrupt routines */
586: #define DEBINIT 0x0080 /* debug initialization routines */
587: #define DEBIFC 0x0100 /* debug Internal function codes */
588: #define DEBIOCTL 0x0200 /* debug ioctl calls */
589: #define DEBOPEN 0x0400 /* debug open calls */
590: #define DEBIO 0x0800 /* debug read & write calls */
591: #define DEBCSR 0x1000 /* debug CSR commands */
592: #define DEBLOCK 0x2000 /* debug lock / unlock calls */
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