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Annotation of Net2/arch/vax/uba/psreg.h, revision 1.1

1.1     ! root        1: /*-
        !             2:  * Copyright (c) 1982, 1986 The Regents of the University of California.
        !             3:  * All rights reserved.
        !             4:  *
        !             5:  * Redistribution and use in source and binary forms, with or without
        !             6:  * modification, are permitted provided that the following conditions
        !             7:  * are met:
        !             8:  * 1. Redistributions of source code must retain the above copyright
        !             9:  *    notice, this list of conditions and the following disclaimer.
        !            10:  * 2. Redistributions in binary form must reproduce the above copyright
        !            11:  *    notice, this list of conditions and the following disclaimer in the
        !            12:  *    documentation and/or other materials provided with the distribution.
        !            13:  * 3. All advertising materials mentioning features or use of this software
        !            14:  *    must display the following acknowledgement:
        !            15:  *     This product includes software developed by the University of
        !            16:  *     California, Berkeley and its contributors.
        !            17:  * 4. Neither the name of the University nor the names of its contributors
        !            18:  *    may be used to endorse or promote products derived from this software
        !            19:  *    without specific prior written permission.
        !            20:  *
        !            21:  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
        !            22:  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
        !            23:  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
        !            24:  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
        !            25:  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
        !            26:  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
        !            27:  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
        !            28:  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
        !            29:  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
        !            30:  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
        !            31:  * SUCH DAMAGE.
        !            32:  *
        !            33:  *     @(#)psreg.h     7.3 (Berkeley) 5/9/91
        !            34:  */
        !            35: 
        !            36: 
        !            37: /*
        !            38:  *     The Real Nitty Gritty Device Registers
        !            39:  */
        !            40: 
        !            41: struct psdevice {
        !            42:        short int ps_data;              /* data register */
        !            43:        short int ps_addr;              /* address register */
        !            44:        short int ps_wcount;            /* word count register */
        !            45:        short int ps_busaddr;           /* unibus address register */
        !            46:        short int ps_iostat;            /* io status register */
        !            47: };
        !            48: 
        !            49: /*
        !            50:  *     Possible ioctl's
        !            51:  */
        !            52: #define PSIOAUTOREFRESH                _IO('p', 0)             /* auto refresh */
        !            53: #define PSIOSINGLEREFRESH      _IO('p', 1)             /* single refresh */
        !            54: #define PSIOAUTOMAP            _IO('p', 2)             /* auto map */
        !            55: #define PSIOSINGLEMAP          _IO('p', 3)             /* single map */
        !            56: #define PSIODOUBLEBUFFER       _IO('p', 4)             /* double buffer */
        !            57: #define PSIOSINGLEBUFFER       _IO('p', 5)             /* single buffer */
        !            58: #define PSIOWAITREFRESH                _IO('p', 6)             /* await refresh */
        !            59: #define PSIOWAITMAP            _IO('p', 7)             /* await map */
        !            60: #define PSIOWAITHIT            _IO('p', 8)             /* await hit */
        !            61: #define PSIOSTOPREFRESH                _IO('p', 9)             /* stop refresh */
        !            62: #define PSIOSTOPMAP            _IO('p',10)             /* stop map */
        !            63: #define PSIOGETADDR            _IOR('p',11, int)       /* get Unibus address */
        !            64: #define PSIOTIMEREFRESH                _IO('p',12)             /* time refresh */
        !            65: 
        !            66: /*
        !            67:  *     Picture system io status register bits
        !            68:  */
        !            69: 
        !            70: #define DIOREADY       0100000
        !            71: #define PSAHOLD                040000
        !            72: #define PSRESET                020000
        !            73: #define DIORESET       010000
        !            74: #define DMARESET       04000
        !            75: #define PSIE           0400
        !            76: #define DMAREADY       0200
        !            77: #define DMAIE          0100
        !            78: #define PASSIVE                010
        !            79: #define DMAIN          04
        !            80: #define NEXEM          02
        !            81: #define GO             01
        !            82: 
        !            83: /*
        !            84:  *     Picture system memory mapping control registers: SCB 0177400-0177410
        !            85:  */
        !            86: 
        !            87: #define EXMMR_DMA      0177400
        !            88: #define EXMMR_DIO      0177404
        !            89: #define EXMMR_RC       0177405
        !            90: #define EXMMR_MAPOUT   0177406
        !            91: #define EXMMR_MAPIN    0177407
        !            92: #define EXMSR          0177410
        !            93: 
        !            94: /*
        !            95:  *     Extended memory status register bits
        !            96:  */
        !            97: 
        !            98: #define DBERROR                0100000
        !            99: #define SBERROR                040000
        !           100: #define MEMREADY       0200
        !           101: #define DBIE           0100
        !           102: #define MMENBL         02
        !           103: #define INITMEM                01
        !           104: 
        !           105: /*
        !           106:  *     Size of extended memory
        !           107:  */
        !           108: 
        !           109: #define NEXMPAGES      (256*2)
        !           110: #define WORDSPERPAGE   (256)
        !           111: 
        !           112: /*
        !           113:  *     MAP picture processor registers: SCB 0177750-0177753
        !           114:  */
        !           115: 
        !           116: #define MAOL           0177750
        !           117: #define MAOA           0177751
        !           118: #define MAIA           0177752
        !           119: #define MASR           0177753
        !           120: #define MAMSR          0177754
        !           121: 
        !           122: /*
        !           123:  *     MAP status register bits
        !           124:  */
        !           125: 
        !           126: #define PPDONE         0100000
        !           127: #define FIFOFULL       040000
        !           128: #define FIFOEMPTY      020000
        !           129: #define HIT            010000
        !           130: #define IB             04000
        !           131: #define TAKE           02000
        !           132: #define MMODE          01400
        !           133: #define MOSTOPPED      0200
        !           134: #define IOUT           0100
        !           135: #define MAO            040
        !           136: #define MAI            020
        !           137: #define HIT_HOLD       010
        !           138: #define RSR_HOLD       04
        !           139: #define VEC_HOLD       02
        !           140: #define MAP_RESET      01
        !           141: 
        !           142: /*
        !           143:  *     Refresh controller registers: SCB 0177730-0177737
        !           144:  */
        !           145: 
        !           146: #define RFCSN          0177730
        !           147: #define RFSN           0177731
        !           148: #define RFAWA          0177732
        !           149: #define RFAWL          0177733
        !           150: #define RFAIA          0177734
        !           151: #define RFASA          0177735
        !           152: #define RFAIL          0177736
        !           153: #define RFSR           0177737
        !           154: 
        !           155: /*
        !           156:  *     Refresh controller status register bits
        !           157:  */
        !           158: 
        !           159: #define RFSTOPPED      0100000
        !           160: #define RFHOLD         040000
        !           161: #define RFSTART                020000
        !           162: #define AUTOREF                010000
        !           163: #define RFBLANK                04000
        !           164: #define RIGHT          02000
        !           165: #define LGFIFO_FULL    01000
        !           166: #define NOT_EXEC       0200
        !           167: #define SKIPSEG                0100
        !           168: #define WRITEBACK      040
        !           169: #define SEARCH         020
        !           170: #define MATCH_HOLD     010
        !           171: #define MATCH_DEC      04
        !           172: #define SEARCH_MODE    03
        !           173: 
        !           174: /*
        !           175:  *     Interrupt control
        !           176:  */
        !           177: 
        !           178: #define RTCREQ         0177760
        !           179: #define RTCIE          0177761
        !           180: #define SYSREQ         0177762
        !           181: #define SYSIE          0177763
        !           182: #define DEVREQ         0177764
        !           183: #define DEVIE          0177765
        !           184: 
        !           185: /*
        !           186:  *     System interrupt request bits
        !           187:  */
        !           188: 
        !           189: #define LPEN_REQ       0200
        !           190: #define MATCH_REQ      0100
        !           191: #define WBSTOP_REQ     040
        !           192: #define RFSTOP_REQ     020
        !           193: #define MOSTOP_REQ     010
        !           194: #define JUMP_REQ       04
        !           195: #define HIT_REQ                02
        !           196: #define HALT_REQ       01
        !           197: 
        !           198: /*
        !           199:  *     Real-Time Clock registers
        !           200:  */
        !           201: 
        !           202: #define RTCCNT         0177744
        !           203: #define RTCSR          0177745
        !           204: 
        !           205: /*
        !           206:  *     Real-Time Clock status register bits
        !           207:  */
        !           208: 
        !           209: #define HZ120          040
        !           210: #define EXT            020
        !           211: #define SYNC           010
        !           212: #define EXTSEL2                04
        !           213: #define EXTSEL1                02
        !           214: #define RUN            01
        !           215: 
        !           216: /*
        !           217:  *     Control dials a/d registers
        !           218:  */
        !           219: 
        !           220: #define ADDR0          0177500
        !           221: #define ADDR1          0177501
        !           222: #define ADDR2          0177502
        !           223: #define ADDR3          0177503
        !           224: #define ADDR4          0177504
        !           225: #define ADDR5          0177505
        !           226: #define ADDR6          0177506
        !           227: #define ADDR7          0177507
        !           228: 
        !           229: /*
        !           230:  *     Function switches and lights
        !           231:  */
        !           232: 
        !           233: #define FSWR           0177626
        !           234: #define FSLR           0177627
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