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1.1 root 1: /*-
2: * Copyright (c) 1982, 1986 The Regents of the University of California.
3: * All rights reserved.
4: *
5: * Redistribution and use in source and binary forms, with or without
6: * modification, are permitted provided that the following conditions
7: * are met:
8: * 1. Redistributions of source code must retain the above copyright
9: * notice, this list of conditions and the following disclaimer.
10: * 2. Redistributions in binary form must reproduce the above copyright
11: * notice, this list of conditions and the following disclaimer in the
12: * documentation and/or other materials provided with the distribution.
13: * 3. All advertising materials mentioning features or use of this software
14: * must display the following acknowledgement:
15: * This product includes software developed by the University of
16: * California, Berkeley and its contributors.
17: * 4. Neither the name of the University nor the names of its contributors
18: * may be used to endorse or promote products derived from this software
19: * without specific prior written permission.
20: *
21: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31: * SUCH DAMAGE.
32: *
33: * @(#)qdreg.h 7.1 (Berkeley) 5/9/91
34: */
35:
36: /************************************************************************
37: * *
38: * Copyright (c) 1985, 1986 by *
39: * Digital Equipment Corporation, Maynard, MA *
40: * All rights reserved. *
41: * *
42: * This software is furnished under a license and may be used and *
43: * copied only in accordance with the terms of such license and *
44: * with the inclusion of the above copyright notice. This *
45: * software or any other copies thereof may not be provided or *
46: * otherwise made available to any other person. No title to and *
47: * ownership of the software is hereby transferred. *
48: * *
49: * The information in this software is subject to change without *
50: * notice and should not be construed as a commitment by Digital *
51: * Equipment Corporation. *
52: * *
53: * Digital assumes no responsibility for the use or reliability *
54: * of its software on equipment which is not supplied by Digital. *
55: * *
56: ************************************************************************/
57:
58: /* Dragon ADDER reg map */
59: /* ADDER register bit definitions */
60: /* Y_SCROLL_CONSTANT */
61:
62: #define SCROLL_ERASE 0x2000
63: #define ADDER_SCROLL_DOWN 0x1000
64:
65: /* ADDER status and interrupt enable registers [1], [2], [3] */
66:
67: #define DISABLE 0x0000
68: #define PAUSE_COMPLETE 0x0001
69: #define FRAME_SYNC 0x0002
70: #define INIT_COMPLETE 0x0004
71: #define RASTEROP_COMPLETE 0x0008
72:
73: #define ADDRESS_COMPLETE 0x0010
74: #define RX_READY 0x0020
75: #define TX_READY 0x0040
76: #define ID_SCROLL_READY 0x0080
77:
78: #define TOP_CLIP 0x0100
79: #define BOTTOM_CLIP 0x0200
80: #define LEFT_CLIP 0x0400
81: #define RIGHT_CLIP 0x0800
82: #define NO_CLIP 0x1000
83: #define VSYNC 0x2000
84:
85: /* ADDER command register [8], [10] */
86:
87: #define OCR_zero 0x0000
88: #define Z_BLOCK0 0x0000
89: #define OCRA 0x0000
90: #define OCRB 0x0004
91: #define RASTEROP 0x02c0
92: #define PBT 0x03c0
93: #define BTPZ 0x0bb0
94: #define PTBZ 0x07a0
95: #define DTE 0x0400
96: #define S1E 0x0800
97: #define S2E 0x1000
98: #define VIPER_Z_LOAD 0x01A0
99: #define ID_LOAD 0x0100
100: #define CANCEL 0x0000
101: #define LF_R1 0x0000
102: #define LF_R2 0x0010
103: #define LF_R3 0x0020
104: #define LF_R4 0x0030
105:
106: /* ADDER rasterop mode register [9] */
107:
108: #define NORMAL 0x0000
109: #define LINEAR_PATTERN 0x0002
110: #define X_FILL 0x0003
111: #define Y_FILL 0x0007
112: #define BASELINE 0x0008
113: #define HOLE_ENABLE 0x0010
114: #define SRC_1_INDEX_ENABLE 0x0020
115: #define DST_INDEX_ENABLE 0x0040
116: #define DST_WRITE_ENABLE 0x0080
117:
118: /* ADDER source 2 size register */
119:
120: #define NO_TILE 0x0080
121:
122: /* External registers base addresses */
123:
124: #define CS_UPDATE_MASK 0x0060
125: #define CS_SCROLL_MASK 0x0040
126:
127: /* VIPER registers */
128:
129: #define RESOLUTION_MODE 0x0080
130: #define MEMORY_BUS_WIDTH 0x0081
131: #define PLANE_ADDRESS 0x0083
132: #define LU_FUNCTION_R1 0x0084
133: #define LU_FUNCTION_R2 0x0085
134: #define LU_FUNCTION_R3 0x0086
135: #define LU_FUNCTION_R4 0x0087
136: #define MASK_1 0x0088
137: #define MASK_2 0x0089
138: #define SOURCE 0x008a
139: #define SOURCE_Z 0x0000
140: #define BACKGROUND_COLOR 0x008e
141: #define BACKGROUND_COLOR_Z 0x000C
142: #define FOREGROUND_COLOR 0x008f
143: #define FOREGROUND_COLOR_Z 0x0004
144: #define SRC1_OCR_A 0x0090
145: #define SRC2_OCR_A 0x0091
146: #define DST_OCR_A 0x0092
147: #define SRC1_OCR_B 0x0094
148: #define SRC2_OCR_B 0x0095
149: #define DST_OCR_B 0x0096
150:
151: /* VIPER scroll registers */
152:
153: #define SCROLL_CONSTANT 0x0082
154: #define SCROLL_FILL 0x008b
155: #define SCROLL_FILL_Z 0x0008
156: #define LEFT_SCROLL_MASK 0x008c
157: #define RIGHT_SCROLL_MASK 0x008d
158:
159: /* VIPER register bit definitions */
160:
161: #define EXT_NONE 0x0000
162: #define EXT_SOURCE 0x0001
163: #define EXT_M1_M2 0x0002
164: #define INT_NONE 0x0000
165: #define INT_SOURCE 0x0004
166: #define INT_M1_M2 0x0008
167: #define ID 0x0010
168: #define NO_ID 0x0000
169: #define WAIT 0x0020
170: #define NO_WAIT 0x0000
171: #define BAR_SHIFT_DELAY WAIT
172: #define NO_BAR_SHIFT_DELAY NO_WAIT
173:
174:
175: /* VIPER logical function unit codes */
176:
177: #define LF_ZEROS 0x0000
178: #define LF_D_XOR_S 0x0006
179: #define LF_SOURCE 0x000A
180: #define LF_D_OR_S 0x000E
181: #define LF_ONES 0x000F
182: #define INV_M1_M2 0x0030
183: #define FULL_SRC_RESOLUTION 0X00C0 /* makes second pass like first pass */
184:
185: /* VIPER scroll register [2] */
186:
187: #define SCROLL_DISABLE 0x0040
188: #define SCROLL_ENABLE 0x0020
189: #define VIPER_LEFT 0x0000
190: #define VIPER_RIGHT 0x0010
191: #define VIPER_UP 0x0040
192: #define VIPER_DOWN 0x0000
193:
194: /* Adder scroll register */
195:
196: #define ADDER_UP 0x0000
197: #define ADDER_DOWN 0x1000
198:
199: /* Misc scroll definitions */
200:
201: #define UP 0
202: #define DOWN 1
203: #define LEFT 2
204: #define RIGHT 3
205: #define NODIR 4
206: #define SCROLL_VMAX 31
207: #define SCROLL_HMAX 15
208: #define NEW 2
209: #define OLD 1
210: #define BUSY 1
211: #define DRAG 1
212: #define SCROLL 0
213:
214: /* miscellaneous defines */
215:
216: #define ALL_PLANES 0xffffffff
217: #define UNITY 0x1fff /* Adder scale factor */
218: #define MAX_SCREEN_X 1024
219: #define MAX_SCREEN_Y 864
220: #define FONT_HEIGHT 32
221:
222: struct adder {
223:
224: /* adder control registers */
225:
226: u_short register_address; /* ADDER reg pntr for use by DGA */
227: u_short request_enable; /* DMA request enables */
228: u_short interrupt_enable; /* interrupt enables */
229: u_short status; /* ADDER status bits */
230: u_short reserved1; /* test function only */
231: u_short spare1; /* spare address (what else?) */
232:
233: u_short reserved2; /* test function only */
234: u_short id_data; /* data path to I/D bus */
235: u_short command; /* ADDER chip command register */
236: u_short rasterop_mode; /* sets rasterop execution modes */
237: u_short cmd; /* duplicate path to above cmd reg */
238: u_short reserved3; /* test function only */
239:
240: /* scroll registers */
241:
242: u_short ID_scroll_data; /* I/D bus scroll data */
243: u_short ID_scroll_command; /* I/D bus scroll command */
244: u_short scroll_x_min; /* X scroll min - left boundary */
245: u_short scroll_x_max; /* X scroll max - right boundary */
246: u_short scroll_y_min; /* Y scroll min - upper boundary */
247: u_short scroll_y_max; /* Y scroll max - lower boundary */
248: u_short pause; /* Y coord to set stat when scanned */
249: u_short y_offset_pending; /* vertical scroll control */
250: u_short y_scroll_constant;
251:
252: /* update control registers */
253:
254: u_short x_index_pending; /* x pending index */
255: u_short y_index_pending; /* y pending index */
256: u_short x_index_new; /* new x index */
257: u_short y_index_new; /* new y index */
258: u_short x_index_old; /* old x index */
259: u_short y_index_old; /* old y index */
260: u_short x_clip_min; /* left clipping boundary */
261: u_short x_clip_max; /* right clipping boundary */
262: u_short y_clip_min; /* upper clipping boundary */
263: u_short y_clip_max; /* lower clipping boundary */
264: u_short spare2; /* spare address (another!) */
265:
266: /* rasterop control registers */
267:
268: u_short source_1_dx; /* source #1 x vector */
269: u_short source_1_dy; /* source #1 y vector*/
270: u_short source_1_x; /* source #1 x origin */
271: u_short source_1_y; /* source #1 y origin */
272: u_short destination_x; /* destination x origin */
273: u_short destination_y; /* destination y origin */
274: u_short fast_dest_dx; /* destination x fast vector */
275: u_short fast_dest_dy; /* destination y fast vector */
276: u_short slow_dest_dx; /* destination x slow vector */
277: u_short slow_dest_dy; /* destination y slow vector */
278: u_short fast_scale; /* scale factor for fast vector */
279: u_short slow_scale; /* scale factor for slow vector */
280: u_short source_2_x; /* source #2 x origin */
281: u_short source_2_y; /* source #2 y origin */
282: u_short source_2_size; /* source #2 height & width */
283: u_short error_1; /* error regs (?) */
284: u_short error_2;
285:
286: /* screen format control registers */
287:
288: u_short y_scan_count_0; /* y scan counts for vert timing */
289: u_short y_scan_count_1;
290: u_short y_scan_count_2;
291: u_short y_scan_count_3;
292: u_short x_scan_conf; /* x scan configuration */
293: u_short x_limit;
294: u_short y_limit;
295: u_short x_scan_count_0; /* x scan count for horiz timing */
296: u_short x_scan_count_1;
297: u_short x_scan_count_2;
298: u_short x_scan_count_3;
299: u_short x_scan_count_4;
300: u_short x_scan_count_5;
301: u_short x_scan_count_6;
302: u_short sync_phase_adj; /* sync phase (horiz sync count) */
303: };
304:
305: /*---------------------
306: * DUART definitions */
307:
308: /* command definitions */
309:
310: #define EN_RCV 0x01
311: #define DIS_RCV 0x02
312: #define EN_XMT 0x04
313: #define DIS_XMT 0x08
314: #define RESET_M 0x10
315: #define RESET_RCV 0x20
316: #define RESET_XMT 0x30
317: #define RESET_ERR 0x40
318: #define RESET_BD 0x50
319: #define START_BREAK 0x60
320: #define STOP_BREAK 0x70
321:
322: /* interupt bit definitions */
323:
324: #define EI_XMT_A 0x01
325: #define EI_RCV_A 0x02
326: #define EI_XMT_B 0x10
327: #define EI_RCV_B 0x20
328:
329: #define XMT_RDY_A 0x01
330: #define RCV_RDY_A 0x02
331: #define XMT_RDY_B 0x10
332: #define RCV_RDY_B 0x20
333:
334: /* status register bit defintions */
335:
336: #define RCV_RDY 0x01
337: #define FIFO_FULL 0x02
338: #define XMT_RDY 0x04
339: #define XMT_EMT 0x08
340: #define OVER_ERR 0x10
341: #define ERR_PARITY 0x20
342: #define FRAME_ERR 0x40
343: #define RCVD_BREAK 0x80
344:
345:
346: struct duart {
347:
348: /* channel A - LK201 */
349:
350: short modeA; /* ch.A mode reg (read/write) */
351: short statusA; /* ch.A status reg (read) */
352: #define clkselA statusA /* ch.A clock slect reg (write) */
353: short cmdA; /* ch.A command reg (write) */
354: short dataA; /* rcv/xmt data ch.A (read/write) */
355: short inchng; /* input change state reg (read) */
356: #define auxctl inchng /* auxiliary control reg (write) */
357: short istatus; /* interrupt status reg (read) */
358: #define imask istatus /* interrupt mask reg (write) */
359: short CThi; /* counter/timer hi byte (read) */
360: #define CTRhi CThi /* counter/timer hi reg (write) */
361: short CTlo; /* counter/timer lo byte (read) */
362: #define CTRlo CTlo /* counter/timer lo reg (write) */
363:
364: /* channel B - pointing device */
365:
366: short modeB; /* ch.B mode reg (read/write) */
367: short statusB; /* ch.B status reg (read) */
368: #define clkselB statusB /* ch.B clock select reg (write) */
369: short cmdB; /* ch.B command reg (write) */
370: short dataB; /* ch.B rcv/xmt data (read/write) */
371: short rsrvd;
372: short inport; /* input port (read) */
373: #define outconf inport /* output port config reg (write) */
374: short strctr; /* start counter command (read) */
375: #define setbits setctr /* output bits set command (write) */
376: short stpctr; /* stop counter command (read) */
377: #define resetbits stpctr /* output bits reset cmd (write) */
378:
379: };
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