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1.1 root 1: /*-
2: * Copyright (c) 1982, 1986 The Regents of the University of California.
3: * All rights reserved.
4: *
5: * Redistribution and use in source and binary forms, with or without
6: * modification, are permitted provided that the following conditions
7: * are met:
8: * 1. Redistributions of source code must retain the above copyright
9: * notice, this list of conditions and the following disclaimer.
10: * 2. Redistributions in binary form must reproduce the above copyright
11: * notice, this list of conditions and the following disclaimer in the
12: * documentation and/or other materials provided with the distribution.
13: * 3. All advertising materials mentioning features or use of this software
14: * must display the following acknowledgement:
15: * This product includes software developed by the University of
16: * California, Berkeley and its contributors.
17: * 4. Neither the name of the University nor the names of its contributors
18: * may be used to endorse or promote products derived from this software
19: * without specific prior written permission.
20: *
21: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31: * SUCH DAMAGE.
32: *
33: * @(#)ubareg.h 7.8 (Berkeley) 5/9/91
34: */
35:
36: /*
37: * VAX UNIBUS adapter registers
38: */
39:
40: /*
41: * "UNIBUS" adaptor types.
42: * This code is used for both UNIBUSes and Q-buses
43: * with different types of adaptors.
44: * Definition of a type includes support code for that type.
45: */
46: #if VAX780 || VAX8600
47: #define DW780 1 /* has adaptor regs, sr: 780/785/8600 */
48: #endif
49:
50: #if VAX750
51: #define DW750 2 /* has adaptor regs, no sr: 750, 730 */
52: #endif
53:
54: #if VAX730
55: #define DW730 3 /* has adaptor regs, no sr: 750, 730 */
56: #endif
57:
58: #if VAX630 || VAX650
59: #define QBA 4 /* 22-bit Q-bus, no adaptor regs: uVAX II */
60: #endif
61:
62: #if VAX8200 || VAX8500 || VAX8800
63: #define DWBUA 5 /* BI UNIBUS adaptor: 8200/8500/8800 */
64: #endif
65:
66: /*
67: * Size of unibus memory address space in pages
68: * (also number of map registers).
69: * QBAPAGES should be 8192, but we don't need nearly that much
70: * address space, and the return from the allocation routine
71: * can accommodate at most 2047 (ubavar.h: UBA_MAXMR);
72: * QBAPAGES must be at least UBAPAGES. Choose pragmatically.
73: */
74: #define UBAPAGES 496
75: #define NUBMREG 496
76: #if defined(GATEWAY) && !defined(QNIVERT)
77: #define QBAPAGES 1024
78: #else
79: #define QBAPAGES UBAPAGES
80: #endif
81: #define UBAIOADDR 0760000 /* start of I/O page */
82: #define UBAIOPAGES 16
83:
84: #ifndef LOCORE
85: /*
86: * DWBUA hardware registers.
87: */
88: struct dwbua_regs {
89: int pad1[456]; /* actually bii regs + pad */
90: int bua_csr; /* control and status register */
91: int bua_offset; /* vector offset register */
92: int bua_fubar; /* failed UNIBUS address register */
93: int bua_bifar; /* BI failed address register */
94: int bua_udiag[5]; /* micro diagnostics (R/O) */
95: int pad2[3];
96: /* dpr[0] is for DDP; dpr's 1 through 5 are for BPD's 1 through 5 */
97: int bua_dpr[6]; /* data path registers */
98: int pad3[10];
99: int bua_bdps[20]; /* buffered data path space *//*???*/
100: int pad4[8];
101: struct pte bua_map[UBAPAGES]; /* unibus map registers */
102: int pad5[UBAIOPAGES]; /* no maps for device address space */
103: };
104:
105: #ifdef DWBUA
106: /* bua_csr */
107: #define BUACSR_ERR 0x80000000 /* composite error */
108: #define BUACSR_BIF 0x10000000 /* BI failure */
109: #define BUACSR_SSYNTO 0x08000000 /* slave sync timeout */
110: #define BUACSR_UIE 0x04000000 /* unibus interlock error */
111: #define BUACSR_IVMR 0x02000000 /* invalid map register */
112: #define BUACSR_BADBDP 0x01000000 /* bad BDP select */
113: #define BUACSR_BUAEIE 0x00100000 /* bua error interrupt enable (?) */
114: #define BUACSR_UPI 0x00020000 /* unibus power init */
115: #define BUACSR_UREGDUMP 0x00010000 /* microdiag register dump */
116: #define BUACSR_IERRNO 0x000000ff /* mask for internal errror number */
117:
118: /* bua_offset */
119: #define BUAOFFSET_MASK 0x00003e00 /* hence max offset = 15872 */
120:
121: /* bua_dpr */
122: #define BUADPR_DPSEL 0x00e00000 /* data path select (?) */
123: #define BUADPR_PURGE 0x00000001 /* purge bdp */
124:
125: /* bua_map -- in particular, those bits that are not in DW780s & DW750s */
126: #define BUAMR_IOADR 0x40000000 /* I/O address space */
127: #define BUAMR_LAE 0x04000000 /* longword access enable */
128: /* I see no reason to use either one, though ... act 6 Aug 1987 */
129:
130: #define UBA_PURGEBUA(uba, bdp) \
131: (((struct dwbua_regs *)(uba))->bua_dpr[bdp] |= BUADPR_PURGE)
132: #else
133: #define UBA_PURGEBUA(uba, bdp)
134: #endif
135:
136: /*
137: * DW780/DW750 hardware registers
138: */
139: struct uba_regs {
140: int uba_cnfgr; /* configuration register */
141: int uba_cr; /* control register */
142: int uba_sr; /* status register */
143: int uba_dcr; /* diagnostic control register */
144: int uba_fmer; /* failed map entry register */
145: int uba_fubar; /* failed UNIBUS address register */
146: int pad1[2];
147: int uba_brsvr[4];
148: int uba_brrvr[4]; /* receive vector registers */
149: int uba_dpr[16]; /* buffered data path register */
150: int pad2[480];
151: struct pte uba_map[UBAPAGES]; /* unibus map register */
152: int pad3[UBAIOPAGES]; /* no maps for device address space */
153: };
154: #endif
155:
156: #ifdef DW780
157: /* uba_cnfgr */
158: #define UBACNFGR_UBINIT 0x00040000 /* unibus init asserted */
159: #define UBACNFGR_UBPDN 0x00020000 /* unibus power down */
160: #define UBACNFGR_UBIC 0x00010000 /* unibus init complete */
161:
162: #define UBACNFGR_BITS \
163: "\40\40PARFLT\37WSQFLT\36URDFLT\35ISQFLT\34MXTFLT\33XMTFLT\30ADPDN\27ADPUP\23UBINIT\22UBPDN\21UBIC"
164:
165: /* uba_cr */
166: #define UBACR_MRD16 0x40000000 /* map reg disable bit 4 */
167: #define UBACR_MRD8 0x20000000 /* map reg disable bit 3 */
168: #define UBACR_MRD4 0x10000000 /* map reg disable bit 2 */
169: #define UBACR_MRD2 0x08000000 /* map reg disable bit 1 */
170: #define UBACR_MRD1 0x04000000 /* map reg disable bit 0 */
171: #define UBACR_IFS 0x00000040 /* interrupt field switch */
172: #define UBACR_BRIE 0x00000020 /* BR interrupt enable */
173: #define UBACR_USEFIE 0x00000010 /* UNIBUS to SBI error field IE */
174: #define UBACR_SUEFIE 0x00000008 /* SBI to UNIBUS error field IE */
175: #define UBACR_CNFIE 0x00000004 /* configuration IE */
176: #define UBACR_UPF 0x00000002 /* UNIBUS power fail */
177: #define UBACR_ADINIT 0x00000001 /* adapter init */
178:
179: /* uba_sr */
180: #define UBASR_BR7FULL 0x08000000 /* BR7 receive vector reg full */
181: #define UBASR_BR6FULL 0x04000000 /* BR6 receive vector reg full */
182: #define UBASR_BR5FULL 0x02000000 /* BR5 receive vector reg full */
183: #define UBASR_BR4FULL 0x01000000 /* BR4 receive vector reg full */
184: #define UBASR_RDTO 0x00000400 /* UNIBUS to SBI read data timeout */
185: #define UBASR_RDS 0x00000200 /* read data substitute */
186: #define UBASR_CRD 0x00000100 /* corrected read data */
187: #define UBASR_CXTER 0x00000080 /* command transmit error */
188: #define UBASR_CXTMO 0x00000040 /* command transmit timeout */
189: #define UBASR_DPPE 0x00000020 /* data path parity error */
190: #define UBASR_IVMR 0x00000010 /* invalid map register */
191: #define UBASR_MRPF 0x00000008 /* map register parity failure */
192: #define UBASR_LEB 0x00000004 /* lost error */
193: #define UBASR_UBSTO 0x00000002 /* UNIBUS select timeout */
194: #define UBASR_UBSSYNTO 0x00000001 /* UNIBUS slave sync timeout */
195:
196: #define UBASR_BITS \
197: "\20\13RDTO\12RDS\11CRD\10CXTER\7CXTMO\6DPPE\5IVMR\4MRPF\3LEB\2UBSTO\1UBSSYNTO"
198:
199: /* uba_brrvr[] */
200: #define UBABRRVR_AIRI 0x80000000 /* adapter interrupt request */
201: #define UBABRRVR_DIV 0x0000ffff /* device interrupt vector field */
202: #endif
203:
204: /* uba_dpr */
205: #ifdef DW780
206: #define UBADPR_BNE 0x80000000 /* buffer not empty - purge */
207: #define UBADPR_BTE 0x40000000 /* buffer transfer error */
208: #define UBADPR_DPF 0x20000000 /* DP function (RO) */
209: #define UBADPR_BS 0x007f0000 /* buffer state field */
210: #define UBADPR_BUBA 0x0000ffff /* buffered UNIBUS address */
211: #define UBA_PURGE780(uba, bdp) \
212: ((uba)->uba_dpr[bdp] |= UBADPR_BNE)
213: #else
214: #define UBA_PURGE780(uba, bdp)
215: #endif
216: #ifdef DW750
217: #define UBADPR_ERROR 0x80000000 /* error occurred */
218: #define UBADPR_NXM 0x40000000 /* nxm from memory */
219: #define UBADPR_UCE 0x20000000 /* uncorrectable error */
220: #define UBADPR_PURGE 0x00000001 /* purge bdp */
221: /* the DELAY is for a hardware problem */
222: #define UBA_PURGE750(uba, bdp) { \
223: ((uba)->uba_dpr[bdp] |= (UBADPR_PURGE|UBADPR_NXM|UBADPR_UCE)); \
224: DELAY(8); \
225: }
226: #else
227: #define UBA_PURGE750(uba, bdp)
228: #endif
229:
230: /*
231: * Macros for fast buffered data path purging in time-critical routines.
232: *
233: * Too bad C pre-processor doesn't have the power of LISP in macro
234: * expansion...
235: */
236:
237: /* THIS IS WRONG, should use pointer to uba_hd */
238: #if DWBUA || DW780 || DW750
239: #define UBAPURGE(uba, bdp) { \
240: switch (cpu) { \
241: case VAX_8200: UBA_PURGEBUA(uba, bdp); break; \
242: case VAX_8600: case VAX_780: UBA_PURGE780((uba), (bdp)); break; \
243: case VAX_750: UBA_PURGE750((uba), (bdp)); break; \
244: } \
245: }
246: #else
247: #define UBAPURGE(uba, bdp)
248: #endif
249:
250:
251:
252: /* uba_mr[] */
253: #define UBAMR_MRV 0x80000000 /* map register valid */
254: #define UBAMR_BO 0x02000000 /* byte offset bit */
255: #define UBAMR_DPDB 0x01e00000 /* data path designator field */
256: #define UBAMR_SBIPFN 0x001fffff /* SBI page address field */
257:
258: #define UBAMR_DPSHIFT 21 /* shift to data path designator */
259:
260: /*
261: * Number of unibus buffered data paths and possible uba's per cpu type.
262: */
263: #define NBDP8600 15
264: #define NBDP780 15
265: #define NBDPBUA 5
266: #define NBDP750 3
267: #define NBDP730 0
268: #define MAXNBDP 15
269:
270: /*
271: * Symbolic BUS addresses for UBAs.
272: */
273:
274: #if VAX630 || VAX650
275: #define QBAMAP630 ((struct pte *)0x20088000)
276: #define QMEM630 0x30000000
277: #define QIOPAGE630 0x20000000
278: /*
279: * Q-bus control registers
280: */
281: #define QIPCR 0x1f40 /* from start of iopage */
282: /* bits in QIPCR */
283: #define Q_DBIRQ 0x0001 /* doorbell interrupt request */
284: #define Q_LMEAE 0x0020 /* local mem external access enable */
285: #define Q_DBIIE 0x0040 /* doorbell interrupt enable */
286: #define Q_AUXHLT 0x0100 /* auxiliary processor halt */
287: #define Q_DMAQPE 0x8000 /* Q22 bus address space parity error */
288: #endif
289:
290: #if VAX730
291: #define UMEM730 0xfc0000
292: #endif
293:
294: #if VAX750
295: #define UMEM750(i) (0xfc0000-(i)*0x40000)
296: #endif
297:
298: #if VAX780
299: #define UMEM780(i) (0x20100000+(i)*0x40000)
300: #endif
301:
302: #if VAX8200 /* BEWARE, argument is node, not ubanum */
303: #define UMEM8200(i) (0x20400000+(i)*0x40000)
304: #endif
305:
306: #if VAX8600
307: #define UMEMA8600(i) (0x20100000+(i)*0x40000)
308: #define UMEMB8600(i) (0x22100000+(i)*0x40000)
309: #endif
310:
311: /*
312: * Macro to offset a UNIBUS device address, often expressed as
313: * something like 0172520, by forcing it into the last 8K
314: * of UNIBUS memory space.
315: */
316: #define ubdevreg(addr) ((addr) & 017777)
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