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1.1 root 1: /*
2: * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
3: *
4: * Intel PIIX/PIIX3/PIIX4 PCI IDE controller.
5: * PIIX = PCI-ISA-IDE-Xelerator. (also USB on newer controllers)
6: *
7: * Notes:
8: *
9: * PIIX introduced in the "Triton" chipset.
10: * PIIX3 supports different timings for Master/Slave devices on both channels.
11: * PIIX4 adds support for Ultra DMA/33.
12: *
13: * Be sure to download and read the PIIX errata from Intel's web site at
14: * developer.intel.com.
15: *
16: * HISTORY:
17: *
18: */
19:
20: #ifndef _APPLEATAPIIXREGS_H
21: #define _APPLEATAPIIXREGS_H
22:
23: /*
24: * PCI ID for supported PIIX variants.
25: */
26: #define PCI_ID_PIIX 0x12308086
27: #define PCI_ID_PIIX3 0x70108086
28: #define PCI_ID_PIIX4 0x71118086
29: #define PCI_ID_NONE 0xffffffff
30:
31: /*
32: * Decoded port addresses. Seems to be hardcoded and it does not
33: * show up in the PCI configuration space memory ranges.
34: */
35: #define PIIX_P_CMD_ADDR 0x1f0
36: #define PIIX_P_CTL_ADDR 0x3f4
37: #define PIIX_S_CMD_ADDR 0x170
38: #define PIIX_S_CTL_ADDR 0x374
39: #define PIIX_CMD_SIZE 8
40: #define PIIX_CTL_SIZE 4
41:
42: /*
43: * IRQ assignment.
44: */
45: #define PIIX_P_IRQ 14
46: #define PIIX_S_IRQ 15
47:
48: /*
49: * PIIX has two IDE channels.
50: */
51: #define PIIX_CHANNEL_PRIMARY 0
52: #define PIIX_CHANNEL_SECONDARY 1
53:
54: /*
55: * PIIX PCI config space registers.
56: * Register size (bits) in parenthesis.
57: */
58: #define PIIX_PCI_CFID 0x00
59:
60: #define PIIX_PCI_PCICMD 0x04 // (16) PCI command register
61: #define PIIX_PCI_PCICMD_IOSE 0x01 // I/O space enable
62: #define PIIX_PCI_PCICMD_BME 0x04 // bus-master enable
63:
64: #define PIIX_PCI_PCISTS 0x06 // (16) PCI device status register
65: #define PIIX_PCI_RID 0x08 // (8) Revision ID register
66: #define PIIX_PCI_CLASSC 0x09 // (24) Class code register
67: #define PIIX_PCI_MLT 0x0d // (8) Master latency timer register
68: #define PIIX_PCI_HEDT 0x0e // (8) Header type register
69:
70: #define PIIX_PCI_BMIBA 0x20 // (32) Bus-Master base address
71: #define PIIX_PCI_BMIBA_RTE 0x01 // resource type indicator (I/O)
72: #define PIIX_PCI_BMIBA_MASK 0xfff0 // base address mask
73:
74: #define PIIX_PCI_IDETIM 0x40 // (16) IDE timing registers (pri)
75: #define PIIX_PCI_IDETIM_S 0x42 // (16) IDE timing registers (sec)
76: #define PIIX_PCI_SIDETIM 0x44 // (8) Slave IDE timing register
77: #define PIIX_PCI_UDMACTL 0x48 // (8) Ultra DMA/33 control register
78: #define PIIX_PCI_UDMATIM 0x4a // (16) Ultra DMA/33 timing register
79:
80: /*
81: * PIIX PCI configuration space register definition.
82: *
83: * PIIX_IDETIM - IDE timing register.
84: *
85: * Address:
86: * 0x40:0x41 - Primary channel
87: * 0x42:0x43 - Secondary channel
88: */
89: #define PIIX_PCI_IDETIM_IDE 0x8000 // IDE decode enable
90: #define PIIX_PCI_IDETIM_SITRE 0x4000 // slave timing register enable
91:
92: #define PIIX_PCI_IDETIM_ISP_MASK 0x3000
93: #define PIIX_PCI_IDETIM_ISP_SHIFT 12
94: #define PIIX_PCI_IDETIM_ISP_5 0x0000 // IORDY sample point
95: #define PIIX_PCI_IDETIM_ISP_4 0x1000 // (PCI clocks)
96: #define PIIX_PCI_IDETIM_ISP_3 0x2000
97: #define PIIX_PCI_IDETIM_ISP_2 0x3000
98:
99: #define PIIX_PCI_IDETIM_RTC_MASK 0x0300
100: #define PIIX_PCI_IDETIM_RTC_SHIFT 8
101: #define PIIX_PCI_IDETIM_RTC_4 0x0000 // receovery time (PCI clocks)
102: #define PIIX_PCI_IDETIM_RTC_3 0x0100
103: #define PIIX_PCI_IDETIM_RTC_2 0x0200
104: #define PIIX_PCI_IDETIM_RTC_1 0x0300
105:
106: #define PIIX_PCI_IDETIM_DTE1 0x0080 // DMA timing enable only
107: #define PIIX_PCI_IDETIM_PPE1 0x0040 // prefetch and posting enabled
108: #define PIIX_PCI_IDETIM_IE1 0x0020 // IORDY sample point enable
109: #define PIIX_PCI_IDETIM_TIME1 0x0010 // fast timing enable
110: #define PIIX_PCI_IDETIM_DTE0 0x0008 // same as above for drive 0
111: #define PIIX_PCI_IDETIM_PPE0 0x0004
112: #define PIIX_PCI_IDETIM_IE0 0x0002
113: #define PIIX_PCI_IDETIM_TIME0 0x0001
114:
115: /*
116: * PIIX PCI configuration space register definition.
117: *
118: * PIIX_SIDETIM - Slave IDE timing register.
119: *
120: * Address: 0x44
121: */
122: #define PIIX_PCI_SIDETIM_SISP1_MASK 0xc0
123: #define PIIX_PCI_SIDETIM_SISP1_SHIFT 6
124: #define PIIX_PCI_SIDETIM_SRTC1_MASK 0x30
125: #define PIIX_PCI_SIDETIM_SRTC1_SHIFT 4
126: #define PIIX_PCI_SIDETIM_PISP1_MASK 0x0c
127: #define PIIX_PCI_SIDETIM_PISP1_SHIFT 2
128: #define PIIX_PCI_SIDETIM_PRTC1_MASK 0x03
129: #define PIIX_PCI_SIDETIM_PRTC1_SHIFT 0
130:
131: /*
132: * PIIX PCI configuration space register definition.
133: *
134: * PIIX_UDMACTL - Ultra DMA/33 control register
135: *
136: * Address: 0x48
137: */
138: #define PIIX_PCI_UDMACTL_SSDE1 0x08 // Enable UDMA/33 Sec/Drive1
139: #define PIIX_PCI_UDMACTL_SSDE0 0x04 // Enable UDMA/33 Sec/Drive0
140: #define PIIX_PCI_UDMACTL_PSDE1 0x02 // Enable UDMA/33 Pri/Drive1
141: #define PIIX_PCI_UDMACTL_PSDE0 0x01 // Enable UDMA/33 Pri/Drive0
142:
143: /*
144: * PIIX PCI configuration space register definition.
145: *
146: * PIIX_UDMATIM - Ultra DMA/33 timing register
147: *
148: * Address: 0x4a-0x4b
149: */
150: #define PIIX_PCI_UDMATIM_PCT0_MASK 0x0003
151: #define PIIX_PCI_UDMATIM_PCT0_SHIFT 0
152: #define PIIX_PCI_UDMATIM_PCT1_MASK 0x0030
153: #define PIIX_PCI_UDMATIM_PCT1_SHIFT 4
154: #define PIIX_PCI_UDMATIM_SCT0_MASK 0x0300
155: #define PIIX_PCI_UDMATIM_SCT0_SHIFT 8
156: #define PIIX_PCI_UDMATIM_SCT1_MASK 0x3000
157: #define PIIX_PCI_UDMATIM_SCT1_SHIFT 12
158:
159:
160: /*
161: * PIIX IO space register offsets. Base address is set in PIIX_PCI_BMIBA.
162: * Register size (bits) in parenthesis.
163: *
164: * Note:
165: * For the primary channel, the base address is stored in PIIX_PCI_BMIBA.
166: * For the secondary channel, an offset (PIIX_IO_BM_OFFSET) is added to
167: * the value stored in PIIX_PCI_BMIBA.
168: */
169: #define PIIX_IO_BMICX 0x00 // (8) Bus master command register
170: #define PIIX_IO_BMISX 0x02 // (8) Bus master status register
171: #define PIIX_IO_BMIDTPX 0x04 // (32) Descriptor table register
172:
173: #define PIIX_IO_BM_OFFSET 0x08 // offset to sec channel registers
174: #define PIIX_IO_BM_SIZE 0x08 // BM registers size for each channel
175: #define PIIX_IO_BM_MASK 0xfff0 // BMIBA mask to get I/O base address
176:
177: /*
178: * PIIX IO space register definition.
179: *
180: * BMICX - Bus master IDE command register
181: */
182: #define PIIX_IO_BMICX_SSBM 0x01 // 1=Start, 0=Stop
183: #define PIIX_IO_BMICX_RWCON 0x08 // 0=Read, 1=Write
184:
185: /*
186: * PIIX IO space register definition.
187: *
188: * PIIX_BMISX - Bus master IDE status register
189: */
190: #define PIIX_IO_BMISX_DMA1CAP 0x40 // drive 1 is capable of DMA transfers
191: #define PIIX_IO_BMISX_DMA0CAP 0x20 // drive 0 is capable of DMA transfers
192: #define PIIX_IO_BMISX_IDEINTS 0x04 // IDE device asserted its interrupt
193: #define PIIX_IO_BMISX_ERROR 0x02 // DMA error (cleared by writing a 1)
194: #define PIIX_IO_BMISX_BMIDEA 0x01 // bus master active bit
195:
196: #define PIIX_IO_BMISX_STATUS (PIIX_IO_BMISX_IDEINTS | \
197: PIIX_IO_BMISX_ERROR | \
198: PIIX_IO_BMISX_BMIDEA)
199:
200: /*
201: * PIIX Bus Master alignment/boundary requirements.
202: *
203: * Intel nomemclature:
204: * WORD - 16-bit
205: * DWord - 32-bit
206: */
207: #define PIIX_DT_ALIGN 4 // descriptor table must be DWord aligned.
208: #define PIIX_DT_BOUND (4 * 1024) // cannot cross 4K boundary. (or 64K ?)
209:
210: #define PIIX_BUF_ALIGN 2 // memory buffer must be word aligned.
211: #define PIIX_BUF_BOUND (64 * 1024) // cannot cross 64K boundary.
212: #define PIIX_BUF_LIMIT (64 * 1024) // limited to 64K in size
213:
214: /*
215: * PIIX Bus Master Physical Region Descriptor (PRD).
216: */
217: typedef struct {
218: UInt32 base; // base address
219: UInt16 count; // byte count
220: UInt16 flags; // flag bits
221: } prdEntry_t;
222:
223: #define PRD_FLAG_EOT 0x8000
224:
225: #define PRD_COUNT(x) (((x) == PIIX_BUF_LIMIT) ? 0 : (x))
226: #define PRD_TABLE_SIZE PAGE_SIZE
227: #define PRD_ENTRIES (PRD_TABLE_SIZE / sizeof(prdEntry_t))
228:
229: /*
230: * PIIX Register setting macro.
231: */
232: #define SET_REG_FIELD(reg, field, val) \
233: { \
234: reg &= ~(field ## _MASK); \
235: reg |= (((val) << field ## _SHIFT) & \
236: field ## _MASK); \
237: }
238:
239: /*
240: * Convert the "isp" and "rtc" fields in PIIX_IDETIM register from
241: * PCI clocks to their respective values, and vice-versa.
242: */
243: #define PIIX_CLK_TO_ISP(x) (5 - (x))
244: #define PIIX_ISP_TO_CLK(x) PIIX_CLK_TO_ISP(x)
245: #define PIIX_CLK_TO_RTC(x) (4 - (x))
246: #define PIIX_RTC_TO_CLK(x) PIIX_CLK_TO_RTC(x)
247:
248: #endif /* !_APPLEATAPIIXREGS_H */
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