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1.1 root 1: /*
2: * Copyright (c) 1998-2000 Apple Computer, Inc. All rights reserved.
3: *
4: * @APPLE_LICENSE_HEADER_START@
5: *
6: * The contents of this file constitute Original Code as defined in and
7: * are subject to the Apple Public Source License Version 1.1 (the
8: * "License"). You may not use this file except in compliance with the
9: * License. Please obtain a copy of the License at
10: * http://www.apple.com/publicsource and read it before using this file.
11: *
12: * This Original Code and all software distributed under the License are
13: * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14: * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15: * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16: * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17: * License for the specific language governing rights and limitations
18: * under the License.
19: *
20: * @APPLE_LICENSE_HEADER_END@
21: */
22: /*
23: *
24: * AppleATAUltra646.cpp
25: *
26: */
27: #include "AppleATAUltra646.h"
28:
29: #include <IOKit/IODeviceTreeSupport.h>
30:
31: #undef super
32: #define super AppleATA
33:
34: extern pmap_t kernel_pmap;
35:
36: OSDefineMetaClassAndStructors( AppleATAUltra646, AppleATA )
37:
38:
39: static struct
40: {
41: UInt32 minDataAccess;
42: UInt32 minDataCycle;
43: } pioModes[] =
44: {
45: { 165, 600 }, /* Mode 0 */
46: { 125, 383 }, /* 1 */
47: { 100, 240 }, /* 2 */
48: { 80, 180 }, /* 3 */
49: { 70, 120 } /* 4 */
50: };
51:
52:
53: /*
54: *
55: *
56: */
57: bool AppleATAUltra646::configure( IOService *forProvider, UInt32 *controllerDataSize )
58: {
59: *controllerDataSize = 0;
60:
61: provider = (IOPCIDevice *)forProvider;
62:
63: busNum = 0;
64:
65: ioMapATA[0] = provider->mapDeviceMemoryWithRegister( 0x10 + busNum * 8 + 0 );
66: if ( ioMapATA[0] == NULL ) return false;
67: ioBaseATA[0] = (volatile UInt32 *)ioMapATA[0]->getVirtualAddress();
68:
69: ioMapATA[1] = provider->mapDeviceMemoryWithRegister( 0x10 + busNum * 8 + 4 );
70: if ( ioMapATA[1] == NULL ) return false;
71: ioBaseATA[1] = (volatile UInt32 *)ioMapATA[1]->getVirtualAddress();
72:
73: pciWriteLong( 0x04, 0x05 );
74:
75: dmaDescriptors = (Ultra646Descriptor *)kalloc(page_size);
76: if ( dmaDescriptors == 0 )
77: {
78: return false;
79: }
80:
81: dmaDescriptorsPhys = (UInt32) pmap_extract(kernel_pmap, (vm_offset_t) dmaDescriptors);
82:
83: if ( (UInt32)dmaDescriptors & (page_size - 1) )
84: {
85: IOLog("AppleATAUltra646::%s() - DMA Descriptor memory not page aligned!!", __FUNCTION__);
86: return false;
87: }
88:
89: bzero( dmaDescriptors, page_size );
90:
91: numDescriptors = page_size/sizeof(Ultra646Descriptor);
92:
93: dmaMemoryCursor = IOBigMemoryCursor::withSpecification( 64*1024-2, 0xffffffff );
94: if ( dmaMemoryCursor == NULL )
95: {
96: return false;
97: }
98:
99: bitBucketAddr = IOMalloc(32);
100: if ( bitBucketAddr == 0 )
101: {
102: return false;
103: }
104: bitBucketAddrPhys = (UInt32) pmap_extract(kernel_pmap, (vm_offset_t) (((UInt32)bitBucketAddr + 0xf) & ~0x0f));
105:
106:
107: // assumes the first child determines the path OF uses to reference the controller
108: pathProvider = OSDynamicCast(IOService, provider->getChildEntry(gIODTPlane));
109:
110: return true;
111: }
112:
113:
114: /*
115: *
116: *
117: */
118: bool AppleATAUltra646::createWorkLoop( IOWorkLoop **workLoop )
119: {
120: if ( super::createWorkLoop( workLoop ) != true )
121: {
122: return false;
123: }
124:
125: interruptEventSource = IOInterruptEventSource::interruptEventSource( (OSObject *) this,
126: (IOInterruptEventAction) &AppleATAUltra646::interruptOccurred,
127: (IOService *) provider,
128: (int) 0 );
129:
130: if ( interruptEventSource == NULL )
131: {
132: return false;
133: }
134:
135: disableControllerInterrupts();
136:
137: (*workLoop)->addEventSource( interruptEventSource );
138:
139: timerEventSource = IOTimerEventSource::timerEventSource( this, (IOTimerEventSource::Action) &AppleATAUltra646::ataTimer );
140: if ( timerEventSource == NULL )
141: {
142: return false;
143: }
144: (*workLoop)->addEventSource( timerEventSource );
145:
146: ataTimer( timerEventSource );
147:
148: return true;
149: }
150:
151:
152: /*
153: *
154: *
155: */
156: bool AppleATAUltra646::provideProtocols( ATAProtocol *protocolsSupported )
157: {
158: return false;
159: }
160:
161:
162: /*
163: *
164: *
165: */
166: bool AppleATAUltra646::provideTimings( UInt32 *numTimings, ATATiming *timingsSupported )
167: {
168: return false;
169: }
170:
171:
172: /*
173: *
174: *
175: */
176: bool AppleATAUltra646::calculateTiming( UInt32 unit, ATATiming *pTiming )
177: {
178: bool rc = false;
179:
180: ideTimingRegs[unit].arttimReg = 0x40;
181: ideTimingRegs[unit].cmdtimReg = 0xA9;
182:
183: switch ( pTiming->timingProtocol )
184: {
185: case ataTimingPIO:
186: rc = calculatePIOTiming( unit, pTiming );
187: break;
188:
189: case ataTimingDMA:
190: rc = calculateDMATiming( unit, pTiming );
191: break;
192:
193: case ataTimingUltraDMA33:
194: rc = calculateUltraDMATiming( unit, pTiming );
195: break;
196:
197:
198: default:
199: ;
200: }
201:
202: return rc;
203: }
204:
205: /*
206: *
207: *
208: */
209: bool AppleATAUltra646::calculatePIOTiming( UInt32 unit, ATATiming *pTiming )
210: {
211: UInt32 accessTime;
212: UInt32 drwActClks, drwRecClks;
213: UInt32 drwActTime, drwRecTime;
214:
215: accessTime = pioModes[pTiming->mode].minDataAccess;
216:
217: drwActClks = accessTime / IDE_SYSCLK_NS;
218: drwActClks += (accessTime % IDE_SYSCLK_NS) ? 1 : 0;
219: drwActTime = drwActClks * IDE_SYSCLK_NS;
220:
221: drwRecTime = pioModes[pTiming->mode].minDataCycle - drwActTime;
222: drwRecClks = drwRecTime / IDE_SYSCLK_NS;
223: drwRecClks += (drwRecTime % IDE_SYSCLK_NS) ? 1 : 0;
224:
225: if ( drwRecClks >= 16 )
226: drwRecClks = 1;
227: else if ( drwRecClks <= 1 )
228: drwRecClks = 16;
229:
230: ideTimingRegs[unit].drwtimRegPIO = ((drwActClks & 0x0f) << 4) | ((drwRecClks-1) & 0x0f);
231:
232: return true;
233: }
234:
235:
236: /*
237: *
238: *
239: */
240: bool AppleATAUltra646::calculateDMATiming( UInt32 unit, ATATiming *pTiming )
241: {
242: UInt32 accessTime;
243: UInt32 drwActClks, drwRecClks;
244: UInt32 drwActTime, drwRecTime;
245:
246: ideTimingRegs[unit].udidetcrReg = 0;
247:
248: accessTime = pTiming->minDataAccess;
249:
250: drwActClks = accessTime / IDE_SYSCLK_NS;
251: drwActClks += (accessTime % IDE_SYSCLK_NS) ? 1 : 0;
252: drwActTime = drwActClks * IDE_SYSCLK_NS;
253:
254: drwRecTime = pTiming->minDataCycle - drwActTime;
255: drwRecClks = drwRecTime / IDE_SYSCLK_NS;
256: drwRecClks += (drwRecTime % IDE_SYSCLK_NS) ? 1 : 0;
257:
258: if ( drwRecClks >= 16 )
259: drwRecClks = 1;
260: else if ( drwRecClks <= 1 )
261: drwRecClks = 16;
262:
263: ideTimingRegs[unit].drwtimRegDMA = ((drwActClks & 0x0f) << 4) | ((drwRecClks-1) & 0x0f);
264:
265: return true;
266: }
267:
268: /*
269: *
270: *
271: */
272: bool AppleATAUltra646::calculateUltraDMATiming( UInt32 unit, ATATiming *pTiming )
273: {
274: UInt32 cycleClks;
275: UInt32 cycleTime;
276:
277: cycleTime = pTiming->minDataCycle;
278:
279: cycleClks = cycleTime / IDE_SYSCLK_NS;
280: cycleClks += (cycleTime % IDE_SYSCLK_NS) ? 1 : 0;
281:
282: ideTimingRegs[unit].udidetcrReg = (0x01 << unit) | ((cycleClks-1) << ((!unit) ? 4 : 6)) ;
283:
284: return true;
285: }
286:
287: /*
288: *
289: *
290: */
291: void AppleATAUltra646::newDeviceSelected( IOATADevice *newDevice )
292: {
293: }
294:
295:
296: /*
297: *
298: *
299: */
300: bool AppleATAUltra646::selectTiming( UInt32 unit, ATATimingProtocol timingProtocol )
301: {
302: Ultra646Regs *cfgRegs;
303: UInt32 cfgByte;
304:
305: cfgRegs = &ideTimingRegs[unit];
306:
307: if ( busNum == 0 )
308: {
309: pciWriteByte( Ultra646CMDTIM, cfgRegs->cmdtimReg );
310:
311: if ( unit == 0 )
312: {
313: pciWriteByte( Ultra646ARTTIM0, cfgRegs->arttimReg );
314:
315: if ( timingProtocol == ataTimingPIO )
316: {
317: cfgByte = pciReadByte( Ultra646CNTRL );
318: cfgByte &= ~Ultra646CNTRL_Drive0ReadAhead;
319: cfgByte |= cfgRegs->cntrlReg;
320: pciWriteByte( Ultra646CNTRL, cfgByte );
321:
322: pciWriteByte( Ultra646DRWTIM0, cfgRegs->drwtimRegPIO );
323: }
324: else if ( timingProtocol == ataTimingDMA )
325: {
326: pciWriteByte( Ultra646DRWTIM0, cfgRegs->drwtimRegDMA );
327: }
328: else if ( timingProtocol == ataTimingUltraDMA33 )
329: {
330: cfgByte = pciReadByte( Ultra646UDIDETCR0 );
331: cfgByte &= ~(Ultra646UDIDETCR0_Drive0UDMACycleTime | Ultra646UDIDETCR0_Drive0UDMAEnable);
332: cfgByte |= cfgRegs->udidetcrReg;
333: pciWriteByte( Ultra646UDIDETCR0, cfgByte );
334: }
335: }
336: else
337: {
338: pciWriteByte( Ultra646ARTTIM1, cfgRegs->arttimReg );
339:
340: if ( timingProtocol == ataTimingPIO )
341: {
342: cfgByte = pciReadByte( Ultra646CNTRL );
343: cfgByte &= ~Ultra646CNTRL_Drive1ReadAhead;
344: cfgByte |= cfgRegs->cntrlReg;
345: pciWriteByte( Ultra646CNTRL, cfgByte );
346:
347: pciWriteByte( Ultra646DRWTIM1, cfgRegs->drwtimRegPIO );
348: }
349: else if ( timingProtocol == ataTimingDMA )
350: {
351: pciWriteByte( Ultra646DRWTIM1, cfgRegs->drwtimRegDMA );
352: }
353: else if ( timingProtocol == ataTimingUltraDMA33 )
354: {
355: cfgByte = pciReadByte( Ultra646UDIDETCR0 );
356: cfgByte &= ~(Ultra646UDIDETCR0_Drive1UDMACycleTime | Ultra646UDIDETCR0_Drive1UDMAEnable);
357: cfgByte |= cfgRegs->udidetcrReg;
358: pciWriteByte( Ultra646UDIDETCR0, cfgByte );
359: }
360: }
361: }
362: else
363: {
364: pciWriteByte( Ultra646CMDTIM, cfgRegs->cmdtimReg );
365:
366: if ( unit == 0 )
367: {
368: cfgByte = pciReadByte( Ultra646ARTTIM23 );
369: cfgByte &= ~(Ultra646ARTTIM23_Drive2ReadAhead | Ultra646ARTTIM23_AddrSetup);
370: cfgByte |= (cfgRegs->cntrlReg >> 4) | cfgRegs->arttimReg;
371: pciWriteByte( Ultra646ARTTIM23, cfgByte );
372:
373: if ( timingProtocol == ataTimingPIO )
374: {
375: pciWriteByte( Ultra646DRWTIM2, cfgRegs->drwtimRegPIO );
376: }
377: else if ( timingProtocol == ataTimingDMA )
378: {
379: pciWriteByte( Ultra646DRWTIM1, cfgRegs->drwtimRegDMA );
380: }
381: else if ( timingProtocol == ataTimingUltraDMA33 )
382: {
383: cfgByte = pciReadByte( Ultra646UDIDETCR1 );
384: cfgByte &= ~(Ultra646UDIDETCR1_Drive2UDMACycleTime | Ultra646UDIDETCR1_Drive2UDMAEnable);
385: cfgByte |= cfgRegs->udidetcrReg;
386: pciWriteByte( Ultra646UDIDETCR1, cfgByte );
387: }
388: }
389: else
390: {
391: cfgByte = pciReadByte( Ultra646ARTTIM23 );
392: cfgByte &= ~(Ultra646ARTTIM23_Drive3ReadAhead | Ultra646ARTTIM23_AddrSetup);
393: cfgByte |= (cfgRegs->cntrlReg >> 4) | cfgRegs->arttimReg;
394: pciWriteByte( Ultra646ARTTIM23, cfgByte );
395:
396: if ( timingProtocol == ataTimingPIO )
397: {
398: pciWriteByte( Ultra646DRWTIM3, cfgRegs->drwtimRegPIO );
399: }
400: else if ( timingProtocol == ataTimingDMA )
401: {
402: pciWriteByte( Ultra646DRWTIM3, cfgRegs->drwtimRegDMA );
403: }
404: else if ( timingProtocol == ataTimingUltraDMA33 )
405: {
406: cfgByte = pciReadByte( Ultra646UDIDETCR1 );
407: cfgByte &= ~(Ultra646UDIDETCR1_Drive3UDMACycleTime | Ultra646UDIDETCR1_Drive3UDMAEnable);
408: cfgByte |= cfgRegs->udidetcrReg;
409: pciWriteByte( Ultra646UDIDETCR1, cfgByte );
410: }
411: }
412: }
413:
414: return true;
415: }
416:
417:
418: /*
419: *
420: *
421: */
422: void AppleATAUltra646::interruptOccurred()
423: {
424: UInt32 intReg;
425: UInt32 cfgReg;
426:
427: super::interruptOccurred();
428:
429: intReg = (busNum == 0) ? Ultra646CFR : Ultra646ARTTIM23;
430: cfgReg = pciReadByte( intReg );
431: pciWriteByte( intReg, cfgReg );
432: }
433:
434: /*
435: *
436: *
437: */
438: void AppleATAUltra646::ataTimer( IOTimerEventSource * /* sender */ )
439: {
440: UInt32 transferCount;
441:
442: if ( xferCmdTimer != 0 )
443: {
444: if ( --xferCmdTimer == 0 )
445: {
446: IOLog("AppleATAUltra646::%s() - Timeout occurred\n\r", __FUNCTION__ );
447:
448: stopDma( xferCmd, &transferCount );
449:
450: resetBusRequest();
451:
452: if ( xferCmdSave != NULL )
453: {
454: xferCmd = xferCmdSave;
455: xferCmdSave = NULL;
456: }
457: completeCmd( xferCmd, ataReturnErrorInterruptTimeout );
458: }
459: }
460:
461: timerEventSource->setTimeoutMS(ATATimerIntervalmS);
462: }
463:
464: /*
465: *
466: *
467: */
468: bool AppleATAUltra646::programDma( IOATACommand *cmd )
469: {
470: IOMemoryDescriptor *memoryDesc;
471: IOPhysicalSegment physSeg;
472: IOByteCount offset;
473: UInt32 i;
474: UInt32 bytesLeft;
475: UInt32 len;
476: Ultra646Descriptor *dmaDesc;
477: UInt32 startSeg, endSeg;
478:
479: cmd->getPointers( &memoryDesc, &dmaReqLength, &dmaIsWrite );
480:
481: if ( dmaReqLength == 0 )
482: {
483: return true;
484: }
485:
486: offset = 0;
487:
488: dmaDesc = dmaDescriptors;
489:
490: bytesLeft = dmaReqLength;
491:
492: for (i = 0; i < numDescriptors-1; i++, dmaDesc++ )
493: {
494: if ( dmaMemoryCursor->getPhysicalSegments( memoryDesc, offset, &physSeg, 1 ) != 1 )
495: {
496: break;
497: }
498:
499: startSeg = (physSeg.location & ~0xffff);
500: endSeg = (physSeg.location + physSeg.length - 1) & ~0xffff;
501:
502: OSWriteSwapInt32( &dmaDesc->start, 0, physSeg.location);
503:
504: if ( startSeg == endSeg )
505: {
506: OSWriteSwapInt32( &dmaDesc->length, 0, physSeg.length );
507: }
508: else
509: {
510: len = (-physSeg.location & 0xffff);
511: OSWriteSwapInt32( &dmaDesc->length, 0, len );
512: dmaDesc++;
513: i++;
514: OSWriteSwapInt32( &dmaDesc->start, 0, physSeg.location + len );
515: OSWriteSwapInt32( &dmaDesc->length, 0, physSeg.length - len );
516: }
517:
518: bytesLeft -= physSeg.length;
519: offset += physSeg.length;
520: }
521:
522: if ( bytesLeft != 0 )
523: {
524: return false;
525: }
526:
527: /*
528: * Note: ATAPI always transfers even byte-counts. Send the extra byte to/from the bit-bucket
529: * if the requested transfer length is odd.
530: */
531: if ( dmaReqLength & 1 )
532: {
533: if ( i == numDescriptors ) return false;
534:
535: dmaDesc++;
536: OSWriteSwapInt32( &dmaDesc->start, 0, bitBucketAddrPhys );
537: OSWriteSwapInt32( &dmaDesc->length, 0, 1 );
538: }
539:
540:
541: dmaDesc--;
542: dmaDesc->length |= 0x80;
543:
544: pciWriteLong( ((busNum == 0) ? 0x74 : 0x7C), dmaDescriptorsPhys );
545:
546: return true;
547: }
548:
549:
550: /*
551: *
552: *
553: */
554: bool AppleATAUltra646::startDma( IOATACommand * )
555: {
556: UInt32 reg;
557: UInt32 cfgReg;
558:
559: if ( dmaReqLength != 0 )
560: {
561: reg = (busNum == 0) ? 0x70 : 0x78;
562: cfgReg = pciReadLong( reg );
563: cfgReg &= ~0x08;
564: cfgReg |= 0x01 | ((dmaIsWrite == false) ? 0x08 : 0x00);
565: pciWriteLong( reg, cfgReg );
566: }
567: return true;
568: }
569:
570:
571: /*
572: *
573: *
574: */
575: bool AppleATAUltra646::stopDma( IOATACommand *, UInt32 *transferCount )
576: {
577: UInt32 reg;
578: UInt32 cfgReg;
579:
580: *transferCount = 0;
581:
582: if ( dmaReqLength == 0 )
583: {
584: return true;
585: }
586:
587: reg = (busNum == 0) ? 0x70 : 0x78;
588: cfgReg = pciReadLong( reg );
589: cfgReg &= ~0x01;
590: pciWriteLong( reg, cfgReg );
591:
592: *transferCount = dmaReqLength;
593:
594: return true;
595: }
596:
597:
598: /*
599: *
600: *
601: */
602: void AppleATAUltra646::disableControllerInterrupts()
603: {
604: interruptEventSource->disable();
605: }
606:
607: /*
608: *
609: *
610: */
611: void AppleATAUltra646::enableControllerInterrupts()
612: {
613: interruptEventSource->enable();
614: }
615:
616: /*
617: *
618: *
619: */
620: void AppleATAUltra646::free()
621: {
622: UInt32 i;
623:
624: if ( interruptEventSource != 0 )
625: {
626: interruptEventSource->disable();
627: interruptEventSource->release();
628: }
629:
630: if ( timerEventSource != 0 )
631: {
632: timerEventSource->release();
633: }
634:
635: for (i = 0; i < 2; i++ )
636: {
637: if ( ioMapATA[i] != 0 ) ioMapATA[i]->release();
638: }
639:
640: if ( dmaDescriptors != 0 )
641: {
642: kfree( (void *)dmaDescriptors, page_size );
643: }
644: }
645:
646: /*
647: *
648: *
649: */
650: void AppleATAUltra646::writeATAReg( UInt32 regIndex, UInt32 regValue )
651: {
652: if ( regIndex == 0 )
653: {
654: *(volatile UInt16 *)ioBaseATA[0] = regValue;
655: }
656: else if ( regIndex < ataRegDeviceControl )
657: {
658: *((volatile UInt8 *)ioBaseATA[0] + regIndex) = regValue;
659: }
660: else
661: {
662: *((volatile UInt8 *)ioBaseATA[1] + regIndex - ataRegDeviceControl + 2) = regValue;
663: }
664: eieio();
665: }
666:
667: UInt32 AppleATAUltra646::readATAReg( UInt32 regIndex )
668: {
669: if ( regIndex == 0 )
670: {
671: return *(volatile UInt16 *)ioBaseATA[0];
672: }
673: else if ( regIndex < ataRegDeviceControl )
674: {
675: return *((volatile UInt8 *)ioBaseATA[0] + regIndex);
676: }
677:
678: return *((volatile UInt8 *)ioBaseATA[1] + regIndex - ataRegDeviceControl + 2);
679: }
680:
681: /*
682: *
683: *
684: */
685: UInt32 AppleATAUltra646::pciReadByte( UInt32 reg )
686: {
687: volatile union
688: {
689: unsigned long word;
690: unsigned char byte[4];
691: } data;
692:
693: data.word = provider->configRead32( reg );
694: return data.byte[3 - (reg & 0x03)];
695: }
696:
697: void AppleATAUltra646::pciWriteByte( UInt32 reg, UInt32 value )
698: {
699: volatile union
700: {
701: unsigned long word;
702: unsigned char byte[4];
703: } data;
704:
705: UInt32 regWord;
706:
707: regWord = reg & ~0x03;
708:
709: data.word = provider->configRead32( regWord );
710: data.word = OSReadSwapInt32( &data.word, 0 );
711:
712: switch (regWord)
713: {
714: case Ultra646CFR:
715: data.byte[Ultra646CFR & 0x03] &= ~Ultra646CFR_IDEIntPRI;
716: break;
717: case Ultra646DRWTIM0:
718: data.byte[Ultra646ARTTIM23 & 0x03] &= ~Ultra646ARTTIM23_IDEIntSDY;
719: break;
720: case Ultra646BMIDECR0:
721: data.byte[Ultra646MRDMODE & 0x03 ] &= ~(Ultra646MRDMODE_IDEIntPRI | Ultra646MRDMODE_IDEIntSDY);
722: data.byte[Ultra646BMIDESR0 & 0x03] &= ~(Ultra646BMIDESR0_DMAIntPRI | Ultra646BMIDESR0_DMAErrorPRI);
723: break;
724: case Ultra646BMIDECR1:
725: data.byte[Ultra646BMIDESR1 & 0x03] &= ~(Ultra646BMIDESR1_DMAIntSDY | Ultra646BMIDESR1_DMAErrorSDY);
726: break;
727: }
728: data.byte[reg & 0x03] = value;
729:
730: data.word = OSReadSwapInt32(&data.word, 0);
731:
732: provider->configWrite32( regWord, data.word );
733: }
734:
735: UInt32 AppleATAUltra646::pciReadLong( UInt32 reg )
736: {
737: return provider->configRead32( reg );
738: }
739:
740: void AppleATAUltra646::pciWriteLong( UInt32 reg, UInt32 value )
741: {
742: provider->configWrite32( reg, value );
743: }
744:
745: /* These overrides take care of OpenFirmware referring to the controller
746: * as a child of the PCI device, "ata-4" */
747:
748: bool AppleATAUltra646::getPath( char * path, int * length,
749: const IORegistryPlane * plane ) const
750: {
751: if (pathProvider && (plane == gIODTPlane))
752: return pathProvider->getPath(path, length, plane);
753: else
754: return super::getPath(path, length, plane);
755: }
756:
757: IOService * AppleATAUltra646::matchLocation( IOService * client )
758: {
759: if (pathProvider)
760: return pathProvider;
761: else
762: return super::matchLocation(client);
763: }
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