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1.1 root 1: /*
2: * Copyright (c) 1998-2000 Apple Computer, Inc. All rights reserved.
3: *
4: * @APPLE_LICENSE_HEADER_START@
5: *
6: * The contents of this file constitute Original Code as defined in and
7: * are subject to the Apple Public Source License Version 1.1 (the
8: * "License"). You may not use this file except in compliance with the
9: * License. Please obtain a copy of the License at
10: * http://www.apple.com/publicsource and read it before using this file.
11: *
12: * This Original Code and all software distributed under the License are
13: * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14: * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15: * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16: * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17: * License for the specific language governing rights and limitations
18: * under the License.
19: *
20: * @APPLE_LICENSE_HEADER_END@
21: */
22: /*
23: * PCI Control registers for Cmd646X chipset
24: *
25: */
26: #define Ultra646CFR 0x50 /* Configuration */
27: #define Ultra646CFR_DSA1 0x40
28: #define Ultra646CFR_IDEIntPRI 0x04
29:
30: #define Ultra646CNTRL 0x51 /* Drive 0/1 Control Register */
31: #define Ultra646CNTRL_Drive1ReadAhead 0x80
32: #define Ultra646CNTRL_Drive0ReadAhead 0x40
33: #define Ultra646CNTRL_EnableSDY 0x08
34: #define Ultra646CNTRL_EnablePRI 0x04
35:
36: #define Ultra646CMDTIM 0x52 /* Task file timing (all drives) */
37: #define Ultra646CMDTIM_Drive01CmdActive 0xF0
38: #define Ultra646CMDTIM_Drive01CmdRecovery 0x0F
39:
40: #define Ultra646ARTTIM0 0x53 /* Drive 0 Address Setup */
41: #define Ultra646ARTTIM0_Drive0AddrSetup 0xC0
42:
43: #define Ultra646DRWTIM0 0x54 /* Drive 0 Data Read/Write - DACK Time */
44: #define Ultra646DRWTIM0_Drive0DataActive 0xF0
45: #define Ultra646DRWTIM0_Drive0DataRecovery 0x0F
46:
47: #define Ultra646ARTTIM1 0x55 /* Drive 1 Address Setup */
48: #define Ultra646ARTTIM1_Drive1AddrSetup 0xC0
49:
50: #define Ultra646DRWTIM1 0x56 /* Drive 1 Data Read/Write - DACK Time */
51: #define Ultra646DRWTIM1_Drive1DataActive 0xF0
52: #define Ultra646DRWTIM1_Drive1DataRecover 0x0F
53:
54: #define Ultra646ARTTIM23 0x57 /* Drive 2/3 Control/Status */
55: #define Ultra646ARTTIM23_AddrSetup 0xC0
56: #define Ultra646ARTTIM23_IDEIntSDY 0x10
57: #define Ultra646ARTTIM23_Drive3ReadAhead 0x08
58: #define Ultra646ARTTIM23_Drive2ReadAhead 0x04
59:
60: #define Ultra646DRWTIM2 0x58 /* Drive 2 Read/Write - DACK Time */
61: #define Ultra646DRWTIM2_Drive2DataActive 0xF0
62: #define Ultra646DRWTIM2_Drive2DataRecovery 0x0F
63:
64: #define Ultra646BRST 0x59 /* Read Ahead Count */
65:
66: #define Ultra646DRWTIM3 0x5B /* Drive 3 Read/Write - DACK Time */
67: #define Ultra646DRWTIM3_Drive3DataActive 0xF0
68: #define Ultra646DRWTIM3_Drive3DataRecover 0x0F
69:
70: #define Ultra646BMIDECR0 0x70 /* BusMaster Command Register - Primary */
71: #define Ultra646BMIDECR0_PCIWritePRI 0x08
72: #define Ultra646BMIDECR0_StartDMAPRI 0x01
73:
74: #define Ultra646MRDMODE 0x71 /* DMA Master Read Mode Select */
75: #define Ultra646MRDMODE_PCIReadMask 0x03
76: #define Ultra646MRDMODE_PCIRead 0x00
77: #define Ultra646MRDMODE_PCIReadMultiple 0x01
78: #define Ultra646MRDMODE_IDEIntPRI 0x04
79: #define Ultra646MRDMODE_IDEIntSDY 0x08
80: #define Ultra646MRDMODE_IntEnablePRI 0x10
81: #define Ultra646MRDMODE_IntEnableSDY 0x20
82: #define Ultra646MRDMODE_ResetAll 0x40
83:
84: #define Ultra646BMIDESR0 0x72 /* BusMaster Status Register - Primary */
85: #define Ultra646BMIDESR0_Simplex 0x80
86: #define Ultra646BMIDESR0_Drive1DMACap 0x40
87: #define Ultra646BMIDESR0_Drive0DMACap 0x20
88: #define Ultra646BMIDESR0_DMAIntPRI 0x04
89: #define Ultra646BMIDESR0_DMAErrorPRI 0x02
90: #define Ultra646BMIDESR0_DMAActivePRI 0x01
91:
92: #define Ultra646UDIDETCR0 0x73 /* Ultra DMA Timing Control Register - Primary */
93: #define Ultra646UDIDETCR0_Drive1UDMACycleTime 0xC0
94: #define Ultra646UDIDETCR0_Drive0UDMACycleTime 0x30
95: #define Ultra646UDIDETCR0_Drive1UDMAEnable 0x02
96: #define Ultra646UDIDETCR0_Drive0UDMAEnable 0x01
97:
98: #define Ultra646DTPR0 0x74 /* Descriptor Table Pointer - Primary */
99:
100: #define Ultra646BMIDECR1 0x78 /* BusMaster Command Register - Secondary */
101: #define Ultra646BMIDECR1_PCIWriteSDY 0x08
102: #define Ultra646BMIDECR1_StartDMASDY 0x01
103:
104: #define Ultra646BMIDESR1 0x7A /* BusMaster Status Register - Secondary */
105: #define Ultra646BMIDESR1_Simplex 0x80
106: #define Ultra646BMIDESR1_Drive3DMACap 0x40
107: #define Ultra646BMIDESR1_Drive2DMACap 0x20
108: #define Ultra646BMIDESR1_DMAIntSDY 0x04
109: #define Ultra646BMIDESR1_DMAErrorSDY 0x02
110: #define Ultra646BMIDESR1_DMAActiveSDY 0x01
111:
112: #define Ultra646UDIDETCR1 0x7B /* Ultra DMA Timing Control Register - Secondary */
113: #define Ultra646UDIDETCR1_Drive3UDMACycleTime 0xC0
114: #define Ultra646UDIDETCR1_Drive2UDMACycleTime 0x30
115: #define Ultra646UDIDETCR1_Drive3UDMAEnable 0x02
116: #define Ultra646UDIDETCR1_Drive2UDMAEnable 0x01
117:
118: #define Ultra646DTPR1 0x7C /* Descriptor Table Pointer - Primary */
119:
120: typedef struct
121: {
122: UInt32 cntrlReg;
123: UInt32 arttimReg;
124: UInt32 cmdtimReg;
125: UInt32 drwtimRegPIO;
126: UInt32 drwtimRegDMA;
127: UInt32 udidetcrReg;
128: } Ultra646Regs;
129:
130:
131: typedef struct
132: {
133: UInt32 start;
134: UInt32 length;
135: } Ultra646Descriptor;
136:
137:
138: #define IDE_SYSCLK_NS 30
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