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1.1 root 1: /*
2: * Copyright (c) 1998-2000 Apple Computer, Inc. All rights reserved.
3: *
4: * @APPLE_LICENSE_HEADER_START@
5: *
6: * The contents of this file constitute Original Code as defined in and
7: * are subject to the Apple Public Source License Version 1.1 (the
8: * "License"). You may not use this file except in compliance with the
9: * License. Please obtain a copy of the License at
10: * http://www.apple.com/publicsource and read it before using this file.
11: *
12: * This Original Code and all software distributed under the License are
13: * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14: * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15: * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16: * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17: * License for the specific language governing rights and limitations
18: * under the License.
19: *
20: * @APPLE_LICENSE_HEADER_END@
21: */
22: /*
23: * Copyright (c) 1998-1999 Apple Computer, Inc. All rights reserved.
24: *
25: * Keylargo Audio Hardware Registers and DAC3550 Hardware Registers
26: *
27: */
28:
29: #ifndef _DACA_HW_H
30: #define _DACA_HW_H
31:
32: /*
33: * I2S registers:
34: */
35:
36: #define kI2S0BaseOffset 0x10000
37: #define kI2S1BaseOffset 0x11000
38:
39: #define kI2SClockOffset 0x0003C
40: #define kI2S0ClockEnable (UInt32)(0x00000001<<12)
41: #define kI2S1ClockEnable (UInt32)(0x00000001<<19)
42: #define kI2S0InterfaceEnable (UInt32)(0x00000001<<13)
43: #define kI2S1InterfaceEnable (UInt32)(0x00000001<<20)
44:
45: #define kI2SIntCtlOffset 0x0000
46: #define kI2SSerialFormatOffset 0x0010
47: #define kI2SCodecMsgOutOffset 0x0020
48: #define kI2SCodecMsgInOffset 0x0030
49: #define kI2SFrameCountOffset 0x0040
50: #define kI2SFrameMatchOffset 0x0050
51: #define kI2SDataWordSizesOffset 0x0060
52: #define kI2SPeakLevelSelOffset 0x0070
53: #define kI2SPeakLevelIn0Offset 0x0080
54: #define kI2SPeakLevelIn1Offset 0x0090
55:
56: /*
57: * Status register:
58: */
59: #define kGPio12 0x00064
60: #define kHeadphoneBit 0x02
61:
62: /*
63: * interrupt control register definitions
64: */
65: enum {
66: kFrameCountEnable = (1<<31), // enable frame count interrupt
67: kFrameCountPending = (1<<30), // frame count interrupt pending
68: kMsgFlagEnable = (1<<29), // enable message flag interrupt
69: kMsgFlagPending = (1<<28), // message flag interrupt pending
70: kNewPeakEnable = (1<<27), // enable new peak interrupt
71: kNewPeakPending = (1<<26), // new peak interrupt pending
72: kClocksStoppedEnable = (1<<25), // enable clocks stopped interrupt
73: kClocksStoppedPending = (1<<24),// clocks stopped interrupt pending
74: kExtSyncErrorEnable = (1<<23), // enable external sync error interrupt
75: kExtSyncErrorPending = (1<<22), // external sync error interrupt pending
76: kExtSyncOKEnable = (1<<21), // enable external sync OK interrupt
77: kExtSyncOKPending = (1<<20), // external sync OK interrupt pending
78: kNewSampleRateEnable = (1<<19), // enable new sample rate interrupt
79: kNewSampleRatePending = (1<<18),// new sample rate interrupt pending
80: kStatusFlagEnable = (1<<17), // enable status flag interrupt
81: kStatusFlagPending = (1<<16) // status flag interrupt pending
82: };
83:
84: // serial format register definitions
85: enum {
86: kClockSourceMask = (3<<30), // mask off clock sources
87: kClockSource18MHz = (0<<30), // select 18 MHz clock base
88: kClockSource45MHz = (1<<30), // select 45 MHz clock base
89: kClockSource49MHz = (2<<30), // select 49 MHz clock base
90: kMClkDivisorShift = 24, // shift to position value in MClk divisor field
91: kMClkDivisorMask = (0x1F<<24),// mask MClk divisor field
92: kMClkDivisor1 = (0x14<<24), // MClk == clock source
93: kMClkDivisor3 = (0x13<<24), // MClk == clock source/3
94: kMClkDivisor5 = (0x12<<24), // MClk == clock source/5
95: kSClkDivisorShift = 20, // shift to position value in SClk divisor field
96: kSClkDivisorMask = (0xF<<20), // mask SClk divisor field
97: kSClkDivisor1 = (8<<20), // SClk == MClk
98: kSClkDivisor3 = (9<<20), // SClk == MClk/3
99: kSClkMaster = (1<<19), // SClk in master mode
100: kSClkSlave = (0<<19), // SClk in slave mode
101: kSerialFormatShift = 16, // shift to position value in I2S serial format field
102: kSerialFormatMask = (7<<16), // mask serial format field
103: kSerialFormatSony = (0<<16), // Sony mode
104: kSerialFormat64x = (1<<16), // I2S 64x mode
105: kSerialFormat32x = (2<<16), // I2S 32x mode
106: kSerialFormatDAV = (4<<16), // DAV mode
107: kSerialFormatSiliLabs = (5<<16), // Silicon Labs mode
108: kExtSampleFreqIntShift = 12, // shift to position for external sample frequency interrupt
109: kExtSampleFreqIntMask = (0xF<<12), // mask external sample frequency interrupt field
110: kExtSampleFreqMask = 0xFFF // mask for external sample frequency
111: };
112:
113: // codec mesage in and out registers are not supported
114: // data word sizes
115: enum {
116: kNumChannelsInShift = 24, // shift to get to num channels in
117: kNumChannelsInMask = (0x1F<<24), // mask num channels in field
118: kDataInSizeShift = 16, // shift to get to data in size
119: kDataInSizeMask = (3<<16), // mask data in size
120: kDataIn16 = (0<<16), // 16 bit audio data in
121: kDataIn24 = (3<<16), // 24 bit audio data in
122: kNumChannelsOutShift = 8, // shift to get to num channels out
123: kNumChannelsOutMask = (0x1F<<8), // mask num channels out field
124: kDataOutSizeShift = 0, // shift to get to data out size
125: kDataOutSizeMask = (3<<0), // mask data out size
126: kDataOut16 = (0<<0), // 16 bit audio data out
127: kDataOut24 = (3<<0) // 24 bit audio data out
128: };
129:
130: // peak level subframe select register is not supported
131: // peak level in meter registers
132: enum {
133: kNewPeakInShift = 31, // shift to get to new peak in
134: kNewPeakInMask = (1<<31), // mask new peak in bit
135: kHoldPeakInShift = 30, // shift to get to peak hold
136: kHoldPeakInMask = (1<<30), // mask hold peak value
137: kHoldPeakInEnable = (0<<30), // enable the hold peak register
138: kHoldPeakInDisable = (1<<30), // disable the hold peak register (from updating)
139: kPeakValueMask = 0x00FFFFFF // mask to get peak value
140: };
141:
142: enum {
143: // 12c bus address for the chip and sub-addresses for registers
144: i2cBusAddrDAC3550A = 0x4d,
145: i2cBusSubAddrSR_REG = 0x01,
146: i2cBusSubAddrAVOL = 0x02,
147: i2cBusSubaddrGCFG = 0x03,
148:
149: // Sample Rate Control, 8 bit register
150: kPowerOnDefaultSR_REG = 0x00,
151:
152: kLeftLRSelSR_REG = 0x00, // left channel default
153: kRightLRSelSR_REG = 0x10, // right channel
154: kLRSelSR_REGMask = 0x10,
155:
156: kNoDelaySPSelSR_REG = 0x00, // default
157: k1BitDelaySPSelSR_REG = 0x08,
158: kDelaySPSelSR_REGMask = 0x08,
159:
160: kSRC_48SR_REG = 0x00, // 32 - 48 KHz default
161: kSRC_32SR_REG = 0x01, // 26 - 32 KHz
162: kSRC_24SR_REG = 0x02, // 20 - 26 KHz
163: kSRC_16SR_REG = 0x03, // 14 - 20 KHz
164: kSRC_12SR_REG = 0x04, // 10 - 14 KHz
165: kSRC_8SR_REG = 0x05, // 8 - 10 KHz
166: kSRC_Auto_REG = 0x06, // autoselect
167: kSampleRateControlMask = 0x07,
168:
169: // Analog Volume, 16 bit register
170: kMuteVolumeLevel_VOL = 0x00, // Mute
171: kMinVolumeLevel_VOL = 0x01, // -75 dB
172: kMaxVolumeLevel_VOL = 0x38, // 18 dB
173: kVolumeRangeLevel_VOL = kMaxVolumeLevel_VOL - kMinVolumeLevel_VOL,
174:
175: kPowerOnDefaultAVOL = 0x2C2C, // 0 dB
176: kLeftAVOLShift = 8,
177: kRightAVOLShift = 0,
178: kRightAVOLMask = 0x003F, // range -75 to +18 dB, default 0 dB
179: kLeftAVOLMask = 0x3F00, // range -75 to +18 dB, default 0 dB
180:
181: // Global Configuration, 8 bit register
182: kPowerOnDefaultGCFG = 0x04,
183:
184: kInvertRightAmpGCFG = 0x01, // 0 -> right power amplifier not inverted (default)
185: kMonoGCFG = 0x02, // 0 -> stereo (default), 1 -> mono
186: kDACOnGCFG = 0x04, // 1 -> DAC on (default)
187: kAuxOneGCFG = 0x08, // 0 -> AUX1 off (default)
188: kAuxTwoGCFG = 0x10, // 0 -> AUX2 off (default)
189: kLowPowerGCFG = 0x20, // 0 -> normal power (default), 1 -> low power
190: kSelect5VoltGCFG = 0x40, // 0 -> 3 Volt (default), 1 -> 5 Volt
191:
192: kNoChangeMask = 0x00
193: };
194:
195: #endif // _DACA_HW_H
196:
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