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1.1 ! root 1: /* ! 2: * Copyright (c) 1998-2000 Apple Computer, Inc. All rights reserved. ! 3: * ! 4: * @APPLE_LICENSE_HEADER_START@ ! 5: * ! 6: * The contents of this file constitute Original Code as defined in and ! 7: * are subject to the Apple Public Source License Version 1.1 (the ! 8: * "License"). You may not use this file except in compliance with the ! 9: * License. Please obtain a copy of the License at ! 10: * http://www.apple.com/publicsource and read it before using this file. ! 11: * ! 12: * This Original Code and all software distributed under the License are ! 13: * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER ! 14: * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, ! 15: * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, ! 16: * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the ! 17: * License for the specific language governing rights and limitations ! 18: * under the License. ! 19: * ! 20: * @APPLE_LICENSE_HEADER_END@ ! 21: */ ! 22: /* ! 23: * Copyright (c) 1996 NeXT Software, Inc. All rights reserved. ! 24: * ! 25: * i82557HW.h - Intel 82557/82558 chip-related definitions ! 26: * ! 27: * HISTORY ! 28: * Jan 22, 1996 Dieter Siegmund at NeXT ([email protected]) ! 29: * Created. ! 30: */ ! 31: ! 32: #ifndef _I82557HW_H ! 33: #define _I82557HW_H ! 34: ! 35: #include <net/etherdefs.h> ! 36: ! 37: //------------------------------------------------------------------------- ! 38: // Misc definitions. ! 39: //------------------------------------------------------------------------- ! 40: ! 41: #define DWORD_ALIGNMENT 4 ! 42: #define WORD_ALIGNMENT 2 ! 43: #define PARAGRAPH_ALIGNMENT 16 ! 44: #define CACHE_ALIGNMENT 32 ! 45: ! 46: #define C_NULL (~0) ! 47: ! 48: #define PCI_CFID_OFFSET 0x00 ! 49: #define PCI_CFCS_OFFSET 0x04 ! 50: #define PCI_BAR0_OFFSET 0x10 ! 51: #define PCI_CFID_INTEL82557 0x12298086 ! 52: ! 53: typedef enum { ! 54: MEDIUM_TYPE_10_HD = 0, ! 55: MEDIUM_TYPE_10_FD, ! 56: MEDIUM_TYPE_TX_HD, ! 57: MEDIUM_TYPE_TX_FD, ! 58: MEDIUM_TYPE_T4, ! 59: MEDIUM_TYPE_AUTO, ! 60: MEDIUM_TYPE_INVALID, ! 61: } mediumType_t; ! 62: ! 63: //------------------------------------------------------------------------- ! 64: // SCB status word. ! 65: // Offset 0, 16-bit, RW. ! 66: //------------------------------------------------------------------------- ! 67: typedef UInt16 scb_status_t; ! 68: #define SCB_STATUS_CX BIT(15) // command block with 'I' bit set. ! 69: #define SCB_STATUS_FR BIT(14) // RU finished receiving a frame. ! 70: #define SCB_STATUS_CNA BIT(13) // CU active to suspended/idle. ! 71: #define SCB_STATUS_RNR BIT(12) // RU no longer in ready state. ! 72: #define SCB_STATUS_MDI BIT(11) // MDI read/write cycle is done. ! 73: #define SCB_STATUS_SWI BIT(10) // software interrupt. ! 74: #define SCB_STATUS_ER BIT(9) // early receive interrupt. ! 75: #define SCB_STATUS_FCP BIT(8) // flow control pause interrupt. ! 76: #define SCB_STATUS_INT_MASK 0xff00 // mask for all interrupt bits. ! 77: ! 78: #define SCB_STATUS_CUS_SHIFT 6 ! 79: #define SCB_STATUS_CUS_MASK CSR_MASK(SCB_STATUS_CUS, 0x3) ! 80: #define SCB_CUS_IDLE 0 ! 81: #define SCB_CUS_SUSPEND 1 ! 82: #define SCB_CUS_ACTIVE 2 ! 83: ! 84: #define SCB_STATUS_RUS_SHIFT 2 ! 85: #define SCB_STATUS_RUS_MASK CSR_MASK(SCB_STATUS_RUS, 0xf) ! 86: #define SCB_RUS_IDLE 0 ! 87: #define SCB_RUS_SUSPEND 1 ! 88: #define SCB_RUS_NO_RESOURCES 2 ! 89: #define SCB_RUS_READY 4 ! 90: #define SCB_RUS_SUSPEND_NO_RBDS 9 ! 91: #define SCB_RUS_NO_RBDS 10 ! 92: #define SCB_RUS_READY_NO_RBDS 12 ! 93: ! 94: //------------------------------------------------------------------------- ! 95: // SCB interrupt control byte. ! 96: // Offset 3, 8-bit, RW. ! 97: //------------------------------------------------------------------------- ! 98: typedef UInt8 scb_interrupt_t; ! 99: #define SCB_INTERRUPT_CX BIT(7) // interrupt masks ! 100: #define SCB_INTERRUPT_FR BIT(6) ! 101: #define SCB_INTERRUPT_CNA BIT(5) ! 102: #define SCB_INTERRUPT_RNR BIT(4) ! 103: #define SCB_INTERRUPT_ER BIT(3) ! 104: #define SCB_INTERRUPT_FCP BIT(2) ! 105: #define SCB_INTERRUPT_SI BIT(1) ! 106: #define SCB_INTERRUPT_M BIT(0) ! 107: ! 108: //------------------------------------------------------------------------- ! 109: // SCB command byte. ! 110: // Offset 2, 8-bit, RW. ! 111: //------------------------------------------------------------------------- ! 112: typedef UInt8 scb_command_t; ! 113: #define SCB_COMMAND_CUC_SHIFT 4 ! 114: #define SCB_COMMAND_CUC_MASK CSR_MASK(SCB_COMMAND_CUC, 0xf) ! 115: #define SCB_CUC_NOP 0 ! 116: #define SCB_CUC_START 1 ! 117: #define SCB_CUC_RESUME 2 ! 118: #define SCB_CUC_LOAD_DUMP_ADDR 4 ! 119: #define SCB_CUC_DUMP_STAT 5 ! 120: #define SCB_CUC_LOAD_BASE 6 ! 121: #define SCB_CUC_DUMP_RESET_STAT 7 ! 122: #define SCB_CUC_STATIC_RESUME 10 ! 123: ! 124: #define SCB_COMMAND_RUC_SHIFT 0 ! 125: #define SCB_COMMAND_RUC_MASK CSR_MASK(SCB_COMMAND_RUC, 0x7) ! 126: #define SCB_RUC_NOP 0 ! 127: #define SCB_RUC_START 1 ! 128: #define SCB_RUC_RESUME 2 ! 129: #define SCB_RUC_DMA_REDIRECT 3 ! 130: #define SCB_RUC_ABORT 4 ! 131: #define SCB_RUC_LOAD_HDS 5 ! 132: #define SCB_RUC_LOAD_BASE 6 ! 133: #define SCB_RUC_RBD_RESUME 7 ! 134: ! 135: //------------------------------------------------------------------------- ! 136: // MDI control register. ! 137: // Offset 0x10, 32-bit, RW. ! 138: //------------------------------------------------------------------------- ! 139: typedef UInt32 mdi_control_t; ! 140: #define MDI_CONTROL_INT_ENABLE BIT(29) // interrupt enable. ! 141: #define MDI_CONTROL_READY BIT(28) // ready bit. ! 142: #define MDI_CONTROL_OPCODE_SHIFT 26 ! 143: #define MDI_CONTROL_OPCODE_MASK CSR_MASK(MDI_CONTROL_OPCODE, 0x3) ! 144: #define MDI_CONTROL_OP_WRITE 1 ! 145: #define MDI_CONTROL_OP_READ 2 ! 146: #define MDI_CONTROL_PHYADDR_SHIFT 21 ! 147: #define MDI_CONTROL_PHYADDR_MASK CSR_MASK(MDI_CONTROL_PHYADDR, 0x1f) ! 148: #define MDI_CONTROL_REGADDR_SHIFT 16 ! 149: #define MDI_CONTROL_REGADDR_MASK CSR_MASK(MDI_CONTROL_REGADDR, 0x1f) ! 150: #define MDI_CONTROL_DATA_SHIFT 0 ! 151: #define MDI_CONTROL_DATA_MASK CSR_MASK(MDI_CONTROL_DATA, 0xffff) ! 152: ! 153: //------------------------------------------------------------------------- ! 154: // EEPROM control register. ! 155: // Offset 0xE, 16-bit, RW. ! 156: //------------------------------------------------------------------------- ! 157: typedef UInt16 eeprom_control_t; ! 158: #define EEPROM_CONTROL_EEDO BIT(3) ! 159: #define EEPROM_CONTROL_EEDI BIT(2) ! 160: #define EEPROM_CONTROL_EECS BIT(1) ! 161: #define EEPROM_CONTROL_EESK BIT(0) ! 162: ! 163: //------------------------------------------------------------------------- ! 164: // Flow control threshold register. ! 165: // Offset 0x19, 8-bit, RW. ! 166: //------------------------------------------------------------------------- ! 167: #define FC_THRESHOLD_SHIFT 0 ! 168: #define FC_THRESHOLD_MASK CSR_MASK(FC_THRESHOLD, 0x7) ! 169: #define FC_THRESHOLD_512 0 ! 170: #define FC_THRESHOLD_1024 1 ! 171: #define FC_THRESHOLD_1280 2 ! 172: #define FC_THRESHOLD_1536 3 ! 173: ! 174: //------------------------------------------------------------------------- ! 175: // Flow control command register. ! 176: // Offset 0x20, 8-bit, RW. ! 177: //------------------------------------------------------------------------- ! 178: #define FC_XON BIT(0) ! 179: #define FC_XOFF BIT(1) ! 180: #define FC_FULL BIT(2) ! 181: #define FC_PAUSED BIT(3) ! 182: #define FC_PAUSED_LOW BIT(4) ! 183: ! 184: //------------------------------------------------------------------------- ! 185: // Generic command block definition. ! 186: //------------------------------------------------------------------------- ! 187: #define CB_NOP 0 ! 188: #define CB_IA_ADDRESS 1 ! 189: #define CB_CONFIGURE 2 ! 190: #define CB_MULTICAST 3 ! 191: #define CB_TRANSMIT 4 ! 192: #define CB_LOAD_MICROCODE 5 ! 193: #define CB_DUMP 6 ! 194: #define CB_DIAGNOSE 7 ! 195: ! 196: typedef UInt16 cb_status_t; ! 197: #define CB_STATUS_C BIT(15) // command complete. ! 198: #define CB_STATUS_OK BIT(13) // DMA OK. ! 199: ! 200: typedef UInt16 cb_command_t; ! 201: #define CB_EL BIT(15) // end of list. ! 202: #define CB_S BIT(14) // suspend bit. ! 203: #define CB_I BIT(13) // interrupt bit. ! 204: #define CB_CMD_SHIFT 0 ! 205: #define CB_CMD_MASK CSR_MASK(CB_CMD, 0x7) ! 206: ! 207: #define CB_CMD_NOP 0x0 ! 208: #define CB_CMD_IASETUP 0x1 ! 209: #define CB_CMD_CONFIGURE 0x2 ! 210: #define CB_CMD_MCSETUP 0x3 ! 211: #define CB_CMD_TRANSMIT 0x4 ! 212: ! 213: static __inline__ char * ! 214: CUCommandString(int cmd) ! 215: { ! 216: char * s[] = { ! 217: "nop", ! 218: "iasetup", ! 219: "configure", ! 220: "mcsetup", ! 221: "transmit" ! 222: }; ! 223: return (s[cmd]); ! 224: } ! 225: ! 226: typedef struct { ! 227: volatile cb_status_t status; ! 228: volatile cb_command_t command; ! 229: IOPhysicalAddress link; ! 230: } cbHeader_t; ! 231: ! 232: //------------------------------------------------------------------------- ! 233: // Configure command. ! 234: //------------------------------------------------------------------------- ! 235: #define CB_CONFIG_BYTE_COUNT 22 ! 236: ! 237: #define CB_CB0_BYTE_COUNT_SHIFT 0 ! 238: #define CB_CB0_BYTE_COUNT_MASK CSR_MASK(CB_CB0_BYTE_COUNT, 0x3f) ! 239: ! 240: #define CB_CB1_TX_FIFO_LIMIT_SHIFT 4 ! 241: #define CB_CB1_TX_FIFO_LIMIT_MASK CSR_MASK(CB_CB1_TX_FIFO_LIMIT, 0xf) ! 242: #define CB_CB1_RX_FIFO_LIMIT_SHIFT 0 ! 243: #define CB_CB1_RX_FIFO_LIMIT_MASK CSR_MASK(CB_CB1_RX_FIFO_LIMIT, 0xf) ! 244: #define CB_CB1_TX_FIFO_0 8 // 0 bytes ! 245: #define CB_CB1_RX_FIFO_64 8 // 64 bytes ! 246: ! 247: #define CB_CB2_ADAPTIVE_IFS_SHIFT 0 ! 248: #define CB_CB2_ADAPTIVE_IFS_MASK CSR_MASK(CB_CB2_ADAPTIVE_IFS, 0xff) ! 249: ! 250: #define CB_CB3_TERM_ON_CL BIT(3) ! 251: #define CB_CB3_READ_AL_ENABLE BIT(2) ! 252: #define CB_CB3_TYPE_ENABLE BIT(1) ! 253: #define CB_CB3_MWI_ENABLE BIT(0) ! 254: ! 255: #define CB_CB4_RX_MIN_SHIFT 0 ! 256: #define CB_CB4_RX_MIN_MASK CSR_MASK(CB_CB4_RX_MIN, 0x7f) ! 257: ! 258: #define CB_CB5_DMBC_EN BIT(7) ! 259: #define CB_CB5_TX_MAX_SHIFT 0 ! 260: #define CB_CB5_TX_MAX_MASK CSR_MASK(CB_CB4_TX_MAX, 0x7f) ! 261: ! 262: #define CB_CB6_SAVE_BF BIT(7) ! 263: #define CB_CB6_DISC_OVER BIT(6) ! 264: #define CB_CB6_STD_STATS BIT(5) ! 265: #define CB_CB6_STD_TCB BIT(4) ! 266: #define CB_CB6_CI_INT BIT(3) ! 267: #define CB_CB6_TNO_INT BIT(2) ! 268: #define CB_CB6_NON_DIRECT_DMA BIT(1) ! 269: #define CB_CB6_LATE_SCB BIT(0) ! 270: ! 271: #define CB_CB7_DYNAMIC_TBD BIT(7) ! 272: #define CB_CB7_UNDERRUN_RETRY_SHIFT 1 ! 273: #define CB_CB7_UNDERRUN_RETRY_MASK CSR_MASK(CB_CB7_UNDERRUN_RETRY, 0x3) ! 274: #define CB_CB7_UNDERRUN_RETRY_1 1 ! 275: #define CB_CB7_UNDERRUN_RETRY_2 2 ! 276: #define CB_CB7_UNDERRUN_RETRY_3 3 ! 277: #define CB_CB7_DISC_SHORT_FRAMES BIT(0) ! 278: ! 279: #define CB_CB8_CSMA_EN BIT(0) ! 280: ! 281: #define CB_CB10_LOOPBACK_SHIFT 6 ! 282: #define CB_CB10_LOOPBACK_MASK CSR_MASK(CB_CB10_LOOPBACK, 0x3) ! 283: #define CB_CB10_PREAMBLE_SHIFT 4 ! 284: #define CB_CB10_PREAMBLE_MASK CSR_MASK(CB_CB10_PREAMBLE, 0x3) ! 285: #define CB_CB10_PREAMBLE_1_BYTE 0 ! 286: #define CB_CB10_PREAMBLE_3_BYTES 1 ! 287: #define CB_CB10_PREAMBLE_7_BYTES 2 ! 288: #define CB_CB10_PREAMBLE_15_BYTES 3 ! 289: #define CB_CB10_NSAI BIT(3) ! 290: ! 291: #define CB_CB11_LIN_PRIORITY_SHIFT 0 ! 292: #define CB_CB11_LIN_PRIORITY_MASK CSR_MASK(CB_CB11_PRIORITY, 0x7) ! 293: ! 294: #define CB_CB12_IFS_SHIFT 4 ! 295: #define CB_CB12_IFS_MASK CSR_MASK(CB_CB12_IFS, 0xf) ! 296: #define CB_CB12_IFS_96_BIT_TIMES 0x6 ! 297: #define CB_CB12_LIN_PRIORITY BIT(0) ! 298: ! 299: #define CB_CB13_FC_TYPE_LSB_SHIFT 0 ! 300: #define CB_CB13_FC_TYPE_LSB_MASK CSR_MASK(CB_CB13_FC_TYPE_LSB, 0xff) ! 301: #define CB_CB13_FC_TYPE_LSB_DEF 0 // 82558 compatible ! 302: ! 303: #define CB_CB14_FC_TYPE_MSB_SHIFT 0 ! 304: #define CB_CB14_FC_TYPE_MSB_MASK CSR_MASK(CB_CB14_FC_TYPE_MSB, 0xff) ! 305: #define CB_CB14_FC_TYPE_MSB_DEF 0xf2 // 82558 compatible ! 306: ! 307: #define CB_CB15_CRS_CDT BIT(7) ! 308: #define CB_CB15_BROADCAST_DISABLE BIT(1) ! 309: #define CB_CB15_PROMISCUOUS BIT(0) ! 310: ! 311: #define CB_CB16_FC_DELAY_LSB_SHIFT 0 ! 312: #define CB_CB16_FC_DELAY_LSB_MASK CSR_MASK(CB_CB16_FC_DELAY_LSB, 0xff) ! 313: #define CB_CB16_FC_DELAY_LSB_DEF 0 ! 314: ! 315: #define CB_CB17_FC_DELAY_MSB_SHIFT 0 ! 316: #define CB_CB17_FC_DELAY_MSB_MASK CSR_MASK(CB_CB17_FC_DELAY_MSB, 0xff) ! 317: #define CB_CB17_FC_DELAY_MSB_DEF 0x40 ! 318: ! 319: #define CB_CB18_LONG_RX_OK BIT(3) ! 320: #define CB_CB18_CRC_XFER BIT(2) ! 321: #define CB_CB18_PADDING BIT(1) ! 322: #define CB_CB18_STRIPPING BIT(0) ! 323: ! 324: #define CB_CB19_AUTO_FDX BIT(7) ! 325: #define CB_CB19_FORCE_FDX BIT(6) ! 326: #define CB_CB19_REJECT_FC BIT(5) ! 327: #define CB_CB19_RX_FC_RESTART BIT(4) ! 328: #define CB_CB19_RX_FC_RESTOP BIT(3) ! 329: #define CB_CB19_TX_FC BIT(2) ! 330: #define CB_CB19_MAGIC_PKT_WAKEUP BIT(1) ! 331: #define CB_CB19_ADDRESS_WAKEUP BIT(0) ! 332: ! 333: #define CB_CB20_MULTI_IA BIT(6) ! 334: #define CB_CB20_FC_ADDR_LSB_SHIFT 0 ! 335: #define CB_CB20_FC_ADDR_LSB_MASK CSR_MASK(CB_CB20_FC_ADDR_LSB, 0x1f) ! 336: #define CB_CB20_FC_ADDR_LSB_DEF 0x0f ! 337: ! 338: #define CB_CB21_MULTICAST_ALL BIT(3) ! 339: ! 340: typedef struct cb_configure { ! 341: cbHeader_t header; ! 342: UInt8 byte[24]; ! 343: } cb_configure_t; ! 344: ! 345: //------------------------------------------------------------------------- ! 346: // MC-Setup command. ! 347: //------------------------------------------------------------------------- ! 348: typedef struct cb_mcsetup { ! 349: cbHeader_t header; ! 350: UInt16 count; ! 351: enet_addr_t addrs[0]; ! 352: } cb_mcsetup_t; ! 353: ! 354: //------------------------------------------------------------------------- ! 355: // IA-Setup command. ! 356: //------------------------------------------------------------------------- ! 357: typedef struct cb_iasetup { ! 358: cbHeader_t header; ! 359: enet_addr_t addr; ! 360: } cb_iasetup_t; ! 361: ! 362: //------------------------------------------------------------------------- ! 363: // Port Commands. ! 364: // Enumerated port command values. ! 365: //------------------------------------------------------------------------- ! 366: typedef enum { ! 367: portReset_e = 0, ! 368: portSelfTest_e = 1, ! 369: portSelectiveReset_e = 2, ! 370: portDump_e = 3, ! 371: } port_command_t; ! 372: ! 373: #define PORT_ADDRESS_SHIFT 4 ! 374: #define PORT_ADDRESS_MASK CSR_MASK(PORT_FUNCTION, 0xfffffff) ! 375: ! 376: #define PORT_FUNCTION_SHIFT 0 ! 377: #define PORT_FUNCTION_MASK CSR_MASK(PORT_FUNCTION, 0xf) ! 378: ! 379: //------------------------------------------------------------------------- ! 380: // Port Self-Test ! 381: // Definition for self test area. ! 382: //------------------------------------------------------------------------- ! 383: #define PORT_SELFTEST_GENERAL BIT(12) ! 384: #define PORT_SELFTEST_DIAGNOSE BIT(5) ! 385: #define PORT_SELFTEST_REGISTER BIT(3) ! 386: #define PORT_SELFTEST_ROM BIT(2) ! 387: ! 388: typedef struct port_selftest_t { ! 389: UInt32 signature; ! 390: UInt32 results; ! 391: } port_selftest_t; ! 392: ! 393: /* ! 394: * Typedef: CSR_t ! 395: * ! 396: * Purpose: Control Status Registers block ! 397: * Communication to the chip occurs via this set of ! 398: * memory-mapped (also io-mapped, which we don't use) ! 399: * registers. ! 400: */ ! 401: typedef struct csr { ! 402: volatile scb_status_t status; ! 403: volatile scb_command_t command; ! 404: volatile scb_interrupt_t interrupt; ! 405: volatile IOPhysicalAddress pointer; ! 406: volatile UInt32 port; ! 407: volatile UInt16 flashControl; ! 408: volatile eeprom_control_t eepromControl; ! 409: volatile mdi_control_t mdiControl; ! 410: volatile UInt32 rxDMAByteCount; ! 411: volatile UInt8 earlyRxInterrupt; ! 412: volatile UInt8 flowControlThreshold; ! 413: volatile UInt8 flowControlCommand; ! 414: volatile UInt8 powerManagement; ! 415: } CSR_t; ! 416: ! 417: //------------------------------------------------------------------------- ! 418: // Structure containing error counters retrieved via: ! 419: // Dump Statistics Counters command, or ! 420: // Dump and Reset Statistics Counters command. ! 421: // ! 422: // NOTE: 82558 can return an extended set of statistics counters. ! 423: //------------------------------------------------------------------------- ! 424: typedef struct { ! 425: UInt32 tx_good_frames; ! 426: UInt32 tx_maxcol_errors; ! 427: UInt32 tx_late_collision_errors; ! 428: UInt32 tx_underrun_errors; ! 429: UInt32 tx_lost_carrier_sense_errors; ! 430: UInt32 tx_deferred; ! 431: UInt32 tx_single_collisions; ! 432: UInt32 tx_multiple_collisions; ! 433: UInt32 tx_total_collisions; ! 434: UInt32 rx_good_frames; ! 435: UInt32 rx_crc_errors; ! 436: UInt32 rx_alignment_errors; ! 437: UInt32 rx_resource_errors; ! 438: UInt32 rx_overrun_errors; ! 439: UInt32 rx_collision_detect_errors; ! 440: UInt32 rx_short_frame_errors; ! 441: UInt32 _status; ! 442: #define DUMP_STATUS 0x0 ! 443: #define DUMP_COMPLETE 0xa005 ! 444: #define DUMP_AND_RESET_COMPLETE 0xa007 ! 445: } errorCounters_t; ! 446: ! 447: //------------------------------------------------------------------------- ! 448: // RBD count dword. ! 449: // Offset 0, 32-bit, RW. ! 450: //------------------------------------------------------------------------- ! 451: typedef UInt32 rbd_count_t; ! 452: #define RBD_COUNT_EOF BIT(15) // end-of-frame bit. ! 453: #define RBD_COUNT_F BIT(14) // buffer fetch bit. ! 454: #define RBD_COUNT_SHIFT 0 ! 455: #define RBD_COUNT_MASK CSR_MASK(RBD_COUNT, 0x3fff) ! 456: ! 457: //------------------------------------------------------------------------- ! 458: // RBD size dword. ! 459: // Offset 0xC, 32-bit, RW. ! 460: //------------------------------------------------------------------------- ! 461: typedef UInt32 rbd_size_t; ! 462: #define RBD_SIZE_EL BIT(15) // EL bit. ! 463: #define RBD_SIZE_SHIFT 0 ! 464: #define RBD_SIZE_MASK CSR_MASK(RBD_SIZE, 0x3fff) ! 465: ! 466: //------------------------------------------------------------------------- ! 467: // RBD - receive buffer descriptor definition. ! 468: //------------------------------------------------------------------------- ! 469: typedef struct rbd { ! 470: volatile rbd_count_t count; ! 471: volatile IOPhysicalAddress link; ! 472: volatile IOPhysicalAddress buffer; ! 473: volatile rbd_size_t size; ! 474: ! 475: /* driver private */ ! 476: ! 477: struct rbd * _next; ! 478: IOPhysicalAddress _paddr; ! 479: struct mbuf * _mbuf; ! 480: UInt32 _pad; ! 481: } rbd_t; ! 482: ! 483: //------------------------------------------------------------------------- ! 484: // RFD status word. ! 485: // Offset 0, 16-bit, RW. ! 486: //------------------------------------------------------------------------- ! 487: typedef UInt16 rfd_status_t; ! 488: #define RFD_STATUS_C BIT(15) // complete bit. ! 489: #define RFD_STATUS_OK BIT(13) // OK bit. ! 490: #define RFD_STATUS_CRC_ERROR BIT(11) // CRC error bit. ! 491: #define RFD_STATUS_ALIGNMENT_ERROR BIT(10) // alignment error. ! 492: #define RFD_STATUS_NO_RESOURCES BIT(9) // no buffer space. ! 493: #define RFD_STATUS_DMA_OVERRUN BIT(8) // receive DMA overrun. ! 494: #define RFD_STATUS_FRAME_TOO_SHORT BIT(7) // frame too short. ! 495: #define RFD_STATUS_TYPE_FRAME BIT(5) // type/length bit. ! 496: #define RFD_STATUS_RX_ERROR BIT(4) // RX_ERR pin on PHY was set. ! 497: #define RFD_STATUS_NO_ADDR_MATCH BIT(2) // no address match. ! 498: #define RFD_STATUS_IA_MATCH BIT(1) // IA address match. ! 499: #define RFD_STATUS_COLLISION BIT(0) // receive collision. ! 500: ! 501: //------------------------------------------------------------------------- ! 502: // RFD command word. ! 503: // Offset 2, 16-bit, RW. ! 504: //------------------------------------------------------------------------- ! 505: typedef UInt16 rfd_command_t; ! 506: #define RFD_COMMAND_EL BIT(15) // EL bit. ! 507: #define RFD_COMMAND_S BIT(14) // suspend bit. ! 508: #define RFD_COMMAND_H BIT(4) // header RFD bit. ! 509: #define RFD_COMMAND_SF BIT(3) // flexible mode bit. ! 510: ! 511: //------------------------------------------------------------------------- ! 512: // RFD misc dword. ! 513: // Offset 0xC, 32-bit, RW. ! 514: //------------------------------------------------------------------------- ! 515: typedef UInt32 rfd_misc_t; ! 516: #define RFD_MISC_EOF BIT(15) // end-of-frame bit. ! 517: #define RFD_MISC_F BIT(14) // buffer fetch bit. ! 518: #define RFD_MISC_ACT_COUNT_SHIFT 0 ! 519: #define RFD_MISC_ACT_COUNT_MASK CSR_MASK(RFD_MISC_ACT_COUNT, 0x3fff) ! 520: #define RFD_MISC_SIZE_SHIFT 16 ! 521: #define RFD_MISC_SIZE_MASK CSR_MASK(RFD_MISC_SIZE, 0x3fff) ! 522: ! 523: //------------------------------------------------------------------------- ! 524: // RFD - receive frame descriptor definition. ! 525: //------------------------------------------------------------------------- ! 526: typedef struct rfd { ! 527: volatile rfd_status_t status; ! 528: volatile rfd_command_t command; ! 529: volatile IOPhysicalAddress link; ! 530: volatile IOPhysicalAddress rbdAddr; ! 531: volatile rfd_misc_t misc; // 16 bytes ! 532: ! 533: UInt32 _pad[2]; // pad it to 64 bytes ! 534: ! 535: /* driver private */ ! 536: ! 537: struct rfd * _next; ! 538: IOPhysicalAddress _paddr; ! 539: rbd_t _rbd; // 32 bytes ! 540: } rfd_t; ! 541: ! 542: //------------------------------------------------------------------------- ! 543: // TBD - Transmit Buffer Descriptor. ! 544: //------------------------------------------------------------------------- ! 545: typedef UInt16 tbd_size_t; ! 546: #define TBD_SIZE_EL BIT(15) // end of list ! 547: #define TBD_SIZE_SHIFT 0 ! 548: #define TBD_SIZE_MASK CSR_MASK(TBD_SIZE, 0x3fff) ! 549: ! 550: typedef struct tbd { ! 551: volatile IOPhysicalAddress addr; ! 552: volatile tbd_size_t size; ! 553: } tbd_t; ! 554: ! 555: //------------------------------------------------------------------------- ! 556: // TxCB Status Word. ! 557: // Offset 0, 16-bit, RW. ! 558: //------------------------------------------------------------------------- ! 559: typedef UInt16 tcb_status_t; ! 560: #define TCB_STATUS_C BIT(15) // complete bit ! 561: #define TCB_STATUS_OK BIT(13) // error free completion ! 562: #define TCB_STATUS_U BIT(12) // underrun bit ! 563: ! 564: //------------------------------------------------------------------------- ! 565: // TxCB Command Word. ! 566: // Offset 2, 16-bit, RW. ! 567: //------------------------------------------------------------------------- ! 568: typedef UInt16 tcb_command_t; ! 569: #define TCB_COMMAND_EL BIT(15) // end of list ! 570: #define TCB_COMMAND_S BIT(14) // suspend bit ! 571: #define TCB_COMMAND_I BIT(13) // interrupt bit ! 572: #define TCB_COMMAND_NC BIT(4) // CRC/Source Address control ! 573: #define TCB_COMMAND_SF BIT(3) // flexible mode bit ! 574: #define TCB_COMMAND_SHIFT 0 ! 575: #define TCB_COMMAND_MASK CSR_MASK(TCB_COMMAND, 0x7) ! 576: ! 577: //------------------------------------------------------------------------- ! 578: // TxCB Count Word. ! 579: // Offset 0xC, 16-bit, RW. ! 580: //------------------------------------------------------------------------- ! 581: typedef UInt16 tcb_count_t; ! 582: #define TCB_COUNT_EOF BIT(15) // whole frame in TCB ! 583: #define TCB_COUNT_SHIFT 0 ! 584: #define TCB_COUNT_MASK CSR_MASK(TCB_COUNT, 0x3fff) ! 585: ! 586: //------------------------------------------------------------------------- ! 587: // TxCB - Transmit Command Block. ! 588: //------------------------------------------------------------------------- ! 589: #define TBDS_PER_TCB 12 ! 590: #define TCB_TX_THRESHOLD 0xe0 ! 591: ! 592: typedef struct tcb { ! 593: volatile tcb_status_t status; ! 594: volatile tcb_command_t command; ! 595: volatile IOPhysicalAddress link; ! 596: volatile IOPhysicalAddress tbdAddr; ! 597: volatile tcb_count_t count; ! 598: volatile UInt8 threshold; ! 599: volatile UInt8 number; ! 600: ! 601: /* driver private */ ! 602: ! 603: tbd_t _tbds[TBDS_PER_TCB]; ! 604: struct tcb * _next; ! 605: IOPhysicalAddress _paddr; ! 606: struct mbuf * _mbuf; ! 607: unsigned _pad; ! 608: } tcb_t; ! 609: ! 610: #endif /* !_I82557HW_H */ ! 611:
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