![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to i82557eeprom.h CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Apple XNU] / XNU / iokit / Drivers / network / drvIntel82557|
Return to i82557eeprom.h CVS log | Up to [Apple XNU] / XNU / iokit / Drivers / network / drvIntel82557 |
1.1 root 1: /*
2: * Copyright (c) 1998-2000 Apple Computer, Inc. All rights reserved.
3: *
4: * @APPLE_LICENSE_HEADER_START@
5: *
6: * The contents of this file constitute Original Code as defined in and
7: * are subject to the Apple Public Source License Version 1.1 (the
8: * "License"). You may not use this file except in compliance with the
9: * License. Please obtain a copy of the License at
10: * http://www.apple.com/publicsource and read it before using this file.
11: *
12: * This Original Code and all software distributed under the License are
13: * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14: * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15: * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16: * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17: * License for the specific language governing rights and limitations
18: * under the License.
19: *
20: * @APPLE_LICENSE_HEADER_END@
21: */
22: /*
23: * Copyright (c) 1996 NeXT Software, Inc.
24: *
25: * i82557eeprom.h
26: * - Intel 82557 eeprom access object
27: *
28: * HISTORY
29: *
30: * 6-Mar-96 Dieter Siegmund (dieter) at NeXT
31: * Created.
32: */
33:
34: #ifndef _I82557EEPROM_H
35: #define _I82557EEPROM_H
36:
37: #include "i82557Inline.h"
38: #include "i82557HW.h"
39:
40: #define BITS_IN_SHORT 16
41: #define MIN_SK_HIGH 20
42: #define MIN_SK_LOW 20
43: #define NUM_EEPROM_WORDS 0x40
44: #define EEPROM_CHECKSUM_VALUE 0xbaba
45:
46: //-------------------------------------------------------------------------
47: // Compatibility Byte 0
48: // 8-bit, word 0x3, low byte
49: //-------------------------------------------------------------------------
50: #define EEPROM_C0_MC_100 BIT(1)
51: #define EEPROM_C0_MC_10 BIT(0)
52:
53: //-------------------------------------------------------------------------
54: // Compatibility Byte 1
55: // 8-bit, word 0x3, high byte
56: //-------------------------------------------------------------------------
57: #define EEPROM_C1_OEM BIT(0)
58:
59: //-------------------------------------------------------------------------
60: // Controller Type
61: // 8-bit, word 0x5, high byte
62: //-------------------------------------------------------------------------
63: #define EEPROM_TYPE_82558 2
64: #define EEPROM_TYPE_82557 1
65:
66: //-------------------------------------------------------------------------
67: // Connectors
68: // 8-bit, word 0x5, low byte
69: //-------------------------------------------------------------------------
70: #define EEPROM_CON_MII BIT(3)
71: #define EEPROM_CON_AUI BIT(2)
72: #define EEPROM_CON_BNC BIT(1)
73: #define EEPROM_CON_RJ45 BIT(0)
74:
75: //-------------------------------------------------------------------------
76: // PHY Device Record.
77: // 16-bit, Primary word 0x6, Secondary word 0x7.
78: //-------------------------------------------------------------------------
79: #define EEPROM_PHY_10 BIT(15)
80: #define EEPROM_PHY_VSCR BIT(14)
81: #define EEPROM_PHY_DEVICE_SHIFT 8
82: #define EEPROM_PHY_DEVICE_MASK CSR_MASK(EEPROM_PHY_DEVICE, 0x3f)
83: #define EEPROM_PHY_ADDRESS_SHIFT 0
84: #define EEPROM_PHY_ADDRESS_MASK CSR_MASK(EEPROM_PHY_ADDRESS, 0xff)
85:
86: typedef enum {
87: PHYDevice_None_e = 0,
88: PHYDevice_Intel82553_A_B_step_e,
89: PHYDevice_Intel82553_C_step_e,
90: PHYDevice_Intel82503_e,
91: PHYDevice_NationalDP83840_TX_C_step_e,
92: PHYDevice_Seeq80C240_T4_e,
93: PHYDevice_Seeq80C24_e,
94: PHYDevice_Intel82555_e,
95: PHYDevice_MicroLinear_e,
96: PHYDevice_Level_One_e,
97: PHYDevice_NationalDP82840A_e,
98: PHYDevice_ICS1890_e,
99: PHYDevice_Last_e
100: } PHYDevice_t;
101:
102: static inline char *
103: PHYDeviceNames(unsigned int i)
104: {
105: char * devices[] = {
106: "No PHY device installed",
107: "Intel 82553 (PHY 100) A or B step",
108: "Intel 82553 (PHY 100) C step",
109: "Intel 82503 10Mps",
110: "National DP83840 C step 100Base-TX",
111: "Seeq 80C240 100Base-T4",
112: "Seeq 80C24 10 Mps",
113: "Intel 82555 10/100Base-TX PHY",
114: "MicroLinear 10Mbps",
115: "Level One 10Mbps",
116: "National DP83840A",
117: "ICS 1890",
118: "PHY device unknown"
119: };
120: if (i > PHYDevice_Last_e)
121: i = PHYDevice_Last_e;
122: return (devices[i]);
123: };
124:
125: #define NUM_PHYS 2
126: #define PRIMARY_PHY 0
127: #define SECONDARY_PHY 1
128: #define NPWA_BYTES 4
129:
130: typedef struct {
131: enet_addr_t addr;
132: UInt8 compatibility_0;
133: UInt8 compatibility_1;
134: UInt16 zero0;
135: UInt8 connectors;
136: UInt8 controllerType;
137: #define I82557_CONTROLLER_TYPE 1
138: #define I82558_CONTROLLER_TYPE 2
139: UInt16 phys[NUM_PHYS];
140: UInt8 PWANumber[NPWA_BYTES];
141: UInt16 zero1[38];
142: UInt16 rplConfig[2];
143: UInt16 zero5[13];
144: UInt16 checkSum;
145: } EEPROM_t;
146:
147: static inline
148: void EEPROMWriteBit(volatile eeprom_control_t * ee_p, bool bit)
149: {
150: if (bit)
151: OSSetLE16(ee_p, EEPROM_CONTROL_EEDI);
152: else
153: OSClearLE16(ee_p, EEPROM_CONTROL_EEDI);
154:
155: OSSetLE16(ee_p, EEPROM_CONTROL_EESK);
156: IODelay(MIN_SK_HIGH);
157: OSClearLE16(ee_p, EEPROM_CONTROL_EESK);
158: IODelay(MIN_SK_LOW);
159: }
160:
161: static inline
162: bool EEPROMReadBit(volatile eeprom_control_t * ee_p)
163: {
164: bool bit;
165:
166: OSSetLE16(ee_p, EEPROM_CONTROL_EESK);
167: IODelay(MIN_SK_HIGH);
168: bit = (OSReadLE16(ee_p) & EEPROM_CONTROL_EEDO) ? 1 : 0;
169: OSClearLE16(ee_p, EEPROM_CONTROL_EESK);
170: IODelay(MIN_SK_LOW);
171: return (bit);
172: }
173:
174: static inline
175: void EEPROMEnable(volatile eeprom_control_t * ee_p)
176: {
177: OSSetLE16(ee_p, EEPROM_CONTROL_EECS);
178: return;
179: }
180:
181: static inline
182: void EEPROMDisable(volatile eeprom_control_t * ee_p)
183: {
184: OSClearLE16(ee_p, EEPROM_CONTROL_EECS);
185: return;
186: }
187:
188: class i82557eeprom : public OSObject
189: {
190: OSDeclareDefaultStructors(i82557eeprom)
191:
192: public:
193: volatile eeprom_control_t * ee_p;
194: int nbits;
195: union {
196: UInt16 words[NUM_EEPROM_WORDS];
197: EEPROM_t fields;
198: } image;
199:
200: static i82557eeprom * withAddress(volatile eeprom_control_t * p);
201:
202: bool initWithAddress(volatile eeprom_control_t * p);
203:
204: UInt16 readWord(int offset);
205:
206: EEPROM_t * getContents();
207:
208: void dumpContents();
209: };
210:
211: #endif /* !_I82557EEPROM_H */
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.