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1.1 root 1: /*
2: * Copyright (c) 1998-2000 Apple Computer, Inc. All rights reserved.
3: *
4: * @APPLE_LICENSE_HEADER_START@
5: *
6: * The contents of this file constitute Original Code as defined in and
7: * are subject to the Apple Public Source License Version 1.1 (the
8: * "License"). You may not use this file except in compliance with the
9: * License. Please obtain a copy of the License at
10: * http://www.apple.com/publicsource and read it before using this file.
11: *
12: * This Original Code and all software distributed under the License are
13: * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14: * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15: * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16: * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17: * License for the specific language governing rights and limitations
18: * under the License.
19: *
20: * @APPLE_LICENSE_HEADER_END@
21: */
22: /*
23: * Copyright (c) 1998-1999 by Apple Computer, Inc., All rights reserved.
24: *
25: * MII protocol and PHY register definitions.
26: *
27: * HISTORY
28: *
29: */
30:
31: #ifndef _BMACENETMII_H
32: #define _BMACENETMII_H
33:
34: /*
35: * MII command frame (32-bits) as documented in IEEE 802.3u
36: */
37:
38: // _BIG_ENDIAN is already defined for PPC
39: //
40: #if 0
41: #ifdef __PPC__
42: #define _BIG_ENDIAN
43: #endif
44: #endif /* 0 */
45:
46: typedef union {
47: unsigned int data;
48: #ifdef _BIG_ENDIAN
49: struct {
50: unsigned int
51: st:2, // start of frame
52: #define MII_ST 0x01
53: op:2, // operation code
54: #define MII_OP_READ 0x02
55: #define MII_OP_WRITE 0x01
56: phyad:5, // PHY address
57: regad:5, // register address
58: ta:2, // turnaround
59: data:16; // 16-bit data field
60: } bit;
61: #else _BIG_ENDIAN
62: struct {
63: unsigned int
64: data:16, // 16-bit data field
65: ta:2, // turnaround
66: regad:5, // register address
67: phyad:5, // PHY address
68: op:2, // operation code
69: st:2; // start of frame
70: } bit;
71: #endif _BIG_ENDIAN
72: } miiFrameUnion;
73:
74: #define MII_FRAME_PREAMBLE 0xFFFFFFFF
75: #define MII_FRAME_SIZE 32
76: #define MII_FRAME_READ 0x60000000
77: #define MII_FRAME_WRITE 0x50020000
78:
79: #define MII_MAX_PHY 32
80:
81: /* MII Registers */
82: #define MII_CONTROL 0
83: #define MII_STATUS 1
84: #define MII_ID0 2
85: #define MII_ID1 3
86: #define MII_ADVERTISEMENT 4
87: #define MII_LINKPARTNER 5
88: #define MII_EXPANSION 6
89: #define MII_NEXTPAGE 7
90:
91: /* MII Control register bits */
92: #define MII_CONTROL_RESET 0x8000
93: #define MII_CONTROL_LOOPBACK 0x4000
94: #define MII_CONTROL_SPEED_SELECTION 0x2000
95: #define MII_CONTROL_AUTONEGOTIATION 0x1000
96: #define MII_CONTROL_POWERDOWN 0x800
97: #define MII_CONTROL_ISOLATE 0x400
98: #define MII_CONTROL_RESTART_NEGOTIATION 0x200
99: #define MII_CONTROL_FULLDUPLEX 0x100
100: #define MII_CONTROL_COLLISION_TEST 0x80
101:
102: /* MII Status register bits */
103: #define MII_STATUS_100BASET4 0x8000
104: #define MII_STATUS_100BASETX_FD 0x4000
105: #define MII_STATUS_100BASETX 0x2000
106: #define MII_STATUS_10BASET_FD 0x1000
107: #define MII_STATUS_10BASET 0x800
108: #define MII_STATUS_NEGOTIATION_COMPLETE 0x20
109: #define MII_STATUS_REMOTE_FAULT 0x10
110: #define MII_STATUS_NEGOTIATION_ABILITY 0x8
111: #define MII_STATUS_LINK_STATUS 0x4
112: #define MII_STATUS_JABBER_DETECT 0x2
113: #define MII_STATUS_EXTENDED_CAPABILITY 0x1
114:
115: /* MII ANAR register bits */
116: #define MII_ANAR_100BASET4 0x200
117: #define MII_ANAR_100BASETX_FD 0x100
118: #define MII_ANAR_100BASETX 0x80
119: #define MII_ANAR_10BASET_FD 0x40
120: #define MII_ANAR_10BASET 0x20
121:
122: /* MII ST10040 Specific */
123:
124: /* MII ST10040 ID */
125: #define MII_ST10040_OUI 0x1e0400
126: #define MII_ST10040_MODEL 0x00
127: #define MII_ST10040_REV 0x01
128: #define MII_ST10040_ID ((MII_ST10040_OUI << 10) | \
129: (MII_ST10040_MODEL << 4))
130: #define MII_ST10040_MASK 0xfffffff0
131:
132: #define MII_ST10040_DELAY 1
133:
134: /* MII ST10040 Regs */
135: #define MII_ST10040_CHIPST 0x14
136:
137: /* MII ST10040 CHIPST register bits */
138: #define MII_ST10040_CHIPST_LINK 0x2000
139: #define MII_ST10040_CHIPST_DUPLEX 0x1000
140: #define MII_ST10040_CHIPST_SPEED 0x0800
141: #define MII_ST10040_CHIPST_NEGOTIATION 0x0020
142:
143: /* MII DP83843 Specific */
144:
145: /* MII DP83843 ID */
146: #define MII_DP83843_OUI 0x080017
147: #define MII_DP83843_MODEL 0x01
148: #define MII_DP83843_REV 0x00
149: #define MII_DP83843_ID ((MII_DP83843_OUI << 10) | \
150: (MII_DP83843_MODEL << 4))
151: #define MII_DP83843_MASK 0xfffffff0
152:
153: #define MII_DP83843_DELAY 20
154:
155: /* MII DP83843 PHYSTS register bits */
156: #define MII_DP83843_PHYSTS 0x10
157: #define MII_DP83843_PHYSTS_LINK 0x0001
158: #define MII_DP83843_PHYSTS_SPEED10 0x0002
159: #define MII_DP83843_PHYSTS_DUPLEX 0x0004
160: #define MII_DP83843_PHYSTS_NEGOTIATION 0x0020
161:
162:
163: /* MII timeout */
164: #define MII_DEFAULT_DELAY 20
165: #define MII_RESET_TIMEOUT 100
166: #define MII_RESET_DELAY 10
167:
168: #define MII_LINK_TIMEOUT 5000
169: #define MII_LINK_DELAY 20
170:
171: #endif /* _BMACENETMII_H */
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