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1.1 root 1: /*
2: * Copyright (c) 1999 Apple Computer, Inc. All rights reserved.
3: *
4: * @APPLE_LICENSE_HEADER_START@
5: *
6: * The contents of this file constitute Original Code as defined in and
7: * are subject to the Apple Public Source License Version 1.1 (the
8: * "License"). You may not use this file except in compliance with the
9: * License. Please obtain a copy of the License at
10: * http://www.apple.com/publicsource and read it before using this file.
11: *
12: * This Original Code and all software distributed under the License are
13: * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14: * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15: * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16: * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17: * License for the specific language governing rights and limitations
18: * under the License.
19: *
20: * @APPLE_LICENSE_HEADER_END@
21: */
22:
23: /*
24: * Copyright (c) 1998-1999 by Apple Computer, Inc., All rights reserved.
25: *
26: * MII protocol and PHY register definitions.
27: *
28: * HISTORY
29: *
30: */
31:
32: /*
33: * MII command frame (32-bits) as documented in IEEE 802.3u
34: */
35: #define MII_OP_READ 0x02
36: #define MII_OP_WRITE 0x01
37:
38: #define MII_MAX_PHY 32
39:
40: /* MII Registers */
41: #define MII_CONTROL 0
42: #define MII_STATUS 1
43: #define MII_ID0 2
44: #define MII_ID1 3
45: #define MII_ADVERTISEMENT 4
46: #define MII_LINKPARTNER 5
47: #define MII_EXPANSION 6
48: #define MII_NEXTPAGE 7
49:
50: /* MII Control register bits */
51: #define MII_CONTROL_RESET 0x8000
52: #define MII_CONTROL_LOOPBACK 0x4000
53: #define MII_CONTROL_SPEED_SELECTION 0x2000
54: #define MII_CONTROL_AUTONEGOTIATION 0x1000
55: #define MII_CONTROL_POWERDOWN 0x800
56: #define MII_CONTROL_ISOLATE 0x400
57: #define MII_CONTROL_RESTART_NEGOTIATION 0x200
58: #define MII_CONTROL_FULLDUPLEX 0x100
59: #define MII_CONTROL_COLLISION_TEST 0x80
60:
61: /* MII Status register bits */
62: #define MII_STATUS_100BASET4 0x8000
63: #define MII_STATUS_100BASETX_FD 0x4000
64: #define MII_STATUS_100BASETX 0x2000
65: #define MII_STATUS_10BASET_FD 0x1000
66: #define MII_STATUS_10BASET 0x800
67: #define MII_STATUS_NEGOTIATION_COMPLETE 0x20
68: #define MII_STATUS_REMOTE_FAULT 0x10
69: #define MII_STATUS_NEGOTIATION_ABILITY 0x8
70: #define MII_STATUS_LINK_STATUS 0x4
71: #define MII_STATUS_JABBER_DETECT 0x2
72: #define MII_STATUS_EXTENDED_CAPABILITY 0x1
73:
74: /* MII ANAR register bits */
75: #define MII_ANAR_ASYM_PAUSE 0x800
76: #define MII_ANAR_PAUSE 0x400
77: #define MII_ANAR_100BASET4 0x200
78: #define MII_ANAR_100BASETX_FD 0x100
79: #define MII_ANAR_100BASETX 0x80
80: #define MII_ANAR_10BASET_FD 0x40
81: #define MII_ANAR_10BASET 0x20
82:
83: /* MII ANLPAR register bits */
84: #define MII_LPAR_NEXT_PAGE 0x8000
85: #define MII_LPAR_ACKNOWLEDGE 0x4000
86: #define MII_LPAR_REMOTE_FAULT 0x2000
87: #define MII_LPAR_ASYM_PAUSE 0x0800
88: #define MII_LPAR_PAUSE 0x0400
89: #define MII_LPAR_100BASET4 0x200
90: #define MII_LPAR_100BASETX_FD 0x100
91: #define MII_LPAR_100BASETX 0x80
92: #define MII_LPAR_10BASET_FD 0x40
93: #define MII_LPAR_10BASET 0x20
94:
95:
96: /* MII BCM5201 Specific */
97:
98: /* MII BCM5201 ID */
99: #define MII_BCM5201_OUI 0x001018
100: #define MII_BCM5201_MODEL 0x21
101: #define MII_BCM5201_REV 0x01
102: #define MII_BCM5201_ID ((MII_BCM5201_OUI << 10) | (MII_BCM5201_MODEL << 4))
103: #define MII_BCM5201_MASK 0xfffffff0
104:
105: #define MII_BCM5201_DELAY 1
106:
107: /* MII BCM5201 Regs */
108: #define MII_BCM5201_AUXSTATUS 0x18
109:
110: /* MII BCM5201 AUXSTATUS register bits */
111: #define MII_BCM5201_AUXSTATUS_DUPLEX 0x0001
112: #define MII_BCM5201_AUXSTATUS_SPEED 0x0002
113:
114: #define MII_BCM5201_MULTIPHY 0x1E
115:
116: /* MII BCM5201 MULTIPHY register bits */
117: #define MII_BCM5201_MULTIPHY_SERIALMODE 0x0002
118: #define MII_BCM5201_MULTIPHY_SUPERISOLATE 0x0008
119:
120: /* MII BCM5400 Specific */
121:
122: /* MII BCM5400 ID */
123: #define MII_BCM5400_OUI 0x000818
124: #define MII_BCM5400_MODEL 0x04
125: #define MII_BCM5400_REV 0x01
126: #define MII_BCM5400_ID ((MII_BCM5400_OUI << 10) | (MII_BCM5400_MODEL << 4))
127: #define MII_BCM5400_MASK 0xfffffff0
128:
129: #define MII_BCM5400_DELAY 1
130:
131: /* MII BCM5400 Regs */
132:
133: #define MII_BCM5400_1000BASETCONTROL 0x09
134: /* MII BCM5400 1000-BASET Control register bits */
135:
136: #define MII_BCM5400_1000BASETCONTROL_FULLDUPLEXCAP 0x0200
137:
138: #define MII_BCM5400_AUXCONTROL 0x18
139:
140: /* MII BCM5400 AUXCONTROL register bits */
141: #define MII_BCM5400_AUXCONTROL_PWR10BASET 0x0004
142:
143: #define MII_BCM5400_AUXSTATUS 0x19
144:
145: /* MII BCM5400 AUXSTATUS register bits */
146: #define MII_BCM5400_AUXSTATUS_LINKMODE_MASK 0x0700
147: #define MII_BCM5400_AUXSTATUS_LINKMODE_BIT 0x0100
148:
149: /* MII ST10040 Specific */
150:
151: /* MII ST10040 ID */
152: #define MII_ST10040_OUI 0x1e0400
153: #define MII_ST10040_MODEL 0x00
154: #define MII_ST10040_REV 0x01
155: #define MII_ST10040_ID ((MII_ST10040_OUI << 10) | (MII_ST10040_MODEL << 4))
156: #define MII_ST10040_MASK 0xfffffff0
157:
158: #define MII_ST10040_DELAY 1
159:
160: /* MII ST10040 Regs */
161: #define MII_ST10040_CHIPST 0x14
162:
163: /* MII ST10040 CHIPST register bits */
164: #define MII_ST10040_CHIPST_LINK 0x2000
165: #define MII_ST10040_CHIPST_DUPLEX 0x1000
166: #define MII_ST10040_CHIPST_SPEED 0x0800
167: #define MII_ST10040_CHIPST_NEGOTIATION 0x0020
168:
169:
170: /* MII DP83843 Specific */
171:
172: /* MII DP83843 ID */
173: #define MII_DP83843_OUI 0x080017
174: #define MII_DP83843_MODEL 0x01
175: #define MII_DP83843_REV 0x00
176: #define MII_DP83843_ID ((MII_DP83843_OUI << 10) | (MII_DP83843_MODEL << 4))
177: #define MII_DP83843_MASK 0xfffffff0
178:
179: #define MII_DP83843_DELAY 20
180:
181: /* MII DP83843 PHYSTS register bits */
182: #define MII_DP83843_PHYSTS 0x10
183: #define MII_DP83843_PHYSTS_LINK 0x0001
184: #define MII_DP83843_PHYSTS_SPEED10 0x0002
185: #define MII_DP83843_PHYSTS_DUPLEX 0x0004
186: #define MII_DP83843_PHYSTS_NEGOTIATION 0x0020
187:
188:
189: /* MII timeout */
190: #define MII_DEFAULT_DELAY 20
191: #define MII_RESET_TIMEOUT 100
192: #define MII_RESET_DELAY 10
193:
194: #define MII_LINK_TIMEOUT 5000
195: #define MII_LINK_DELAY 20
196:
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