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1.1 root 1: /*
2: * Copyright (c) 1998-2000 Apple Computer, Inc. All rights reserved.
3: *
4: * @APPLE_LICENSE_HEADER_START@
5: *
6: * The contents of this file constitute Original Code as defined in and
7: * are subject to the Apple Public Source License Version 1.1 (the
8: * "License"). You may not use this file except in compliance with the
9: * License. Please obtain a copy of the License at
10: * http://www.apple.com/publicsource and read it before using this file.
11: *
12: * This Original Code and all software distributed under the License are
13: * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14: * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15: * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16: * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17: * License for the specific language governing rights and limitations
18: * under the License.
19: *
20: * @APPLE_LICENSE_HEADER_END@
21: */
22: #include <IOKit/IOTypes.h>
23:
24: typedef char *Ptr;
25:
26: #define bit0 0x00000001
27: #define bit1 0x00000002
28: #define bit2 0x00000004
29: #define bit3 0x00000008
30: #define bit4 0x00000010
31: #define bit5 0x00000020
32: #define bit6 0x00000040
33: #define bit7 0x00000080
34: #define bit8 0x00000100
35: #define bit9 0x00000200
36: #define bit10 0x00000400
37: #define bit11 0x00000800
38: #define bit12 0x00001000
39: #define bit13 0x00002000
40: #define bit14 0x00004000
41: #define bit15 0x00008000
42: #define bit16 0x00010000
43: #define bit17 0x00020000
44: #define bit18 0x00040000
45: #define bit19 0x00080000
46: #define bit20 0x00100000
47: #define bit21 0x00200000
48: #define bit22 0x00400000
49: #define bit23 0x00800000
50: #define bit24 0x01000000
51: #define bit25 0x02000000
52: #define bit26 0x04000000
53: #define bit27 0x08000000
54: #define bit28 0x10000000
55: #define bit29 0x20000000
56: #define bit30 0x40000000
57: #define bit31 0x80000000
58:
59:
60: /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
61: * Configuration Registers
62: *
63: */
64: enum {
65: kConfigStart = 0x00,
66: cwVendorID = 0x00, /* 0x1000 */
67: cwDeviceID = 0x02, /* 0x0003 */
68: cwCommand = 0x04,
69: cwStatus = 0x06,
70: clClassCodeAndRevID = 0x08,
71: clHeaderAndLatency = 0x0C,
72: clBaseAddressZero = 0x10, /* I/O Base address */
73: clBaseAddressOne = 0x14, /* Memory Base address */
74: clExpansionRomAddr = 0x30,
75: clLatGntIntPinLine = 0x3C, /* Max_Lat, Max_Gnt, Int. Pin, Int. Line */
76: kConfigEnd = 0x40
77: };
78:
79: /*
80: * 0x04 cwCommand Command Register (read/write)
81: */
82: enum {
83: cwCommandSERREnable = bit8,
84: cwCommandEnableParityError = bit6,
85: cwCommandEnableBusMaster = bit2, /* Set this on initialization */
86: cwCommandEnableMemorySpace = bit1, /* Respond at Base Address One if set */
87: cwCommandEnableIOSpace = bit0 /* Respond at Base Address Zero if set */
88: };
89: /*
90: * 0x06 cwStatus Status Register (read/write)
91: */
92: enum {
93: cwStatusDetectedParityError = bit15, /* Detected from slave */
94: cwStatusSignaledSystemError = bit14, /* Device asserts SERR/ signal */
95: cwStatusMasterAbort = bit13, /* Master sets when transaction aborts */
96: cwStatusReceivedTargetAbort = bit12, /* Master sets when target-abort */
97: cwStatusDEVSELTimingMask = (bit10 | bit9), /* DEVSEL timing encoding R/O */
98: cwStatusDEVSELFastTiming = 0,
99: cwStatusDEVSELMediumTiming = bit9,
100: cwStatusDEVSELSlowTiming = bit10,
101: cwStatusDataParityReported = bit8
102: };
103:
104:
105: ////////////////////////////////////////////////////////////////////////////////
106: //
107: // OHCI type defs.
108: //
109: typedef UInt32 PhysicalPtr;
110:
111: typedef struct OHCIRegistersStruct
112: OHCIRegisters,
113: *OHCIRegistersPtr;
114:
115: typedef struct OHCIIntHeadStruct
116: OHCIIntHead,
117: *OHCIIntHeadPtr;
118:
119: typedef struct OHCIEndpointDescriptorStruct
120: OHCIEndpointDescriptor,
121: *OHCIEndpointDescriptorPtr;
122:
123: typedef struct OHCIGeneralTransferDescriptorStruct
124: OHCIGeneralTransferDescriptor,
125: *OHCIGeneralTransferDescriptorPtr;
126:
127: typedef struct OHCIIsochTransferDescriptorStruct
128: OHCIIsochTransferDescriptor,
129: *OHCIIsochTransferDescriptorPtr;
130:
131: typedef struct OHCIUIMDataStruct
132: OHCIUIMData,
133: *OHCIUIMDataPtr;
134:
135: typedef struct OHCIPhysicalLogicalStruct
136: OHCIPhysicalLogical,
137: *OHCIPhysicalLogicalPtr;
138:
139:
140: ////////////////////////////////////////////////////////////////////////////////
141: //
142: // OHCI register file.
143: //
144:
145: enum
146: {
147: kOHCIBit0 = (1 << 0),
148: kOHCIBit1 = (1 << 1),
149: kOHCIBit2 = (1 << 2),
150: kOHCIBit3 = (1 << 3),
151: kOHCIBit4 = (1 << 4),
152: kOHCIBit5 = (1 << 5),
153: kOHCIBit6 = (1 << 6),
154: kOHCIBit7 = (1 << 7),
155: kOHCIBit8 = (1 << 8),
156: kOHCIBit9 = (1 << 9),
157: kOHCIBit10 = (1 << 10),
158: kOHCIBit11 = (1 << 11),
159: kOHCIBit12 = (1 << 12),
160: kOHCIBit13 = (1 << 13),
161: kOHCIBit14 = (1 << 14),
162: kOHCIBit15 = (1 << 15),
163: kOHCIBit16 = (1 << 16),
164: kOHCIBit17 = (1 << 17),
165: kOHCIBit18 = (1 << 18),
166: kOHCIBit19 = (1 << 19),
167: kOHCIBit20 = (1 << 20),
168: kOHCIBit21 = (1 << 21),
169: kOHCIBit22 = (1 << 22),
170: kOHCIBit23 = (1 << 23),
171: kOHCIBit24 = (1 << 24),
172: kOHCIBit25 = (1 << 25),
173: kOHCIBit26 = (1 << 26),
174: kOHCIBit27 = (1 << 27),
175: kOHCIBit28 = (1 << 28),
176: kOHCIBit29 = (1 << 29),
177: kOHCIBit30 = (1 << 30),
178: kOHCIBit31 = (1 << 31)
179: };
180:
181: #define OHCIBitRange(start, end) \
182: ( \
183: ((((UInt32) 0xFFFFFFFF) << (31 - (end))) >> \
184: ((31 - (end)) + (start))) << \
185: (start) \
186: )
187:
188: #define OHCIBitRangePhase(start, end) \
189: (start)
190:
191:
192: // OHCI register file.
193:
194: struct OHCIRegistersStruct
195: {
196: // Control and status group.
197: volatile UInt32 hcRevision;
198: volatile UInt32 hcControl;
199: volatile UInt32 hcCommandStatus;
200: volatile UInt32 hcInterruptStatus;
201: volatile UInt32 hcInterruptEnable;
202: volatile UInt32 hcInterruptDisable;
203:
204: // Memory pointer group.
205: volatile UInt32 hcHCCA;
206: volatile UInt32 hcPeriodCurrentED;
207: volatile UInt32 hcControlHeadED;
208: volatile UInt32 hcControlCurrentED;
209: volatile UInt32 hcBulkHeadED;
210: volatile UInt32 hcBulkCurrentED;
211: volatile UInt32 hcDoneHead;
212:
213: // Frame counter group.
214: volatile UInt32 hcFmInterval;
215: volatile UInt32 hcFmRemaining;
216: volatile UInt32 hcFmNumber;
217: volatile UInt32 hcPeriodicStart;
218: volatile UInt32 hcLSThreshold;
219:
220: // Root hub group.
221: volatile UInt32 hcRhDescriptorA;
222: volatile UInt32 hcRhDescriptorB;
223: volatile UInt32 hcRhStatus;
224: volatile UInt32 hcRhPortStatus[1];
225: };
226:
227: typedef struct OHCIRegistersStruct *OHCIRegistersPtr;
228:
229: // hcControl register defs.
230: enum
231: {
232: kOHCIHcControl_CBSR = OHCIBitRange (0, 1),
233: kOHCIHcControl_CBSRPhase = OHCIBitRangePhase (0, 1),
234: kOHCIHcControl_PLE = kOHCIBit2,
235: kOHCIHcControl_IE = kOHCIBit3,
236: kOHCIHcControl_CLE = kOHCIBit4,
237: kOHCIHcControl_BLE = kOHCIBit5,
238: kOHCIHcControl_HCFS = OHCIBitRange (6, 7),
239: kOHCIHcControl_HCFSPhase = OHCIBitRangePhase (6, 7),
240: kOHCIHcControl_IR = kOHCIBit8,
241: kOHCIHcControl_RWC = kOHCIBit9,
242: kOHCIHcControl_RWE = kOHCIBit10,
243:
244: kOHCIHcControl_Reserved = OHCIBitRange (11, 31),
245:
246: kOHCIFunctionalState_Reset = 0,
247: kOHCIFunctionalState_Resume = 1,
248: kOHCIFunctionalState_Operational = 2,
249: kOHCIFunctionalState_Suspend = 3
250: };
251:
252: // hcCommandStatus register defs.
253: enum
254: {
255: kOHCIHcCommandStatus_HCR = kOHCIBit0,
256: kOHCIHcCommandStatus_CLF = kOHCIBit1,
257: kOHCIHcCommandStatus_BLF = kOHCIBit2,
258: kOHCIHcCommandStatus_OCR = kOHCIBit3,
259: kOHCIHcCommandStatus_SOC = OHCIBitRange (16, 17),
260: kOHCIHcCommandStatus_SOCPhase = OHCIBitRangePhase (16, 17),
261:
262: kOHCIHcCommandStatus_Reserved = OHCIBitRange (4, 15) | OHCIBitRange (18, 31)
263: };
264:
265: // hcInterrupt register defs.
266: enum
267: {
268: kOHCIHcInterrupt_SO = kOHCIBit0,
269: kOHCIHcInterrupt_WDH = kOHCIBit1,
270: kOHCIHcInterrupt_SF = kOHCIBit2,
271: kOHCIHcInterrupt_RD = kOHCIBit3,
272: kOHCIHcInterrupt_UE = kOHCIBit4,
273: kOHCIHcInterrupt_FNO = kOHCIBit5,
274: kOHCIHcInterrupt_RHSC = kOHCIBit6,
275: kOHCIHcInterrupt_OC = kOHCIBit30,
276: kOHCIHcInterrupt_MIE = kOHCIBit31
277: };
278:
279: // this is what I would like it to be
280: //#define kOHCIDefaultInterrupts (kOHCIHcInterrupt_SO | kOHCIHcInterrupt_WDH | kOHCIHcInterrupt_UE | kOHCIHcInterrupt_FNO | kOHCIHcInterrupt_RHSC)
281: #define kOHCIDefaultInterrupts (kOHCIHcInterrupt_WDH | kOHCIHcInterrupt_UE | kOHCIHcInterrupt_FNO)
282:
283:
284: // hcFmInterval register defs.
285: enum
286: {
287: kOHCIHcFmInterval_FI = OHCIBitRange (0, 13),
288: kOHCIHcFmInterval_FIPhase = OHCIBitRangePhase (0, 13),
289: kOHCIHcFmInterval_FSMPS = OHCIBitRange (16, 30),
290: kOHCIHcFmInterval_FSMPSPhase = OHCIBitRangePhase (16, 30),
291: kOHCIHcFmInterval_FIT = kOHCIBit31,
292:
293: kOHCIHcFmInterval_Reserved = OHCIBitRange (14, 15)
294: };
295:
296: enum
297: {
298: kOHCIMax_OverHead = 210 // maximum bit time overhead for a xaction
299: };
300:
301:
302: // hcRhDescriptorA register defs.
303: enum
304: {
305: kOHCIHcRhDescriptorA_NDP = OHCIBitRange (0, 7),
306: kOHCIHcRhDescriptorA_NDPPhase = OHCIBitRangePhase (0, 7),
307: kOHCIHcRhDescriptorA_PSM = kOHCIBit8,
308: kOHCIHcRhDescriptorA_NPS = kOHCIBit9,
309: kOHCIHcRhDescriptorA_DT = kOHCIBit10,
310: kOHCIHcRhDescriptorA_OCPM = kOHCIBit11,
311: kOHCIHcRhDescriptorA_NOCP = kOHCIBit12,
312: kOHCIHcRhDescriptorA_POTPGT = OHCIBitRange (24, 31),
313: kOHCIHcRhDescriptorA_POTPGTPhase = OHCIBitRangePhase (24, 31),
314:
315: kOHCIHcRhDescriptorA_Reserved = OHCIBitRange (13,23)
316: };
317:
318:
319: // hcRhDescriptorB register defs.
320: enum
321: {
322: kOHCIHcRhDescriptorB_DR = OHCIBitRange (0, 15),
323: kOHCIHcRhDescriptorB_DRPhase = OHCIBitRangePhase (0, 15),
324: kOHCIHcRhDescriptorB_PPCM = OHCIBitRange (16, 31),
325: kOHCIHcRhDescriptorB_PPCMPhase = OHCIBitRangePhase (16, 31)
326: };
327:
328:
329: // Config space defs.
330: enum
331: {
332: kOHCIConfigRegBaseAddressRegisterNumber = 0x10
333: };
334:
335:
336: enum
337: {
338: kOHCIEDControl_FA = OHCIBitRange (0, 6),
339: kOHCIEDControl_FAPhase = OHCIBitRangePhase (0, 6),
340: kOHCIEDControl_EN = OHCIBitRange (7, 10),
341: kOHCIEDControl_ENPhase = OHCIBitRangePhase (7, 10),
342: kOHCIEDControl_D = OHCIBitRange (11, 12),
343: kOHCIEDControl_DPhase = OHCIBitRangePhase (11, 12),
344: kOHCIEDControl_S = OHCIBitRange (13, 13),
345: kOHCIEDControl_SPhase = OHCIBitRangePhase (13, 13),
346: kOHCIEDControl_K = kOHCIBit14,
347: kOHCIEDControl_F = OHCIBitRange (15, 15),
348: kOHCIEDControl_FPhase = OHCIBitRangePhase (15, 15),
349: kOHCIEDControl_MPS = OHCIBitRange (16, 26),
350: kOHCIEDControl_MPSPhase = OHCIBitRangePhase (16, 26),
351:
352: kOHCITailPointer_tailP = OHCIBitRange (4, 31),
353: kOHCITailPointer_tailPPhase = OHCIBitRangePhase (4, 31),
354:
355: kOHCIHeadPointer_H = kOHCIBit0,
356: kOHCIHeadPointer_C = kOHCIBit1,
357: kOHCIHeadPointer_headP = OHCIBitRange (4, 31),
358: kOHCIHeadPointer_headPPhase = OHCIBitRangePhase (4, 31),
359:
360: kOHCINextEndpointDescriptor_nextED = OHCIBitRange (4, 31),
361: kOHCINextEndpointDescriptor_nextEDPhase = OHCIBitRangePhase (4, 31),
362:
363: kOHCIEDDirectionTD = 0,
364: kOHCIEDDirectionOut = 1,
365: kOHCIEDDirectionIn = 2,
366:
367: kOHCIEDSpeedFull = 0,
368: kOHCIEDSpeedLow = 1,
369:
370: kOHCIEDFormatGeneralTD = 0,
371: kOHCIEDFormatIsochronousTD = 1
372: };
373:
374: typedef UInt8 OHCIEDFormat; // really only need 1 bit
375:
376: // General Transfer Descriptor
377: enum
378: {
379: kOHCIGTDControl_R = kOHCIBit18,
380: kOHCIGTDControl_DP = OHCIBitRange (19, 20),
381: kOHCIGTDControl_DPPhase = OHCIBitRangePhase (19, 20),
382: kOHCIGTDControl_DI = OHCIBitRange (21, 23),
383: kOHCIGTDControl_DIPhase = OHCIBitRangePhase (21, 23),
384: kOHCIGTDControl_T = OHCIBitRange (24, 25),
385: kOHCIGTDControl_TPhase = OHCIBitRangePhase (24, 25),
386: kOHCIGTDControl_EC = OHCIBitRange (26, 27),
387: kOHCIGTDControl_ECPhase = OHCIBitRangePhase (26, 27),
388: kOHCIGTDControl_CC = OHCIBitRange (28, 31),
389: kOHCIGTDControl_CCPhase = OHCIBitRangePhase (28, 31),
390:
391: kOHCIGTDPIDSetup = 0,
392: kOHCIGTDPIDOut = 1,
393: kOHCIGTDPIDIn = 2,
394:
395: kOHCIGTDNoInterrupt = 7,
396:
397: kOHCIGTDDataToggleCarry = 0,
398: kOHCIGTDDataToggle0 = 2,
399: kOHCIGTDDataToggle1 = 3,
400:
401: kOHCIGTDConditionNoError = 0,
402: kOHCIGTDConditionCRC = 1,
403: kOHCIGTDConditionBitStuffing = 2,
404: kOHCIGTDConditionDataToggleMismatch = 3,
405: kOHCIGTDConditionStall = 4,
406: kOHCIGTDConditionDeviceNotResponding = 5,
407: kOHCIGTDConditionPIDCheckFailure = 6,
408: kOHCIGTDConditionUnexpectedPID = 7,
409: kOHCIGTDConditionDataOverrun = 8,
410: kOHCIGTDConditionDataUnderrun = 9,
411: kOHCIGTDConditionBufferOverrun = 12,
412: kOHCIGTDConditionBufferUnderrun = 13,
413: kOHCIGTDConditionNotAccessed = 15
414: };
415:
416: // Isochronous Transfer Descriptor
417: enum
418: {
419: kOHCIITDControl_SF = OHCIBitRange (0,15),
420: kOHCIITDControl_SFPhase = OHCIBitRangePhase(0,15),
421: kOHCIITDControl_DI = OHCIBitRange (21,23),
422: kOHCIITDControl_DIPhase = OHCIBitRangePhase (21,23),
423: kOHCIITDControl_FC = OHCIBitRange (24,26),
424: kOHCIITDControl_FCPhase = OHCIBitRangePhase (24,26),
425: kOHCIITDControl_CC = OHCIBitRange (28,31),
426: kOHCIITDControl_CCPhase = OHCIBitRangePhase (28,31),
427:
428: // The Offset/PSW words have two slightly different formats depending on whether they have been accessed
429: // by the host controller or not. They are initialized in Offset format, with 3-bit of condition code (=NOTACCESSED)
430: // if the OHCI controller accesses this frame it fills in the 4-bit condition code, and the PSW size field contains
431: // the number of bytes transferred IN, or 0 for an OUT transaction.
432:
433: // PSW format bit field definitions
434: kOHCIITDPSW_Size = OHCIBitRange(0,10),
435: kOHCIITDPSW_SizePhase = OHCIBitRangePhase(0,10),
436: kOHCIITDPSW_CC = OHCIBitRange(12,15),
437: kOHCIITDPSW_CCPhase = OHCIBitRangePhase(12,15),
438: kOHCIITDPSW_CCNA = OHCIBitRange(13,15),
439: kOHCIITDPSW_CCNAPhase = OHCIBitRangePhase(13,15),
440:
441: // offset format bit field definitions
442: kOHCIITDOffset_Size = OHCIBitRange(0,11),
443: kOHCIITDOffset_SizePhase = OHCIBitRangePhase(0,11),
444: kOHCIITDOffset_PC = OHCIBitRange(12,12),
445: kOHCIITDOffset_PCPhase = OHCIBitRangePhase(12,12),
446: kOHCIITDOffset_CC = OHCIBitRange(13,15),
447: kOHCIITDOffset_CCPhase = OHCIBitRangePhase(13,15),
448: kOHCIITDConditionNoError = 0,
449: kOHCIITDConditionCRC = 1,
450: kOHCIITDConditionBitStuffing = 2,
451: kOHCIITDConditionDataToggleMismatch = 3,
452: kOHCIITDConditionStall = 4,
453: kOHCIITDConditionDeviceNotResponding = 5,
454: kOHCIITDConditionPIDCheckFailure = 6,
455: kOHCIITDConditionUnExpectedPID = 7,
456: kOHCIITDConditionDataOverrun = 8,
457: kOHCIITDConditionDataUnderrun = 9,
458: kOHCIITDConditionBufferOverrun = 12,
459: kOHCIITDConditionBufferUnderrun = 13,
460: kOHCIITDOffsetConditionNotAccessed = 7, // note that this is the "Offset" variant (3-bit) of this condition code
461: kOHCIITDConditionNotAccessedReturn = 15,
462: kOHCIITDConditionNotCrossPage = 0,
463: kOHCIITDConditionCrossPage = 1
464: };
465:
466:
467:
468: // misc definitions -- most of these need to be cleaned up/replaced with better terms defined previously
469:
470: enum
471: {
472: // Barry, note - Root hub defines moved to OHCIRootHub.h
473:
474: kOHCIEndpointNumberOffset = 7,
475: kOHCIEndpointDirectionOffset = 11,
476: kOHCIMaxPacketSizeOffset = 16,
477: kOHCISpeedOffset = 13,
478: kOHCIBufferRoundingOffset = 18,
479: kOHCIDirectionOffset = 19,
480: kENOffset = 7,
481:
482: kUniqueNumMask = OHCIBitRange (0, 12),
483: kUniqueNumNoDirMask = OHCIBitRange (0, 10),
484: kOHCIHeadPMask = OHCIBitRange (4, 31),
485: kOHCIInterruptSOFMask = kOHCIHcInterrupt_SF,
486: kOHCISkipped = kOHCIEDControl_K,
487: kOHCIDelayIntOffset = 21,
488: kOHCIPageSize = 4096,
489: kOHCIEndpointDirectionMask = OHCIBitRange (11, 12),
490: kOHCIEDToggleBitMask = OHCIBitRange (1, 1),
491: kOHCIGTDClearErrorMask = OHCIBitRange (0, 25),
492: kHCCAalignment = 0x100, // required alignment for HCCA
493: kHCCAsize = 256 // size of HCCA
494: };
495:
496:
497: enum {
498: kOHCIBulkTransferOutType = 1,
499: kOHCIBulkTransferInType = 2,
500: kOHCIControlSetupType = 3,
501: kOHCIControlDataType = 4,
502: kOHCIControlStatusType = 5,
503: kOHCIInterruptInType = 6,
504: kOHCIInterruptOutType = 7,
505: kOHCIOptiLSBug = 8,
506: kOHCIIsochronousInType = 9,
507: kOHCIIsochronousOutType = 10
508: };
509:
510: enum {
511: kOHCIFrameOffset = 16,
512: kOHCIFmNumberMask = OHCIBitRange (0, 15),
513: kOHCIFrameOverflowBit = kOHCIBit16,
514: kOHCIMaxRetrys = 20
515:
516: };
517:
518: ////////////////////////////////////////////////////////////////////////////////
519: //
520: // OHCI UIM data records.
521: //
522:
523: //typedef short RootHubID;
524:
525: // Interrupt head struct
526: struct OHCIIntHeadStruct
527: {
528: OHCIEndpointDescriptorPtr pHead;
529: OHCIEndpointDescriptorPtr pTail;
530: UInt32 pHeadPhysical;
531: int nodeBandwidth;
532: };
533:
534: struct OHCIUIMDataStruct
535: {
536: // RegEntryID ohciRegEntryID; // Name Registry entry of OHCI.
537: // UIMID uimID; // ID for OHCI UIM.
538: // RootHubID rootHubID; // Status of root hub, if 0, not initialized otherwise has virtual ID number
539: UInt32 errataBits; // various bits for chip erratas
540: OHCIRegistersPtr pOHCIRegisters; // Pointer to base address of OHCI registers.
541: Ptr pHCCA; // Pointer to HCCA.
542: OHCIIntHead pInterruptHead[63]; // ptr to private list of all interrupts heads
543: volatile OHCIEndpointDescriptorPtr pIsochHead; // ptr to Isochtonous list
544: volatile UInt32 pIsochTail; // ptr to Isochtonous list
545: volatile UInt32 pBulkHead; // ptr to Bulk list
546: volatile UInt32 pControlHead; // ptr to Control list
547: volatile UInt32 pBulkTail; // ptr to Bulk list
548: volatile UInt32 pControlTail; // ptr to Control list
549: volatile OHCIPhysicalLogicalPtr pPhysicalLogical; // ptr to list of memory maps
550: volatile OHCIGeneralTransferDescriptorPtr pFreeTD; // list of availabble Trasfer Descriptors
551: volatile OHCIIsochTransferDescriptorPtr pFreeITD; // list of availabble Trasfer Descriptors
552: volatile OHCIEndpointDescriptorPtr pFreeED; // list of available Endpoint Descriptors
553: volatile OHCIGeneralTransferDescriptorPtr pLastFreeTD; // last of availabble Trasfer Descriptors
554: volatile OHCIIsochTransferDescriptorPtr pLastFreeITD; // last of availabble Trasfer Descriptors
555: volatile OHCIEndpointDescriptorPtr pLastFreeED; // last of available Endpoint Descriptors
556: volatile OHCIGeneralTransferDescriptorPtr pPendingTD; // list of non processed Trasfer Descriptors
557: Ptr pDataAllocation; // ptr to block used for TD, ED, ITD
558: Ptr pPCIAssignedAddresses; // ptr to PCI assigned addresses
559: UInt32 pageSize; // OS Logical page size
560: struct {
561: volatile UInt32 scheduleOverrun; // updated by the interrupt handler
562: volatile UInt32 unrecoverableError; // updated by the interrupt handler
563: volatile UInt32 frameNumberOverflow; // updated by the interrupt handler
564: volatile UInt32 ownershipChange; // updated by the interrupt handler
565: } errors;
566: volatile UInt64 frameNumber;
567: UInt16 rootHubFuncAddress; // Function Address for the root hub
568: int OptiOn;
569: UInt32 isochBandwidthAvail; // amount of available bandwidth for Isochronous transfers
570: };
571:
572: struct OHCIEndpointDescriptorStruct
573: {
574: UInt32 flags; // 0x00 control
575: PhysicalPtr tdQueueTailPtr; // 0x04 pointer to last TD (physical address)
576: PhysicalPtr tdQueueHeadPtr; // 0x08 pointer to first TD (physical)
577: PhysicalPtr nextED; // 0x0c Pointer to next ED (physical)
578: OHCIEndpointDescriptorPtr pLogicalNext; // 0x10
579: PhysicalPtr pPhysical; // 0x14
580: void* pLogicalTailP; // 0x18
581: void* pLogicalHeadP; // 0x1c
582: }; // 0x20 length of structure
583:
584: struct OHCIGeneralTransferDescriptorStruct
585: {
586: volatile UInt32 flags; // 0x00 Data controlling transfer.
587: volatile PhysicalPtr currentBufferPtr; // 0x04 Current buffer pointer (physical)
588: volatile PhysicalPtr nextTD; // 0x08 Pointer to next transfer descriptor
589: PhysicalPtr bufferEnd; // 0x0c Pointer to end of buffer (physical)
590: IOUSBCompletion completion; // only used if last TD, other wise its nil
591: OHCIEndpointDescriptorPtr pEndpoint; // pointer to TD's Endpoint
592: UInt32 pType; // 0x20 Note this must appear at the same offset (32) in GTD & ITD structs
593: PhysicalPtr pPhysical; // 0x24 Note this must appear at the same offset (36) in GTD & ITD structs
594: OHCIGeneralTransferDescriptorPtr pLogicalNext; // 0x28 Note this must appear at the same offset (40) in GTD & ITD structs
595: UInt32 bufferSize; // used only by control transfers to keep track of data buffers size leftover
596: };
597:
598: struct OHCIIsochTransferDescriptorStruct
599: {
600: UInt32 flags; // 0x00 Condition code/FrameCount/DelayInterrrupt/StartingFrame.
601: PhysicalPtr bufferPage0; // 0x04 Buffer Page 0 (physical)
602: PhysicalPtr nextTD; // 0x08 Pointer to next transfer descriptor (physical)
603: PhysicalPtr bufferEnd; // 0x0c Pointer to end of buffer (physical)
604: UInt16 offset[8];
605: UInt32 pType; // 0x20 Note this must appear at the same offset (32) in GTD & ITD structs
606: UInt32 pPhysical; // 0x24 Note this must appear at the same offset (36) in GTD & ITD structs
607: OHCIIsochTransferDescriptorPtr pLogicalNext; // 0x28 Note this must appear at the same offset (40) in GTD & ITD structs
608: IOUSBIsocCompletion completion; // callback for Isoch transactions
609: IOUSBIsocFrame * pIsocFrame; // ptr to USLs status and length array
610: UInt32 frameNum; // index to pIsocFrame array
611: };
612:
613: struct OHCIPhysicalLogicalStruct
614: {
615: UInt32 LogicalStart;
616: UInt32 LogicalEnd;
617: UInt32 PhysicalStart;
618: UInt32 PhysicalEnd;
619: UInt32 type;
620: OHCIPhysicalLogicalStruct * pNext;
621: };
622:
623: #define kOHCIPageOffsetMask ( kOHCIPageSize - 1 ) // mask off just the offset bits (low 12)
624: #define kOHCIPageMask (~(kOHCIPageOffsetMask)) // mask off just the page number (high 20)
625:
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