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1.1 root 1: /*
2: * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
3: *
4: * @APPLE_LICENSE_HEADER_START@
5: *
6: * The contents of this file constitute Original Code as defined in and
7: * are subject to the Apple Public Source License Version 1.1 (the
8: * "License"). You may not use this file except in compliance with the
9: * License. Please obtain a copy of the License at
10: * http://www.apple.com/publicsource and read it before using this file.
11: *
12: * This Original Code and all software distributed under the License are
13: * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14: * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15: * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16: * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17: * License for the specific language governing rights and limitations
18: * under the License.
19: *
20: * @APPLE_LICENSE_HEADER_END@
21: */
22: /*
23: * @OSF_COPYRIGHT@
24: */
25: /* CMU_ENDHIST */
26: /*
27: * Mach Operating System
28: * Copyright (c) 1991,1990 Carnegie Mellon University
29: * All Rights Reserved.
30: *
31: * Permission to use, copy, modify and distribute this software and its
32: * documentation is hereby granted, provided that both the copyright
33: * notice and this permission notice appear in all copies of the
34: * software, derivative works or modified versions, and any portions
35: * thereof, and that both notices appear in supporting documentation.
36: *
37: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
38: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
39: * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
40: *
41: * Carnegie Mellon requests users of this software to return to
42: *
43: * Software Distribution Coordinator or [email protected]
44: * School of Computer Science
45: * Carnegie Mellon University
46: * Pittsburgh PA 15213-3890
47: *
48: * any improvements or extensions that they make and grant Carnegie Mellon
49: * the rights to redistribute these changes.
50: */
51:
52: /*
53: */
54:
55: /*
56: * Processor registers for i386 and i486.
57: */
58: #ifndef _I386_PROC_REG_H_
59: #define _I386_PROC_REG_H_
60:
61: /*
62: * Model Specific Registers
63: */
64: #define MSR_P5_TSC 0x10 /* Time Stamp Register */
65: #define MSR_P5_CESR 0x11 /* Control and Event Select Register */
66: #define MSR_P5_CTR0 0x12 /* Counter #0 */
67: #define MSR_P5_CTR1 0x13 /* Counter #1 */
68:
69: #define MSR_P5_CESR_PC 0x0200 /* Pin Control */
70: #define MSR_P5_CESR_CC 0x01C0 /* Counter Control mask */
71: #define MSR_P5_CESR_ES 0x003F /* Event Control mask */
72:
73: #define MSR_P5_CESR_SHIFT 16 /* Shift to get Counter 1 */
74: #define MSR_P5_CESR_MASK (MSR_P5_CESR_PC|\
75: MSR_P5_CESR_CC|\
76: MSR_P5_CESR_ES) /* Mask Counter */
77:
78: #define MSR_P5_CESR_CC_CLOCK 0x0100 /* Clock Counting (otherwise Event) */
79: #define MSR_P5_CESR_CC_DISABLE 0x0000 /* Disable counter */
80: #define MSR_P5_CESR_CC_CPL012 0x0040 /* Count if the CPL == 0, 1, 2 */
81: #define MSR_P5_CESR_CC_CPL3 0x0080 /* Count if the CPL == 3 */
82: #define MSR_P5_CESR_CC_CPL 0x00C0 /* Count regardless of the CPL */
83:
84: #define MSR_P5_CESR_ES_DATA_READ 0x000000 /* Data Read */
85: #define MSR_P5_CESR_ES_DATA_WRITE 0x000001 /* Data Write */
86: #define MSR_P5_CESR_ES_DATA_RW 0x101000 /* Data Read or Write */
87: #define MSR_P5_CESR_ES_DATA_TLB_MISS 0x000010 /* Data TLB Miss */
88: #define MSR_P5_CESR_ES_DATA_READ_MISS 0x000011 /* Data Read Miss */
89: #define MSR_P5_CESR_ES_DATA_WRITE_MISS 0x000100 /* Data Write Miss */
90: #define MSR_P5_CESR_ES_DATA_RW_MISS 0x101001 /* Data Read or Write Miss */
91: #define MSR_P5_CESR_ES_HIT_EM 0x000101 /* Write (hit) to M|E state */
92: #define MSR_P5_CESR_ES_DATA_CACHE_WB 0x000110 /* Cache lines written back */
93: #define MSR_P5_CESR_ES_EXTERNAL_SNOOP 0x000111 /* External Snoop */
94: #define MSR_P5_CESR_ES_CACHE_SNOOP_HIT 0x001000 /* Data cache snoop hits */
95: #define MSR_P5_CESR_ES_MEM_ACCESS_PIPE 0x001001 /* Mem. access in both pipes */
96: #define MSR_P5_CESR_ES_BANK_CONFLICTS 0x001010 /* Bank conflicts */
97: #define MSR_P5_CESR_ES_MISALIGNED 0x001011 /* Misaligned Memory or I/O */
98: #define MSR_P5_CESR_ES_CODE_READ 0x001100 /* Code Read */
99: #define MSR_P5_CESR_ES_CODE_TLB_MISS 0x001101 /* Code TLB miss */
100: #define MSR_P5_CESR_ES_CODE_CACHE_MISS 0x001110 /* Code Cache miss */
101: #define MSR_P5_CESR_ES_SEGMENT_LOADED 0x001111 /* Any segment reg. loaded */
102: #define MSR_P5_CESR_ES_BRANCHE 0x010010 /* Branches */
103: #define MSR_P5_CESR_ES_BTB_HIT 0x010011 /* BTB Hits */
104: #define MSR_P5_CESR_ES_BRANCHE_BTB 0x010100 /* Taken branch or BTB Hit */
105: #define MSR_P5_CESR_ES_PIPELINE_FLUSH 0x010101 /* Pipeline Flushes */
106: #define MSR_P5_CESR_ES_INSTRUCTION 0x010110 /* Instruction executed */
107: #define MSR_P5_CESR_ES_INSTRUCTION_V 0x010111 /* Inst. executed (v-pipe) */
108: #define MSR_P5_CESR_ES_BUS_CYCLE 0x011000 /* Clocks while bus cycle */
109: #define MSR_P5_CESR_ES_FULL_WRITE_BUF 0x011001 /* Clocks while full wrt buf. */
110: #define MSR_P5_CESR_ES_DATA_MEM_READ 0x011010 /* Pipeline waiting for read */
111: #define MSR_P5_CESR_ES_WRITE_EM 0x011011 /* Stall on write E|M state */
112: #define MSR_P5_CESR_ES_LOCKED_CYCLE 0x011100 /* Locked bus cycles */
113: #define MSR_P5_CESR_ES_IO_CYCLE 0x011101 /* I/O Read or Write cycles */
114: #define MSR_P5_CESR_ES_NON_CACHEABLE 0x011110 /* Non-cacheable Mem. read */
115: #define MSR_P5_CESR_ES_AGI 0x011111 /* Stall because of AGI */
116: #define MSR_P5_CESR_ES_FLOP 0x100010 /* Floating Point operations */
117: #define MSR_P5_CESR_ES_BREAK_DR0 0x100011 /* Breakpoint matches on DR0 */
118: #define MSR_P5_CESR_ES_BREAK_DR1 0x100100 /* Breakpoint matches on DR1 */
119: #define MSR_P5_CESR_ES_BREAK_DR2 0x100101 /* Breakpoint matches on DR2 */
120: #define MSR_P5_CESR_ES_BREAK_DR3 0x100110 /* Breakpoint matches on DR3 */
121: #define MSR_P5_CESR_ES_HARDWARE_IT 0x100111 /* Hardware interrupts */
122:
123: /*
124: * CR0
125: */
126: #define CR0_PG 0x80000000 /* Enable paging */
127: #define CR0_CD 0x40000000 /* i486: Cache disable */
128: #define CR0_NW 0x20000000 /* i486: No write-through */
129: #define CR0_AM 0x00040000 /* i486: Alignment check mask */
130: #define CR0_WP 0x00010000 /* i486: Write-protect kernel access */
131: #define CR0_NE 0x00000020 /* i486: Handle numeric exceptions */
132: #define CR0_ET 0x00000010 /* Extension type is 80387 */
133: /* (not official) */
134: #define CR0_TS 0x00000008 /* Task switch */
135: #define CR0_EM 0x00000004 /* Emulate coprocessor */
136: #define CR0_MP 0x00000002 /* Monitor coprocessor */
137: #define CR0_PE 0x00000001 /* Enable protected mode */
138:
139: /*
140: * CR4
141: */
142: #define CR4_MCE 0x00000040 /* p5: Machine Check Exceptions */
143: #define CR4_PSE 0x00000010 /* p5: Page Size Extensions */
144: #define CR4_DE 0x00000008 /* p5: Debugging Extensions */
145: #define CR4_TSD 0x00000004 /* p5: Time Stamp Disable */
146: #define CR4_PVI 0x00000002 /* p5: Protected-mode Virtual Interrupts */
147: #define CR4_VME 0x00000001 /* p5: Virtual-8086 Mode Extensions */
148:
149: #ifndef ASSEMBLER
150: extern unsigned int get_cr0(void);
151: extern void set_cr0(
152: unsigned int value);
153: extern unsigned int get_cr2(void);
154: extern unsigned int get_cr3(void);
155: extern void set_cr3(
156: unsigned int value);
157: extern unsigned int get_cr4(void);
158: extern void set_cr4(
159: unsigned int value);
160:
161: #define set_ts() \
162: set_cr0(get_cr0() | CR0_TS)
163: extern void clear_ts(void);
164:
165: extern unsigned short get_tr(void);
166: extern void set_tr(
167: unsigned int seg);
168:
169: extern unsigned short get_ldt(void);
170: extern void set_ldt(
171: unsigned int seg);
172: #ifdef __GNUC__
173: extern __inline__ unsigned int get_cr0(void)
174: {
175: register unsigned int cr0;
176: __asm__ volatile("mov %%cr0, %0" : "=r" (cr0));
177: return(cr0);
178: }
179:
180: extern __inline__ void set_cr0(unsigned int value)
181: {
182: __asm__ volatile("mov %0, %%cr0" : : "r" (value));
183: }
184:
185: extern __inline__ unsigned int get_cr2(void)
186: {
187: register unsigned int cr2;
188: __asm__ volatile("mov %%cr2, %0" : "=r" (cr2));
189: return(cr2);
190: }
191:
192: #if NCPUS > 1 && AT386
193: /*
194: * get_cr3 and set_cr3 are more complicated for the MPs. cr3 is where
195: * the cpu number gets stored. The MP versions live in locore.s
196: */
197: #else /* NCPUS > 1 && AT386 */
198: extern __inline__ unsigned int get_cr3(void)
199: {
200: register unsigned int cr3;
201: __asm__ volatile("mov %%cr3, %0" : "=r" (cr3));
202: return(cr3);
203: }
204:
205: extern __inline__ void set_cr3(unsigned int value)
206: {
207: __asm__ volatile("mov %0, %%cr3" : : "r" (value));
208: }
209: #endif /* NCPUS > 1 && AT386 */
210:
211: extern __inline__ void clear_ts(void)
212: {
213: __asm__ volatile("clts");
214: }
215:
216: extern __inline__ unsigned short get_tr(void)
217: {
218: unsigned short seg;
219: __asm__ volatile("str %0" : "=rm" (seg));
220: return(seg);
221: }
222:
223: extern __inline__ void set_tr(unsigned int seg)
224: {
225: __asm__ volatile("ltr %0" : : "rm" ((unsigned short)(seg)));
226: }
227:
228: extern __inline__ unsigned short get_ldt(void)
229: {
230: unsigned short seg;
231: __asm__ volatile("sldt %0" : "=rm" (seg));
232: return(seg);
233: }
234:
235: extern __inline__ void set_ldt(unsigned int seg)
236: {
237: __asm__ volatile("lldt %0" : : "rm" ((unsigned short)(seg)));
238: }
239:
240: extern __inline__ void flush_tlb(void)
241: {
242: unsigned long cr3_temp;
243: __asm__ volatile("movl %%cr3, %0; movl %0, %%cr3" : "=r" (cr3_temp) :: "memory");
244: }
245:
246: extern __inline__ void invlpg(unsigned long addr)
247: {
248: __asm__ volatile("invlpg (%0)" :: "r" (addr) : "memory");
249: }
250: #endif /* __GNUC__ */
251: #endif /* ASSEMBLER */
252:
253: #endif /* _I386_PROC_REG_H_ */
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