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1.1 root 1: /*
2: * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
3: *
4: * @APPLE_LICENSE_HEADER_START@
5: *
6: * The contents of this file constitute Original Code as defined in and
7: * are subject to the Apple Public Source License Version 1.1 (the
8: * "License"). You may not use this file except in compliance with the
9: * License. Please obtain a copy of the License at
10: * http://www.apple.com/publicsource and read it before using this file.
11: *
12: * This Original Code and all software distributed under the License are
13: * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14: * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15: * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16: * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17: * License for the specific language governing rights and limitations
18: * under the License.
19: *
20: * @APPLE_LICENSE_HEADER_END@
21: */
22: /*
23: * File: mach/ppc/processor_info.h
24: *
25: * Data structure definitions for ppc specific processor control
26: */
27:
28:
29: #ifndef _MACH_PPC_PROCESSOR_INFO_H_
30: #define _MACH_PPC_PROCESSOR_INFO_H_
31:
32: #include <mach/machine.h>
33:
34: /* processor_control command operations */
35: #define PROCESSOR_PM_SET_REGS 1 /* Set Performance Monitor Registers */
36: #define PROCESSOR_PM_SET_MMCR 2 /* Set Monitor Mode Controls Registers */
37: #define PROCESSOR_PM_CLR_PMC 3 /* Clear Performance Monitor Counter Registers */
38:
39: /*
40: * Performance Monitor Register structures
41: */
42:
43: typedef union {
44: unsigned int word;
45: struct {
46: unsigned int dis : 1;
47: unsigned int dp : 1;
48: unsigned int du : 1;
49: unsigned int dms : 1;
50: unsigned int dmr : 1;
51: unsigned int reserved3 : 1; /* enint */
52: unsigned int reserved4 : 1; /* discount */
53: unsigned int reserved5 : 2; /* rtcselect */
54: unsigned int reserved6 : 1; /* intonbittrans */
55: unsigned int threshold : 6;
56: unsigned int reserved7 : 1; /* pmc1intcontrol */
57: unsigned int reserved8 : 1; /* pmcintcontrol */
58: unsigned int reserved9 : 1; /* pmctrigger */
59: unsigned int pmc1select : 7;
60: unsigned int pmc2select : 6;
61: }bits;
62: }mmcr0_t;
63:
64: typedef union {
65: unsigned int word;
66: struct {
67: unsigned int pmc3select : 5;
68: unsigned int pmc4select : 5;
69: unsigned int reserved : 22;
70: }bits;
71: }mmcr1_t;
72:
73: typedef union {
74: unsigned int word;
75: struct {
76: unsigned int threshmult : 1;
77: unsigned int reserved : 31;
78: }bits;
79: }mmcr2_t;
80:
81: typedef union {
82: unsigned int word;
83: struct {
84: unsigned int ov : 1; /* overflow value */
85: unsigned int cv : 31; /* countervalue */
86: }bits;
87: }pmcn_t;
88:
89:
90:
91: /* Processor Performance Monitor Registers definitions */
92:
93: struct processor_pm_regs {
94: union {
95: mmcr0_t mmcr0;
96: mmcr1_t mmcr1;
97: mmcr2_t mmcr2;
98: }u;
99: pmcn_t pmc[2];
100: };
101:
102: typedef struct processor_pm_regs processor_pm_regs_data_t;
103: typedef struct processor_pm_regs *processor_pm_regs_t;
104: #define PROCESSOR_PM_REGS_COUNT \
105: (sizeof(processor_pm_regs_data_t) / sizeof (unsigned int))
106:
107: #define PROCESSOR_PM_REGS_COUNT_POWERPC_604 \
108: (PROCESSOR_PM_REGS_COUNT * 1 )
109:
110: #define PROCESSOR_PM_REGS_COUNT_POWERPC_604e \
111: (PROCESSOR_PM_REGS_COUNT * 2 )
112:
113: #define PROCESSOR_PM_REGS_COUNT_POWERPC_750 \
114: (PROCESSOR_PM_REGS_COUNT * 2 )
115:
116: #define PROCESSOR_PM_REGS_COUNT_POWERPC_Max \
117: (PROCESSOR_PM_REGS_COUNT * 3 )
118:
119:
120: union processor_control_data {
121: processor_pm_regs_data_t cmd_pm_regs[3];
122: };
123:
124: struct processor_control_cmd {
125: integer_t cmd_op;
126: cpu_type_t cmd_cpu_type;
127: cpu_subtype_t cmd_cpu_subtype;
128: union processor_control_data u;
129: };
130:
131: typedef struct processor_control_cmd processor_control_cmd_data_t;
132: typedef struct processor_control_cmd *processor_control_cmd_t;
133: #define cmd_pm_regs u.cmd_pm_regs;
134: #define cmd_pm_ctls u.cmd_pm_ctls;
135:
136: #define PROCESSOR_CONTROL_CMD_COUNT \
137: (((sizeof(processor_control_cmd_data_t)) - \
138: (sizeof(union processor_control_data))) / sizeof (integer_t))
139:
140: /* x should be a processor_pm_regs_t */
141: #define PERFMON_MMCR0(x) ((x)[0].u.mmcr0.word)
142: #define PERFMON_PMC1(x) ((x)[0].pmc[0].word)
143: #define PERFMON_PMC2(x) ((x)[0].pmc[1].word)
144: #define PERFMON_MMCR1(x) ((x)[1].u.mmcr1.word)
145: #define PERFMON_PMC3(x) ((x)[1].pmc[0].word)
146: #define PERFMON_PMC4(x) ((x)[1].pmc[1].word)
147: #define PERFMON_MMCR2(x) ((x)[2].u.mmcr2.word)
148:
149: #define PERFMON_DIS(x) ((x)[0].u.mmcr0.bits.dis)
150: #define PERFMON_DP(x) ((x)[0].u.mmcr0.bits.dp)
151: #define PERFMON_DU(x) ((x)[0].u.mmcr0.bits.du)
152: #define PERFMON_DMS(x) ((x)[0].u.mmcr0.bits.dms)
153: #define PERFMON_DMR(x) ((x)[0].u.mmcr0.bits.dmr)
154: #define PERFMON_THRESHOLD(x) ((x)[0].u.mmcr0.bits.threshold)
155: #define PERFMON_PMC1SELECT(x) ((x)[0].u.mmcr0.bits.pmc1select)
156: #define PERFMON_PMC2SELECT(x) ((x)[0].u.mmcr0.bits.pmc2select)
157: #define PERFMON_PMC3SELECT(x) ((x)[1].u.mmcr1.bits.pmc3select)
158: #define PERFMON_PMC4SELECT(x) ((x)[1].u.mmcr1.bits.pmc4select)
159: #define PERFMON_THRESHMULT(x) ((x)[2].u.mmcr2.bits.threshmult)
160: #define PERFMON_PMC1_CV(x) ((x)[0].u.pmc[0].bits.cv)
161: #define PERFMON_PMC2_CV(x) ((x)[0].u.pmc[1].bits.cv)
162: #define PERFMON_PMC3_CV(x) ((x)[1].u.pmc[0].bits.cv)
163: #define PERFMON_PMC4_CV(x) ((x)[1].u.pmc[1].bits.cv)
164:
165: #endif /* _MACH_PPC_PROCESSOR_INFO_H_ */
166:
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