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Annotation of XNU/osfmk/ppc/POWERMAC/scc_8530.h, revision 1.1

1.1     ! root        1: /*
        !             2:  * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
        !             3:  *
        !             4:  * @APPLE_LICENSE_HEADER_START@
        !             5:  * 
        !             6:  * The contents of this file constitute Original Code as defined in and
        !             7:  * are subject to the Apple Public Source License Version 1.1 (the
        !             8:  * "License").  You may not use this file except in compliance with the
        !             9:  * License.  Please obtain a copy of the License at
        !            10:  * http://www.apple.com/publicsource and read it before using this file.
        !            11:  * 
        !            12:  * This Original Code and all software distributed under the License are
        !            13:  * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
        !            14:  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
        !            15:  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
        !            16:  * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
        !            17:  * License for the specific language governing rights and limitations
        !            18:  * under the License.
        !            19:  * 
        !            20:  * @APPLE_LICENSE_HEADER_END@
        !            21:  */
        !            22: /*
        !            23:  * @OSF_COPYRIGHT@
        !            24:  */
        !            25: /*
        !            26:  * @APPLE_FREE_COPYRIGHT@
        !            27:  */
        !            28: /* 
        !            29:  * Mach Operating System
        !            30:  * Copyright (c) 1991,1990,1989 Carnegie Mellon University
        !            31:  * All Rights Reserved.
        !            32:  * 
        !            33:  * Permission to use, copy, modify and distribute this software and its
        !            34:  * documentation is hereby granted, provided that both the copyright
        !            35:  * notice and this permission notice appear in all copies of the
        !            36:  * software, derivative works or modified versions, and any portions
        !            37:  * thereof, and that both notices appear in supporting documentation.
        !            38:  * 
        !            39:  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
        !            40:  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
        !            41:  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
        !            42:  * 
        !            43:  * Carnegie Mellon requests users of this software to return to
        !            44:  * 
        !            45:  *  Software Distribution Coordinator  or  [email protected]
        !            46:  *  School of Computer Science
        !            47:  *  Carnegie Mellon University
        !            48:  *  Pittsburgh PA 15213-3890
        !            49:  * 
        !            50:  * any improvements or extensions that they make and grant Carnegie Mellon
        !            51:  * the rights to redistribute these changes.
        !            52:  */
        !            53: /*
        !            54:  */
        !            55: /*
        !            56:  *     File: scc_8530.h
        !            57:  *     Author: Alessandro Forin, Carnegie Mellon University
        !            58:  *     Date:   6/91
        !            59:  *
        !            60:  *     Definitions for the Zilog Z8530 SCC serial line chip
        !            61:  */
        !            62: 
        !            63: #ifndef        _SCC_8530_H_
        !            64: #define        _SCC_8530_H_
        !            65: 
        !            66: /*
        !            67:  * Register map, needs definition of the alignment
        !            68:  * used on the specific machine.
        !            69:  * #define the 'scc_register_t' data type before
        !            70:  * including this header file.  For restrictions on
        !            71:  * access modes define the set/get_datum macros.
        !            72:  * We provide defaults ifnot.
        !            73:  */
        !            74: 
        !            75: 
        !            76: #define        SCC_CHANNEL_A   1
        !            77: #define        SCC_CHANNEL_B   0
        !            78: 
        !            79: #define        SCC_MODEM       SCC_CHANNEL_A
        !            80: #define        SCC_PRINTER     SCC_CHANNEL_B
        !            81: 
        !            82: #define        SCC_DATA_OFFSET 4
        !            83: 
        !            84: typedef unsigned char *scc_regmap_t;
        !            85: 
        !            86: extern void    powermac_scc_set_datum(scc_regmap_t regs, unsigned int offset, unsigned char value);
        !            87: extern unsigned char powermac_scc_get_datum(scc_regmap_t regs, unsigned int offset);
        !            88: 
        !            89: #define scc_set_datum(regs, d, v)      powermac_scc_set_datum(regs, (d), (v))
        !            90: #define        scc_get_datum(regs, d,v)        (v)  = powermac_scc_get_datum(regs, (d));
        !            91: 
        !            92: #define        scc_init_reg(regs,chan)         { \
        !            93:                char tmp; \
        !            94:                scc_get_datum(regs, ((chan)<<1),tmp); \
        !            95:                scc_get_datum(regs, ((chan)<<1),tmp); \
        !            96:        }
        !            97: 
        !            98: #define        scc_read_reg(regs,chan,reg,val) { \
        !            99:                scc_set_datum(regs, ((chan)<<1),reg); \
        !           100:                scc_get_datum(regs, ((chan)<<1),val); \
        !           101:        }
        !           102: 
        !           103: #define        scc_read_reg_zero(regs,chan,val)        { \
        !           104:                scc_get_datum(regs, ((chan)<<1),val); \
        !           105:        }
        !           106: 
        !           107: #define        scc_write_reg(regs,chan,reg,val)        { \
        !           108:                scc_set_datum(regs, ((chan)<<1),reg); \
        !           109:                scc_set_datum(regs, ((chan)<<1),val); \
        !           110:        }
        !           111: 
        !           112: #define        scc_write_reg_zero(regs,chan,val) { \
        !           113:                scc_set_datum(regs, ((chan)<<1),val); \
        !           114:        }
        !           115: 
        !           116: #define        scc_read_data(regs,chan,val)    { \
        !           117:                scc_get_datum(regs, ((chan)<<1)+SCC_DATA_OFFSET,val); \
        !           118:        }
        !           119: 
        !           120: #define        scc_write_data(regs,chan,val) { \
        !           121:                scc_set_datum(regs, ((chan)<<1)+SCC_DATA_OFFSET,val); \
        !           122:        }
        !           123: 
        !           124: 
        !           125: /*
        !           126:  * Addressable registers
        !           127:  */
        !           128: 
        !           129: #define        SCC_RR0         0       /* status register */
        !           130: #define        SCC_RR1         1       /* special receive conditions */
        !           131: #define        SCC_RR2         2       /* (modified) interrupt vector */
        !           132: #define        SCC_RR3         3       /* interrupts pending (cha A only) */
        !           133: #define        SCC_RR8         8       /* recv buffer (alias for data) */
        !           134: #define        SCC_RR10        10      /* sdlc status */
        !           135: #define        SCC_RR12        12      /* BRG constant, low part */
        !           136: #define        SCC_RR13        13      /* BRG constant, high part */
        !           137: #define        SCC_RR15        15      /* interrupts currently enabled */
        !           138: 
        !           139: #define        SCC_WR0         0       /* reg select, and commands */
        !           140: #define        SCC_WR1         1       /* interrupt and DMA enables */
        !           141: #define        SCC_WR2         2       /* interrupt vector */
        !           142: #define        SCC_WR3         3       /* receiver params and enables */
        !           143: #define        SCC_WR4         4       /* clock/char/parity params */
        !           144: #define        SCC_WR5         5       /* xmit params and enables */
        !           145: #define        SCC_WR6         6       /* synchr SYNCH/address */
        !           146: #define        SCC_WR7         7       /* synchr SYNCH/flag */
        !           147: #define        SCC_WR8         8       /* xmit buffer (alias for data) */
        !           148: #define        SCC_WR9         9       /* vectoring and resets */
        !           149: #define        SCC_WR10        10      /* synchr params */
        !           150: #define        SCC_WR11        11      /* clocking definitions */
        !           151: #define        SCC_WR12        12      /* BRG constant, low part */
        !           152: #define        SCC_WR13        13      /* BRG constant, high part */
        !           153: #define        SCC_WR14        14      /* BRG enables and commands */
        !           154: #define        SCC_WR15        15      /* interrupt enables */
        !           155: 
        !           156: /*
        !           157:  * Read registers defines
        !           158:  */
        !           159: 
        !           160: #define        SCC_RR0_BREAK           0x80    /* break detected (rings twice), or */
        !           161: #define        SCC_RR0_ABORT           0x80    /* abort (synchr) */
        !           162: #define        SCC_RR0_TX_UNDERRUN     0x40    /* xmit buffer empty/end of message */
        !           163: #define        SCC_RR0_CTS             0x20    /* clear-to-send pin active (sampled
        !           164:                                           only on intr and after RESI cmd */
        !           165: #define        SCC_RR0_SYNCH           0x10    /* SYNCH found/still hunting */
        !           166: #define        SCC_RR0_DCD             0x08    /* carrier-detect (same as CTS) */
        !           167: #define        SCC_RR0_TX_EMPTY        0x04    /* xmit buffer empty */
        !           168: #define        SCC_RR0_ZERO_COUNT      0x02    /* ? */
        !           169: #define        SCC_RR0_RX_AVAIL        0x01    /* recv fifo not empty */
        !           170: 
        !           171: #define        SCC_RR1_EOF             0x80    /* end-of-frame, SDLC mode */
        !           172: #define        SCC_RR1_CRC_ERR         0x40    /* incorrect CRC or.. */
        !           173: #define        SCC_RR1_FRAME_ERR       0x40    /* ..bad frame */
        !           174: #define        SCC_RR1_RX_OVERRUN      0x20    /* rcv fifo overflow */
        !           175: #define        SCC_RR1_PARITY_ERR      0x10    /* incorrect parity in data */
        !           176: #define        SCC_RR1_RESIDUE0        0x08
        !           177: #define        SCC_RR1_RESIDUE1        0x04
        !           178: #define        SCC_RR1_RESIDUE2        0x02
        !           179: #define        SCC_RR1_ALL_SENT        0x01
        !           180: 
        !           181: /* RR2 contains the interrupt vector unmodified (channel A) or
        !           182:    modified as follows (channel B, if vector-include-status) */
        !           183: 
        !           184: #define        SCC_RR2_STATUS(val)     ((val)&0xe)     /* 11/7/95 used to be 0xf */
        !           185: 
        !           186: #define        SCC_RR2_B_XMIT_DONE     0x0
        !           187: #define        SCC_RR2_B_EXT_STATUS    0x2
        !           188: #define        SCC_RR2_B_RECV_DONE     0x4
        !           189: #define        SCC_RR2_B_RECV_SPECIAL  0x6
        !           190: #define        SCC_RR2_A_XMIT_DONE     0x8
        !           191: #define        SCC_RR2_A_EXT_STATUS    0xa
        !           192: #define        SCC_RR2_A_RECV_DONE     0xc
        !           193: #define        SCC_RR2_A_RECV_SPECIAL  0xe
        !           194: 
        !           195: /* Interrupts pending, to be read from channel A only (B raz) */
        !           196: #define        SCC_RR3_zero            0xc0
        !           197: #define        SCC_RR3_RX_IP_A         0x20
        !           198: #define        SCC_RR3_TX_IP_A         0x10
        !           199: #define        SCC_RR3_EXT_IP_A        0x08
        !           200: #define        SCC_RR3_RX_IP_B         0x04
        !           201: #define        SCC_RR3_TX_IP_B         0x02
        !           202: #define        SCC_RR3_EXT_IP_B        0x01
        !           203: 
        !           204: /* RR8 is the receive data buffer, a 3 deep FIFO */
        !           205: #define        SCC_RECV_BUFFER         SCC_RR8
        !           206: #define        SCC_RECV_FIFO_DEEP      3
        !           207: 
        !           208: #define        SCC_RR10_1CLKS          0x80
        !           209: #define        SCC_RR10_2CLKS          0x40
        !           210: #define        SCC_RR10_zero           0x2d
        !           211: #define        SCC_RR10_LOOP_SND       0x10
        !           212: #define        SCC_RR10_ON_LOOP        0x02
        !           213: 
        !           214: /* RR12/RR13 hold the timing base, upper byte in RR13 */
        !           215: 
        !           216: #define        scc_get_timing_base(scc,chan,val)       { \
        !           217:                register char   tmp;    \
        !           218:                scc_read_reg(scc,chan,SCC_RR12,val);\
        !           219:                scc_read_reg(scc,chan,SCC_RR13,tmp);\
        !           220:                (val) = ((val)<<8)|(tmp&0xff);\
        !           221:        }
        !           222: 
        !           223: #define        SCC_RR15_BREAK_IE       0x80
        !           224: #define        SCC_RR15_TX_UNDERRUN_IE 0x40
        !           225: #define        SCC_RR15_CTS_IE         0x20
        !           226: #define        SCC_RR15_SYNCH_IE       0x10
        !           227: #define        SCC_RR15_DCD_IE         0x08
        !           228: #define        SCC_RR15_zero           0x05
        !           229: #define        SCC_RR15_ZERO_COUNT_IE  0x02
        !           230: 
        !           231: 
        !           232: /*
        !           233:  * Write registers defines
        !           234:  */
        !           235: 
        !           236: /* WR0 is used for commands too */
        !           237: #define        SCC_RESET_TXURUN_LATCH  0xc0
        !           238: #define        SCC_RESET_TX_CRC        0x80
        !           239: #define        SCC_RESET_RX_CRC        0x40
        !           240: #define        SCC_RESET_HIGHEST_IUS   0x38    /* channel A only */
        !           241: #define        SCC_RESET_ERROR         0x30
        !           242: #define        SCC_RESET_TX_IP         0x28
        !           243: #define        SCC_IE_NEXT_CHAR        0x20
        !           244: #define        SCC_SEND_SDLC_ABORT     0x18
        !           245: #define        SCC_RESET_EXT_IP        0x10
        !           246: 
        !           247: #define        SCC_WR1_DMA_ENABLE      0x80    /* dma control */
        !           248: #define        SCC_WR1_DMA_MODE        0x40    /* drive ~req for DMA controller */
        !           249: #define        SCC_WR1_DMA_RECV_DATA   0x20    /* from wire to host memory */
        !           250:                                        /* interrupt enable/conditions */
        !           251: #define        SCC_WR1_RXI_SPECIAL_O   0x18    /* on special only */
        !           252: #define        SCC_WR1_RXI_ALL_CHAR    0x10    /* on each char, or special */
        !           253: #define        SCC_WR1_RXI_FIRST_CHAR  0x08    /* on first char, or special */
        !           254: #define        SCC_WR1_RXI_DISABLE     0x00    /* never on recv */
        !           255: #define        SCC_WR1_PARITY_IE       0x04    /* on parity errors */
        !           256: #define        SCC_WR1_TX_IE           0x02
        !           257: #define        SCC_WR1_EXT_IE          0x01
        !           258: 
        !           259: /* WR2 is common and contains the interrupt vector (high nibble) */
        !           260: 
        !           261: #define        SCC_WR3_RX_8_BITS       0xc0
        !           262: #define        SCC_WR3_RX_6_BITS       0x80
        !           263: #define        SCC_WR3_RX_7_BITS       0x40
        !           264: #define        SCC_WR3_RX_5_BITS       0x00
        !           265: #define        SCC_WR3_AUTO_ENABLE     0x20
        !           266: #define        SCC_WR3_HUNT_MODE       0x10
        !           267: #define        SCC_WR3_RX_CRC_ENABLE   0x08
        !           268: #define        SCC_WR3_SDLC_SRCH       0x04
        !           269: #define        SCC_WR3_INHIBIT_SYNCH   0x02
        !           270: #define        SCC_WR3_RX_ENABLE       0x01
        !           271: 
        !           272: /* Should be re-written after reset */
        !           273: #define        SCC_WR4_CLK_x64         0xc0    /* clock divide factor */
        !           274: #define        SCC_WR4_CLK_x32         0x80
        !           275: #define        SCC_WR4_CLK_x16         0x40
        !           276: #define        SCC_WR4_CLK_x1          0x00
        !           277: #define        SCC_WR4_EXT_SYNCH_MODE  0x30    /* synch modes */
        !           278: #define        SCC_WR4_SDLC_MODE       0x20
        !           279: #define        SCC_WR4_16BIT_SYNCH     0x10
        !           280: #define        SCC_WR4_8BIT_SYNCH      0x00
        !           281: #define        SCC_WR4_2_STOP          0x0c    /* asynch modes */
        !           282: #define        SCC_WR4_1_5_STOP        0x08
        !           283: #define        SCC_WR4_1_STOP          0x04
        !           284: #define        SCC_WR4_SYNCH_MODE      0x00
        !           285: #define        SCC_WR4_EVEN_PARITY     0x02
        !           286: #define        SCC_WR4_PARITY_ENABLE   0x01
        !           287: 
        !           288: #define        SCC_WR5_DTR             0x80    /* drive DTR pin */
        !           289: #define        SCC_WR5_TX_8_BITS       0x60
        !           290: #define        SCC_WR5_TX_6_BITS       0x40
        !           291: #define        SCC_WR5_TX_7_BITS       0x20
        !           292: #define        SCC_WR5_TX_5_BITS       0x00
        !           293: #define        SCC_WR5_SEND_BREAK      0x10
        !           294: #define        SCC_WR5_TX_ENABLE       0x08
        !           295: #define        SCC_WR5_CRC_16          0x04    /* CRC if non zero, .. */
        !           296: #define        SCC_WR5_SDLC            0x00    /* ..SDLC otherwise  */
        !           297: #define        SCC_WR5_RTS             0x02    /* drive RTS pin */
        !           298: #define        SCC_WR5_TX_CRC_ENABLE   0x01
        !           299: 
        !           300: /* Registers WR6 and WR7 are for synch modes data, with among other things: */
        !           301: 
        !           302: #define        SCC_WR6_BISYNCH_12      0x0f
        !           303: #define        SCC_WR6_SDLC_RANGE_MASK 0x0f
        !           304: #define        SCC_WR7_SDLC_FLAG       0x7e
        !           305: 
        !           306: /* Register WR7' (prime) controls some ESCC features */
        !           307: #define SCC_WR7P_RX_FIFO       0x08    /* Enable interrupt on FIFO 1/2 full */
        !           308: 
        !           309: /* WR8 is the transmit data buffer (no FIFO) */
        !           310: #define        SCC_XMT_BUFFER          SCC_WR8
        !           311: 
        !           312: #define        SCC_WR9_HW_RESET        0xc0    /* force hardware reset */
        !           313: #define        SCC_WR9_RESET_CHA_A     0x80
        !           314: #define        SCC_WR9_RESET_CHA_B     0x40
        !           315: #define        SCC_WR9_NON_VECTORED    0x20    /* mbz for Zilog chip */
        !           316: #define        SCC_WR9_STATUS_HIGH     0x10
        !           317: #define        SCC_WR9_MASTER_IE       0x08
        !           318: #define        SCC_WR9_DLC             0x04    /* disable-lower-chain */
        !           319: #define        SCC_WR9_NV              0x02    /* no vector */
        !           320: #define        SCC_WR9_VIS             0x01    /* vector-includes-status */
        !           321: 
        !           322: #define        SCC_WR10_CRC_PRESET     0x80
        !           323: #define        SCC_WR10_FM0            0x60
        !           324: #define        SCC_WR10_FM1            0x40
        !           325: #define        SCC_WR10_NRZI           0x20
        !           326: #define        SCC_WR10_NRZ            0x00
        !           327: #define        SCC_WR10_ACTIVE_ON_POLL 0x10
        !           328: #define        SCC_WR10_MARK_IDLE      0x08    /* flag if zero */
        !           329: #define        SCC_WR10_ABORT_ON_URUN  0x04    /* flag if zero */
        !           330: #define        SCC_WR10_LOOP_MODE      0x02
        !           331: #define        SCC_WR10_6BIT_SYNCH     0x01
        !           332: #define        SCC_WR10_8BIT_SYNCH     0x00
        !           333: 
        !           334: #define        SCC_WR11_RTxC_XTAL      0x80    /* RTxC pin is input (ext oscill) */
        !           335: #define        SCC_WR11_RCLK_DPLL      0x60    /* clock received data on dpll */
        !           336: #define        SCC_WR11_RCLK_BAUDR     0x40    /* .. on BRG */
        !           337: #define        SCC_WR11_RCLK_TRc_PIN   0x20    /* .. on TRxC pin */
        !           338: #define        SCC_WR11_RCLK_RTc_PIN   0x00    /* .. on RTxC pin */
        !           339: #define        SCC_WR11_XTLK_DPLL      0x18
        !           340: #define        SCC_WR11_XTLK_BAUDR     0x10
        !           341: #define        SCC_WR11_XTLK_TRc_PIN   0x08
        !           342: #define        SCC_WR11_XTLK_RTc_PIN   0x00
        !           343: #define        SCC_WR11_TRc_OUT        0x04    /* drive TRxC pin as output from..*/
        !           344: #define        SCC_WR11_TRcOUT_DPLL    0x03    /* .. the dpll */
        !           345: #define        SCC_WR11_TRcOUT_BAUDR   0x02    /* .. the BRG */
        !           346: #define        SCC_WR11_TRcOUT_XMTCLK  0x01    /* .. the xmit clock */
        !           347: #define        SCC_WR11_TRcOUT_XTAL    0x00    /* .. the external oscillator */
        !           348: 
        !           349: /* WR12/WR13 are for timing base preset */
        !           350: #define        scc_set_timing_base(scc,chan,val)       { \
        !           351:                scc_write_reg(scc,chan,SCC_RR12,val);\
        !           352:                scc_write_reg(scc,chan,SCC_RR13,(val)>>8);\
        !           353:        }
        !           354: 
        !           355: /* More commands in this register */
        !           356: #define        SCC_WR14_NRZI_MODE      0xe0    /* synch modulations */
        !           357: #define        SCC_WR14_FM_MODE        0xc0
        !           358: #define        SCC_WR14_RTc_SOURCE     0xa0    /* clock is from pin .. */
        !           359: #define        SCC_WR14_BAUDR_SOURCE   0x80    /* .. or internal BRG */
        !           360: #define        SCC_WR14_DISABLE_DPLL   0x60
        !           361: #define        SCC_WR14_RESET_CLKMISS  0x40
        !           362: #define        SCC_WR14_SEARCH_MODE    0x20
        !           363: /* ..and more bitsy */
        !           364: #define        SCC_WR14_LOCAL_LOOPB    0x10
        !           365: #define        SCC_WR14_AUTO_ECHO      0x08
        !           366: #define        SCC_WR14_DTR_REQUEST    0x04
        !           367: #define        SCC_WR14_BAUDR_SRC      0x02
        !           368: #define        SCC_WR14_BAUDR_ENABLE   0x01
        !           369: 
        !           370: #define        SCC_WR15_BREAK_IE       0x80
        !           371: #define        SCC_WR15_TX_UNDERRUN_IE 0x40
        !           372: #define        SCC_WR15_CTS_IE         0x20
        !           373: #define        SCC_WR15_SYNCHUNT_IE    0x10
        !           374: #define        SCC_WR15_DCD_IE         0x08
        !           375: #define        SCC_WR15_zero           0x05
        !           376: #define        SCC_WR15_ZERO_COUNT_IE  0x02
        !           377: #define SCC_WR15_ENABLE_ESCC   0x01    /* Enable some ESCC registers */
        !           378: 
        !           379: #define        NSCC_LINE               2       /* How many lines are support per 8530 */
        !           380: /*
        !           381:  * Driver status
        !           382:  */
        !           383: 
        !           384: #define        SCC_FLAGS_DMA_PAUSED    0x00001         /* DMA has been paused because of XON/XOFF */
        !           385: #define        SCC_FLAGS_DMA_TX_BUSY   0x00002         /* On going DMA operation.. */
        !           386: 
        !           387: struct scc_softreg {
        !           388:        unsigned char   wr1;
        !           389:        unsigned char   wr4;
        !           390:        unsigned char   wr5;
        !           391:        unsigned char   wr14;
        !           392: 
        !           393:        unsigned long   speed;
        !           394:        unsigned long   flags;
        !           395:        unsigned long   dma_flags;
        !           396: };
        !           397: 
        !           398: 
        !           399: struct scc_softc {
        !           400:        scc_regmap_t            regs;
        !           401:        struct scc_dma_ops      *dma_ops;
        !           402: 
        !           403:        /* software copy of some write regs, for reg |= */
        !           404:        struct scc_softreg softr[NSCC_LINE];
        !           405: 
        !           406:        int             flags;
        !           407:        int             modem[NSCC_LINE]; /* Mach modem bits (TM_DTR etc). */
        !           408:        int             dcd_timer[NSCC_LINE];
        !           409:        int             dma_initted;
        !           410: 
        !           411:        char            polling_mode;
        !           412:        char            probed_once;
        !           413: 
        !           414:        boolean_t               full_modem;
        !           415: };
        !           416: 
        !           417: #define DCD_TIMEOUT 4
        !           418: 
        !           419: typedef struct scc_softc *scc_softc_t;
        !           420: extern struct scc_softc                scc_softc[];
        !           421: 
        !           422: #endif /*_SCC_8530_H_*/

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